TW202335319A - Semiconductor light-emitting device - Google Patents

Abstract

A semiconductor light-emitting device includes a semiconductor stack; a recess region; a first protective structure formed on the semiconductor stack, and including a first upper surface and a bending region formed corresponding to the recess region, wherein the first protective structure includes a seam; and a second protective structure disposed in the seam.

Description

Semiconductor light emitting element

This case relates to a semiconductor component, especially a semiconductor light-emitting component.

Light-Emitting Diode (LED) has good characteristics such as low energy consumption, low heat generation, long operating life, shockproof, small size, and fast response speed, so it is suitable for various lighting and display purposes. In addition to good luminous efficiency, LEDs also need to have good reliability. An LED often needs to undergo many rigorous reliability tests to prove that it can last for a certain service life. How to make LEDs have better reliability is the goal of the industry.

A semiconductor light-emitting element includes a semiconductor stack; a recessed area; and a first protection structure, which is formed on the semiconductor stack and includes a first upper surface and a turning area formed corresponding to the recessed area, wherein the first protection structure The structure includes a crack; and a second protective structure located in the crack.

A semiconductor light-emitting element includes a substrate; a semiconductor stack formed on the substrate; a plurality of recessed areas; a first protection structure formed above the semiconductor stack and the substrate, including a first upper surface and a first lower surface The surface is relative to the first upper surface; a second protection structure is formed between the first protection structure and the semiconductor stack and/or substrate and is located in the recessed area, wherein the second protection structure includes a second upper surface and a The second lower surface is opposite to the second upper surface; wherein, the first upper surface of the first protection structure corresponding to the recessed area and/or the second upper surface of the second protection structure corresponding to the recessed area is a substantially flat surface.

In order to make the description of the present disclosure more detailed and complete, please refer to the description of the following embodiments and the relevant illustrations. However, the embodiments shown below are used to illustrate the semiconductor light-emitting element of the present disclosure, and the disclosure is not limited to the following embodiments. In addition, the size, material, shape, relative arrangement, etc. of the constituent parts described in the embodiments described in this specification are not limited to the description, and the scope of the present disclosure is not limited thereto, but is merely a simple explanation. In addition, the size and positional relationship of components shown in each diagram may be exaggerated for clear explanation. In the following description, in order to omit detailed description appropriately, components of the same or similar nature are shown with the same names and symbols.

Figure 1 is a top view of an embodiment of a semiconductor light emitting device 1 of the present disclosure. Figure 2 is a cross-sectional view of the semiconductor light-emitting element 1 along line segment A-A' in Figure 1 .

Please refer to Figures 1 and 2. According to an embodiment of the present disclosure, the semiconductor light emitting element 1 includes a substrate 10, a semiconductor stack 20, a first electrode 30, a second electrode 40, a first protection structure 50, and a second protection structure. 60. The third electrode 70 and the fourth electrode 80 . The semiconductor stack 20 is located on the upper surface 10a of the substrate 10. The semiconductor stack 20 includes a first semiconductor layer 201, an active layer 203 and a second semiconductor layer 202 in order from the upper surface 10a of the substrate upward. The first semiconductor layer 201 has an upper surface 201 a which is not covered by the active layer 203 and the second semiconductor layer 202 . The upper surface 10a of the substrate 10 has an exposed area 100 that is not covered by the first semiconductor layer 201, the active layer 203 and the second semiconductor layer 202. In one embodiment, the exposed region 100 surrounds the semiconductor stack 20 . The first electrode 30 includes a first contact portion 31 and a first extension portion 32 . The second electrode 40 includes a second contact portion 41 and a second extension portion 42 . The first protection structure 50 covers the semiconductor stack 20 , the substrate 10 , the first electrode 30 and the second electrode 40 . As shown in FIG. 1 , the first protection structure 50 includes two openings 501 and 502 corresponding to the first contact portion 31 of the first electrode 30 and the second contact portion 41 of the second electrode 40 . The second protection structure 60 covers part or all of the first protection structure 50 . The third electrode 70 and the fourth electrode 80 are formed above the first electrode 30 and the second electrode 40 respectively. The third electrode 70 is electrically connected to the first contact portion 31 of the first electrode 30 through the opening 501 of the first protection structure 50 , and the fourth electrode 80 is electrically connected to the second electrode 40 through the opening 502 of the first protection structure 50 . first contact portion 41.

The substrate 10 is a growth substrate for epitaxial growth of the semiconductor stack 20 . The substrate 10 includes a gallium arsenide (GaAs) wafer for epitaxial growth of aluminum gallium indium phosphide (AlGaInP), or for the growth of gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride ( AlGaN) sapphire (Al2O3) wafer, gallium nitride (GaN) wafer, silicon carbide (SiC) wafer, or aluminum nitride (AlN) wafer. Alternatively, the substrate 10 is a supporting substrate, including conductive materials, such as silicon (Si), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), carbonized Silicon (SiC) or alloys of the above materials, or thermally conductive materials, such as diamond, graphite, or aluminum nitride. The growth substrate originally used to epitaxially grow the semiconductor stack 20 can be selectively removed according to application requirements, and then the semiconductor stack 20 is transferred to the aforementioned support substrate.

Referring to FIG. 2 , the surface of the substrate 10 that is in contact with the semiconductor stack 20 has a roughened surface. The roughened surface may be a surface with an irregular shape or a surface with a regular shape. For example, the substrate 10 includes one or a plurality of feature portions 11 protruding or recessed from the upper surface 10 a of the substrate 10 , and the feature portions 11 are components including a hemispherical shape, a conical shape, or a polygonal cone shape. In other embodiments, the side of the substrate 10 that is in contact with the semiconductor stack 20 is a flat surface.

In one embodiment, metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion plating are used. A semiconductor stack, such as a semiconductor stack 20 with optoelectronic properties, such as a light-emitting stack, is formed on the substrate 10 . The physical vapor deposition method includes sputtering or evaporation. Next, an etching process is used to form a platform on the semiconductor stack 20 and expose the upper surface 201 a of the first semiconductor layer 201 , and remove part of the semiconductor stack 20 to form an exposed region 100 on the substrate 10 .

The wavelength of light emitted by the semiconductor light-emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 20 (such as the first semiconductor layer 201, the second semiconductor layer 202 and the active layer 203). The material of the semiconductor stack 20 includes III-V group semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where x≧0, y≦1, and ( x+y)≦1. When the material of the semiconductor stack 20 is an AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, or green light with a wavelength between 530 nm and 570 nm. When the material of the semiconductor stack 20 is an InGaN series material, it can emit blue light with a wavelength between 400 nm and 490 nm. When the material of the semiconductor stack 20 is AlGaN series or AlInGaN series material, it can emit ultraviolet light with a wavelength between 400 nm and 250 nm.

The first semiconductor layer 201 and the second semiconductor layer 202 can be cladding layers, which have different conductivity types, electrical properties, polarities, or are doped with elements to provide electrons or holes, such as a third The first semiconductor layer 201 is an n-type semiconductor, and the second semiconductor layer 202 is a p-type semiconductor. The active layer 203 is formed between the first semiconductor layer 201 and the second semiconductor layer 202. Electrons and holes are driven by a current to recombine in the active layer 203, converting electrical energy into light energy to emit light. The active layer 203 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum structure (multi-quantum). well, MQW). The material of the active layer 203 may be a neutral, p-type or n-type electrical semiconductor. The first semiconductor layer 201, the second semiconductor layer 202, or the active layer 203 may be a single layer or a structure including multiple layers.

In addition, the semiconductor stack 20 also includes a buffer layer (not shown) located between the first semiconductor layer 201 and the substrate 10 to release the stress caused by the material lattice mismatch between the substrate 10 and the semiconductor stack 20 , to reduce misalignment and lattice defects, thereby improving epitaxial quality. The buffer layer may be a single layer or a structure including multiple layers. The material of the buffer layer includes GaN, AlGaN or AlN. In one embodiment, the buffer structure includes multiple sub-layers (not shown). The sub-layers include the same material or different materials. In one embodiment, the buffer structure includes two sub-layers, wherein the growth method of the first sub-layer is sputtering, and the growth method of the second sub-layer is MOCVD. In one embodiment, the buffer layer further includes a third sub-layer. The growth method of the third sub-layer is MOCVD, and the growth temperature of the second sub-layer is higher or lower than the growth temperature of the third sub-layer. In one embodiment, the first, second and third sub-layers include the same material, such as AlN, or a combination of different materials, such as AlN, GaN and AlGaN. In other embodiments, PVD-aluminum nitride (PVD-AlN) is used as the buffer layer, and the target used to form PVD-aluminum nitride is composed of aluminum nitride, or a target composed of aluminum is used and Aluminum nitride is reactively formed in the presence of a nitrogen source.

The materials of the first electrode 30 and the second electrode 40 include metals, such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), silver (Ag), tin (Sn), Metals such as nickel (Ni), rhodium (Rh) or platinum (Pt) or alloys or laminates of the above materials. In some embodiments, the first electrode 30 and/or the second electrode 40 is a single layer, or a structure including a plurality of layers, such as a Ti/Au layer, a Ti/Al layer, a Ti/Pt/Au layer, or a Cr/Au layer. layer, Cr/Pt/Au layer, Ni/Au layer, Ni/Pt/Au layer, Ti/Al/Ti/Au layer, Cr/Ti/Al/Au layer, Cr/Al/Ti/Au layer, Cr/ Al/Ti/Pt layer or Cr/Al/Cr/Ni/Au layer, or a combination thereof.

Please refer to Figure 2. The first protection structure 50 is a single-layer or multi-layer structure and includes a first upper surface 50a. In one embodiment, the first protection structure 50 is a single-layer structure, including non-conductive materials such as dielectric materials such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), Titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). In another embodiment, the first protection structure 50 is a structure including a plurality of layers, for example, two or more material layers including different refractive indexes are stacked alternately to form a Dispersed Bragg Reflector (DBR) structure for transmitting light from the source. The light from the active layer 203 is reflected to one side of the substrate 10 . For example, a high reflectivity DBR structure is formed by stacking layers such as SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ . When the wavelength of light emitted by the semiconductor light emitting element 1 is λ, the optical thickness of the distributed Bragg reflector (DBR) structure is set to an integer multiple of λ/4. The optical thickness of a Dispersed Bragg Reflector (DBR) structure can have a deviation of ±30% based on integer multiples of λ/4. In one embodiment, the first protective structure 50 is formed by physical vapor deposition (PVD), electron beam evaporation (E-gun Evaporation), thermal evaporation (Thermal Evaporation), and atomic layer deposition (Atomic Layer Deposition). ALD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).

The material of the second protective structure 60 includes flowable material. Since the material of the second protective structure 60 has flowable characteristics, it can be anisotropically formed in the turning area 52 and/or the crack 54 of the first protective structure 50, which will be described in detail later. In one embodiment, the second protective structure 60 is composed of a rotary coating medium. Flowable materials include organic materials or inorganic materials. Organic materials include photosensitive materials, polymeric materials, or combinations thereof. Photosensitive materials include Su-8 and benzocyclobutene (BCB). Polymer materials include perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyterephthalic acid Ethylene glycol (PET), polycarbonate (PC), polyetherimide (PI), or fluorocarbon polymer. Inorganic materials include silicon-containing materials such as siloxanes. The second protection structure 60 can be formed on the semiconductor light-emitting element 1 by anisotropically applying the above-mentioned flowable material. Anisotropic formation methods include spin coating.

The materials of the third electrode 70 and the fourth electrode 80 include metals, such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), silver (Ag), tin (Sn), Metals such as nickel (Ni), rhodium (Rh) or platinum (Pt) or alloys or laminates of the above materials. In some embodiments, the third electrode 70 and/or the fourth electrode 80 is a single layer, or includes a plurality of layer structures. In some embodiments, an electrode bonding pad (not shown) is formed above the third electrode 70 and/or the fourth electrode 80 respectively. In another embodiment, the electrode bonding pad can be formed in the same process as the third electrode 70 and/or the fourth electrode 80 , or suitable materials can be selected for the third electrode 70 and/or the fourth electrode 80 , respectively. an electrode bonding pad. The electrode bonding pad includes a single layer or a multi-layer stack structure composed of metal materials such as Sn, Au and other metal elements or their alloys, such as Sn/Ag, Sn/Au, Sn/AuSn, SnAg/Sn, SnAg/AuSn, SnAg/Sn/ AuSn, or its combination, is used to connect the carrier board during the wiring or welding process, so that the semiconductor light-emitting element 1 is electrically connected to an external power supply or external electronic components.

In some embodiments, the first electrode 30 , the second electrode 40 , the third electrode 70 and the fourth electrode 80 each have a thickness between 1 μm and 100 μm, preferably between 1.2 μm and 60 μm, and more preferably between 1.2 μm and 60 μm. Between 1.5μm~6μm.

In some embodiments, a transparent conductive layer 28 is formed on the upper surface 202a of the second semiconductor layer 202 and is in electrical contact with the second semiconductor layer 202 for laterally dispersing current. The first electrode 30 is located on the upper surface 201 a of the first semiconductor layer 201 and is electrically connected to the first semiconductor layer 201 . The second electrode 40 is located on the upper surface 202 a of the second semiconductor layer 202 and is electrically connected to the second semiconductor layer 202 through the transparent conductive layer 28 . The material of the transparent conductive layer 28 includes a material that is transparent to the light emitted by the active layer 203, such as metal or transparent conductive oxide. The metal transparent conductive layer 28 is selected from thin metal layers with light transmittance. Transparent conductive oxides include graphene, indium tin oxide (ITO), gallium zinc oxide (GZO), aluminum zinc oxide (AZO) or indium zinc oxide (IZO).

Referring to FIG. 2 , the semiconductor light-emitting element 1 may further include a current blocking layer 26 between the transparent conductive layer 28 and the second semiconductor layer 202 , and/or between the first electrode 30 and the first semiconductor layer 201 (not shown in the figure). ). The transparent conductive layer 28 includes an opening (not shown) located under the second contact portion 41 of the second electrode 40 to expose the second semiconductor layer 202 and/or the current blocking layer 26 . The second contact portion 41 can pass through the transparent conductive layer 28 The opening contacts the second semiconductor layer 202 . In other embodiments, the current blocking layer 26 located between the first electrode 30 and the first semiconductor layer 201 and/or the transparent conductive layer 28 and the second semiconductor layer 201 also includes a plurality of discontinuous currents. The blocking blocks are respectively arranged corresponding to the first electrode 30 and the second electrode 40 . In one embodiment, the current blocking block is located below the first contact part 31 and the first extension part 32, and/or below the second contact part 41 and the second extension part 42, and the width of the current blocking block is respectively greater than or smaller than the first contact part 31 and the first extension part 32. The width of a contact portion 31 and the first extension portion 32 and/or the second contact portion 41 and the second extension portion 42 .

The current blocking layer 26 is formed of a non-conductive material, including a dielectric material such as aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx). In a variation, the current blocking layer 26 may include a Dispersed Bragg Reflector (DBR) structure, where the DBR structure is formed by stacking insulating materials with different refractive indexes. In order to increase the light extraction efficiency of the semiconductor light emitting element 1, the current blocking layer 26 has a light reflectivity of more than 80% for the light emitted by the active layer 203.

Figure 3 is a partial cross-sectional SEM photograph of an embodiment of the semiconductor light-emitting element 1 of the present disclosure, showing part of the substrate 10, the first semiconductor layer 201 in Figure 2, and the first extension portion 32 and the first semiconductor layer 201 located thereon. Protection structure 50 and second protection structure 60 .

Referring to Figures 2 and 3, the structure of the semiconductor light-emitting element 1 itself has one or more recessed areas 12 caused by height differences. For example, the height difference between the first semiconductor layer 201 and the first electrode 30, such as the first extension 32, causes the recessed area 12; and the height difference between the semiconductor stack 20 and the surface of the substrate 10 causes the recessed area 12; and the substrate 10 itself The height differences of the roughened surface create a plurality of recessed areas 12 . In one embodiment, the recessed region 12 is located at the interface between the first semiconductor layer 201 and the first electrode 30 (such as the first extension 32 ), at the interface between the semiconductor stack 20 and the substrate 10 , and/or at between the features 11 of the substrate 10 . In other embodiments, such as between the first semiconductor layer 201 and the first contact portion 31 of the first electrode 30 , the second contact portion 41 and/or the second extension portion 42 of the second electrode 40 and the second semiconductor layer 202 And/or the height difference between the transparent conductive layers 28 may also cause recessed areas (not shown).

Since the first protective structure 50 covers the recessed area 12 , and especially conforms to the topography of the recessed area, the film properties of the first protective structure 50 are affected, such as uneven film thickness or insufficient film quality. In one embodiment, the film layer of the first protective structure 50 located in the recessed area 12 is thinner than the area outside the recessed area 12 , or the film thickness is relatively uneven due to the height difference of the recessed area 12 . In another embodiment, the first protective structure 50 located in the recessed area 12 has an uneven plating rate due to the height difference of the recessed area 12 , which in turn causes the film in the recessed area 12 to be insufficiently dense, resulting in defects such as gaps or film discontinuity.

FIG. 4 is a partially enlarged SEM photograph of the first extending portion 32 and the first semiconductor layer 201 in FIG. 3 .

Please refer to FIGS. 3 and 4 together. When the first protection structure 50 covers the recessed area 12 , the first protection structure 50 generates a turning area 52 at a position corresponding to the recessed area 12 . In this embodiment, if the angle θ between the side surface of the first extension portion 32 of the first electrode 30 and the upper surface 201a of the first semiconductor layer 201 below is too large (for example, greater than 30 degrees, or greater than 40 degrees, or greater than 60 degrees ), the turning amplitude of the turning area 52 of the first protective structure 50 will be too large, which will lead to poor film properties of the first protective structure 50. For example, poor step coverage will cause uneven film thickness, which will cause defects or density. Not good. In other embodiments, if the angle θ between the second extension portion 42 of the second electrode 40 and the upper surface 202a of the second semiconductor layer 202 below is too large (for example, greater than 30 degrees, or greater than 40 degrees, or greater than 60 degrees ), may also result in poor film properties of the first protective structure 50 .

Due to the height difference of the semiconductor light-emitting element 1 itself, there is a problem of poor step coverage of the coating, which in turn results in poor properties of the film, such as the first protective structure 50 , affecting the life of the semiconductor light-emitting element 1 . In this embodiment, the second protective structure 60 covers part or all of the turning area 52 of the first protective structure 50 to fill or repair the turning area 52 and/or the crack 54 of the first protective structure 50 . In one embodiment, the second protection structure 60 directly contacts and covers the first upper surface 50 a of the first protection structure 50 at least in the turning area 52 . In this embodiment, the second protection structure 60 is non-conformally formed on the first protection structure 50 . The second protective structure 60 has a second upper surface 60a, and the second upper surface 60a is flatter or smoother than the first upper surface 52 at a position corresponding to the turning area 52. In one embodiment, the material constituting the second protective structure 60 may be a flowable material. Due to the flowability characteristics of the material, it can be anisotropically deposited in the turning zone 52 by, for example, spin coating. In one embodiment, after the second protective structure is formed by spin coating, it can be further cured by heating. An appropriate heating temperature is selected according to the material of the second protective structure 60 . For example, when the second protection structure 60 includes an organic material, the heating temperature is no higher than 300°C, such as about 100°C to 300°C, or for example, about 100°C to 200°C; when the second protection structure 60 includes an inorganic material, the heating temperature The temperature is about 300℃ to 400℃. Therefore, the thickness of the second protective structure 60 at the position corresponding to the turning zone 52 is not uniform, and as the turning amplitude of the turning zone 52 becomes larger, the film coverage thickness increases, and the thickness gradually decreases toward the direction away from the turning zone 52 . For example, when the included angle θ increases, that is, when the turning amplitude of the recessed area 12 and the turning area 52 increases, the thickness of the second protection structure 60 at the position corresponding to the turning area 52 will also increase, and the thickness will increase in the direction away from the turning area 52 Gradually reduce, the minimum can be reduced to 0.

In one embodiment, the second upper surface 60a of the second protection structure 60 presents a substantially flat surface in a position corresponding to the turning area 52. In some embodiments, the second upper surface 60a of the second protection structure 60 presents a smooth and curved surface in a position corresponding to the turning area 52 . When the turning area 52 of the first protection structure 50 is covered by the second protection structure 60, the second upper surface 60a of the second protection structure 60 is formed in a position corresponding to the turning area 52 that is smaller than the first upper surface 50a of the first protection structure 50. A flatter or smoother topography can effectively alleviate the unevenness of the surface of the semiconductor light-emitting element 1 caused by the turning region 52 and enable subsequent processes, such as other film layers formed above the first protective structure 50, to obtain a better surface. Quality. In another embodiment, by virtue of the flowability of the material of the second protection structure 60 , the second protection structure 60 can be filled into the cracks 54 to further prevent water vapor from penetrating, or electrodes formed in subsequent processes, for example, from being formed during device operation. When the crack 54 is formed, the metal diffuses and invades the semiconductor stack 20 along the crack 54 , thereby reducing the reliability of the semiconductor light-emitting element 1 . Or, due to the weak structural strength of the crack 54 , the stress generated in subsequent processes affects it and causes further structural damage.

FIG. 5 is an SEM photograph of the semiconductor light-emitting element 1 of another embodiment, showing the partial structure of part of the substrate 10 , the first semiconductor layer 201 , the first protection structure 50 and the second protection structure 60 .

As shown in Figure 5, in this embodiment, the main structure and materials of the semiconductor light-emitting element 1 are similar to the previous embodiments. The difference is that the first protection structure 50 of the semiconductor light-emitting element 1 in this embodiment includes a DBR structure 56 and A bottom layer 58 is located between the DBR structure 56 and the substrate 10 and/or the semiconductor layer (eg, the first semiconductor layer 201). The bottom layer 58 contains a single layer or multiple sub-layers. In one embodiment, the bottom layer 58 includes a single layer, and the DBR structure 56 is located above the bottom layer 58 . In another embodiment, the bottom layer 58 includes a plurality of sub-layers, and the DBR structure is formed between the plurality of bottom layers 58 . In a specific embodiment, the first protection structure 50 is formed by sequentially stacking the bottom layer 58/DBR structure 56/bottom layer 58 (not shown), such as SiO2/DBR/SiO2. In one embodiment, the bottom layer 58 and the DBR structure 56 are formed by physical vapor deposition (PVD), electron beam evaporation (E-gun Evaporation), thermal evaporation (Thermal Evaporation), and atomic layer deposition (Atomic Layer Deposition). , ALD) or plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD). In one embodiment, the bottom layer 58 and the DBR structure are formed in different ways. The bottom layer 58 is formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atomic Layer Deposition (ALD). DBR The structure is formed by physical vapor deposition (PVD).

In one embodiment, the first protection structure 50 includes a turning area 52 , and at least one crack 54 is formed corresponding to the turning area 52 . When the first protective structure 50 covers the recessed area 12 , if the turning amplitude of the recessed area 12 is too large or the depth of the recessed area 12 increases due to a large height difference, cracks will be formed in the turning area 52 of the first protective structure 50 54, and extends from the first upper surface 50a into the first protection structure 50. External moisture and metal during the manufacturing process invade the semiconductor stack 20 along the cracks 54 and reduce the reliability of the semiconductor light-emitting element 1 .

Please continue to refer to FIG. 5 . In some embodiments, a part of the second protection structure 60 is located in the crack 54 and fills it, and another part of the second protection structure 60 covers the turning area 52 and its crack 54 . As mentioned above, since the second upper surface 60a of the second protective structure 60 located on the turning area 52 has a flatter topography than the first upper surface 50a located in the turning area 52, the subsequent film layer covering it will A certain level of flatness can be maintained to avoid defects. Furthermore, filling the cracks 54 with the second protection structure 60 can effectively prevent metal, moisture, etc. from unintentionally diffusing into the semiconductor stack 20 through the cracks 54 , thereby greatly improving the reliability of the component surface. In other embodiments, the second protective structure 60 only fills the crack 54 without covering the turning area 52 , so that the second upper surface 60 a of the second protective structure 60 is located at the opening of the crack 54 (not shown in the figure). ).

Figure 6 is a cross-sectional view of another embodiment of the semiconductor light-emitting device 1' of the present disclosure, showing the partial structure of the substrate 10, the first semiconductor layer 201, the first protection structure 50 and the second protection structure 60.

Please refer to Figure 6. The main structure of the semiconductor light-emitting element 1' is similar to the semiconductor light-emitting element 1. The difference is that the second protection structure 60 of the semiconductor light-emitting element 1' is located between the substrate 10 and the first protection structure 50. In this embodiment, the semiconductor light-emitting element 1' includes a substrate 10, a semiconductor stack 20 is formed on the substrate 10, and the substrate 10 has an exposed area 100 that is not covered by the semiconductor stack 20. The substrate 10 includes a plurality of feature portions 11 located on the upper surface 10 a of the substrate 10 and protruding upward. The height difference between the feature portions 11 of the substrate 10 creates a plurality of recessed areas 12 . In another embodiment, as in the light-emitting device described in the previous embodiments, the recessed region 12 may be formed at the interface between the electrode (not shown) and the semiconductor stack 20 . The first protection structure 50 is formed on the substrate 10 and/or the semiconductor stack 20 and includes a first upper surface 50a and a first lower surface 50b opposite the first upper surface 50a, and the first upper surface 50a is a substantially flat surface. . The second protection structure 60 is formed between the first protection structure 50 and the substrate 10 and/or the semiconductor stack 20, including a second upper surface 60a and a first lower surface 50b of the first protection structure 50 overlapping each other, and a second The lower surface 60b is opposite to the second upper surface 60a.

The second protection structure 60 covers the exposed area 100 of the upper surface 10a of the substrate 10. Due to the flowability characteristics of the material of the second protective structure 60 , it can be anisotropically deposited in the recessed area 12 , such as the recessed area 12 between the features 11 or on the semiconductor stack 20 , by, for example, spin coating. recessed area (not shown). In one embodiment, after the second protective structure is formed by spin coating, it can be further cured by heating. An appropriate heating temperature is selected according to the material of the second protective structure 60 . For example, when the second protective structure 60 includes an organic material, the heating temperature is no higher than 300°C, such as about 100°C to 300°C, or for example, 100°C to 200°C; when the second protective structure 60 includes an inorganic material, the heating temperature About 300℃ to 400℃. Through the characteristics of the second protective structure 60 , the height difference caused by the recessed area 12 can be mitigated or filled up. In one embodiment, the second protection structure 60 completely covers the feature portion 11 of the substrate 10 so that the top 11 a of the feature portion 11 is located below the second upper surface 60 a of the second protection structure 60 . Let the distance from the top 11a of the feature portion 11 to the upper surface 10a of the substrate 10 be D1, and the distance between the second upper surface 60a of the second protection structure 60 and the upper surface 10a of the substrate 10 be D2, then the second protection structure 60 The distance D2 between the second upper surface 60a and the upper surface 10a of the substrate 10 is greater than the distance D1 from the top 11a of the feature 11 to the upper surface 10a of the substrate 10 (ie, the height of the feature 11).

In another embodiment, the top 11a of the feature portion 11 is in the same plane as the second upper surface 60a of the second protection structure 60 (not shown), that is, the second upper surface 60a of the second protection structure 60 is in the same plane as the exposed area 100 The distance D2 from the upper surface 10a of the middle substrate 10 is equal to the distance D1 from the top 11a of the feature portion 11 to the upper surface 10a of the exposed area 100 of the substrate 10 (not shown).

By forming the second protection structure 60 between the first protection structure 50 and the substrate 10, and contacting the second upper surface 60a of the second protection structure 60 with the first lower surface 50b of the first protection structure 50, that is, the second protection structure 60 is formed between the first protection structure 50 and the substrate 10. A protective structure 50 is directly formed on the second upper surface 60a of the second protective structure 60, thereby greatly improving the flatness of the first protective structure 50, reducing or avoiding the formation of turning areas and/or defects such as cracks, and improving the first protective structure 50. Protect the film properties of the structure 50 and improve component reliability.

FIG. 7 is a schematic diagram of a light-emitting device L1 according to an embodiment of the present disclosure. The semiconductor light-emitting elements 1 and 1' in the aforementioned embodiment are mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in the form of a flip chip. The first gasket 511 and the second gasket 512 are electrically insulated by an insulating portion 513 containing insulating material. In flip-chip mounting, the side of the growth substrate opposite to the surface where the electrode pad is formed is set upward as the main light extraction surface. In order to increase the light extraction efficiency of the light-emitting device L1, a reflective structure RF can be provided around the semiconductor light-emitting elements 1 and 1'.

Figure 8 is a schematic diagram of a light emitting device L2 according to an embodiment of the present disclosure. The light-emitting device L2 is a bulb lamp and includes a lampshade 602, a reflector 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connecting part 616 and an electrical connection component 618. The light-emitting module 610 includes a carrying part 606, and a plurality of light-emitting units 608 located on the carrying part 606. The plurality of light-emitting units 608 may be the semiconductor light-emitting elements 1, 1' or the light-emitting device L1 in the aforementioned embodiments.

Figure 9 is a schematic top view of a display M according to an embodiment of the present disclosure. As shown in Figure 9, the display M includes a display substrate 90, wherein the display substrate 90 includes a display area 901 and a non-display area 902, and a plurality of pixel units PX are arranged in the display area 901 of the display substrate 90. Each pixel The unit PX includes a first sub-pixel PX_A, a second sub-pixel PX_B and a third sub-pixel PX_C respectively. The non-display area 902 is provided with a data line driving circuit DL and a scanning line driving circuit SL. The data line driving circuit DL is connected to the data line (not shown) of each pixel unit PX to transmit data signals to each pixel unit PX. The scan line driving circuit SL is connected to the scan line (not shown) of each pixel unit PX to transmit the scan signal to each pixel unit PX. The pixel unit PX includes the semiconductor light-emitting elements 1 and 1' of any of the aforementioned embodiments. Each sub-pixel emits light of different colors. In some embodiments, the first sub-pixel PX_A, the second sub-pixel PX_B and the third sub-pixel PX_C are, for example, a red sub-pixel, a green sub-pixel and a blue sub-pixel respectively. Color pixels. Light-emitting elements that emit light of different wavelengths can be used as sub-pixels, so that each sub-pixel displays different colors. In some embodiments, any sub-pixel includes the semiconductor light-emitting element 1, 1' of any of the aforementioned embodiments. The light emitted by the semiconductor light-emitting element 1, 1' passes through the wavelength conversion element (not shown), so that each sub-pixel Pixels appear in different colors. Through the combination of red, green and blue light emitted by each sub-pixel, the display M can emit a full-color image. However, the number and arrangement of the sub-pixels of the pixel unit PX in this embodiment are not limited to this. Different implementations can be implemented according to user needs, such as color saturation, resolution, contrast, etc.

Figure 10 is a cross-sectional view of one pixel unit PX in Figure 9. As mentioned above, the pixel unit PX includes the semiconductor light-emitting elements 1 and 1' of any of the above embodiments. In some embodiments, any sub-pixel includes a light-emitting element package PKG, and the light-emitting element package PKG encloses the semiconductor light-emitting element 1, 1' of any of the aforementioned embodiments. The light-emitting element package PKG is bonded to the display substrate 90 in a flip-chip manner. The display substrate 90 is provided with a circuit layer 91 and circuit bonding pads 6a and 6b. The circuit layer 91 is electrically connected to the circuit bonding pads 6a and 6b. The circuit layer 91 may include active electronic components, such as transistors. The electrodes 6c and 6d of the light-emitting element package PKG are respectively connected to the circuit bonding pads 6a and 6b by soldering, for example, and are electrically connected to the display driving circuit (ie, the data line driving circuit DL and the scanning line driving circuit SL) through the circuit layer 91. sexual connection. In this way, the semiconductor light-emitting elements 1 and 1' in the pixel unit PX can be controlled by the data line driving circuit DL, the scanning line driving circuit SL and the circuit layer 91. In some embodiments (not shown), the pixel unit PX includes a light-emitting element package PKG. A single light-emitting element package PKG simultaneously encloses a plurality of semiconductor light-emitting elements 1, 1', and each semiconductor light-emitting element 1, 1' Constitute a sub-pixel. In some embodiments (not shown), any sub-pixel includes a semiconductor light-emitting element 1, 1' according to any embodiment of the present disclosure, and the first electrode 30 of the semiconductor light-emitting element 1, 1' is flip-chip. The second electrode 40, or the third electrode 70 and the fourth electrode 80 are respectively connected to the circuit bonding pads 6a and 6b on the display substrate 90.

FIG. 11 is a cross-sectional view of a display backlight unit BL according to an embodiment of the present disclosure. The display backlight unit BL includes a bottom case 700 that accommodates a light source module 71 and an optical film 72 disposed above the light source module 71 . The optical film 72 is, for example, a light diffuser. In some embodiments, the backlight unit BL is a direct backlight unit. The light source module 71 includes a circuit carrier board 710 and a plurality of light sources 711 arranged on its upper surface. In some embodiments, the light source 711 includes the semiconductor light-emitting element 1, 1' of any of the aforementioned embodiments, which is mounted on the upper surface of the circuit carrier board 710 in a flip-chip manner. In some embodiments, the light source 711 includes a light-emitting element package PKG, in which the semiconductor light-emitting element 1, 1' of any of the foregoing embodiments is encapsulated, and is mounted on the upper surface of the circuit carrier board 710 in a flip-chip manner. In some embodiments, a plurality of semiconductor light-emitting elements 1, 1' are enclosed in a single light-emitting element package PKG.

However, the above embodiments are only illustrative to illustrate the principle and effect of the present application, and are not used to limit the present application. Anyone with ordinary knowledge in the technical field to which this application belongs can make modifications and changes to the above embodiments without violating the technical principles and spirit of this application. All changes and modifications made equally to the shape, structure, characteristics and spirit described in the patentable scope of this application shall be included in the patentable scope of this application.

1. 1’: Semiconductor light-emitting element 10: Substrate 100: Exposed area 10a: Upper surface 11: Characteristic part 11a: Top 12: Recessed area 20: Semiconductor stack 20b: Side surface 201: First semiconductor layer 201a: Upper surface 202: Second semiconductor layer 202a: Upper surface 203: Active layer 30: First electrode 31: First contact part 32: Second extension 40: Second electrode 41: Second contact part 42: Second extension part 50: First protective structure 50a: First upper surface 50b: First lower surface 52: Turning area 54:Crack 60:Second protective structure 60a: Second upper surface 60b: Second lower surface 70:Third electrode 80:Fourth electrode D1, D2: distance θ: angle L1:Light-emitting device 51:Packaging substrate 511: First gasket 512: Second gasket 53: Insulation part RF: Reflective structure L2:Light-emitting device 602:Lampshade 604: Reflector 606: Bearing part 608:Light-emitting unit 610:Light-emitting module 612: Lamp holder 614: Heat sink 616: Connection part 618: Electrical connection component M:Display 90:Display substrate 901: Display area 902: Non-display area PX: Pixel unit PX_A: First sub-pixel PX_B: Second sub-pixel PX_C: Third sub-pixel PKG: Light emitting element package 6a, 6b: Circuit bonding pad 6c, 6d: Electrode BL: Backlight unit 700: Bottom case 71: Light source module 710:Circuit carrier board 711:Light source 72: Optical film

FIG. 1 is a top view of an embodiment of a semiconductor light-emitting device of the present disclosure.

Figure 2 is a cross-sectional view of the semiconductor light-emitting element along line segment A-A' in Figure 1.

Figure 3 is a partial cross-sectional scanning electron microscope (SEM) photo of an embodiment of a semiconductor light-emitting device of the present disclosure.

Figure 4 is a partially enlarged SEM photograph of the electrode and the first semiconductor layer in Figure 3 and the recessed area formed between them.

FIG. 5 is a cross-sectional view of another embodiment of a semiconductor light-emitting device of the present disclosure.

FIG. 6 is a cross-sectional view of another embodiment of a semiconductor light-emitting device of the present disclosure.

FIG. 7 is a schematic diagram of an embodiment of the light emitting device L1 of the present disclosure.

FIG. 8 is a schematic top view of an embodiment of the light-emitting device L2 of the present disclosure.

FIG. 9 is a schematic top view of an embodiment of the display M of the present disclosure.

Figure 10 is a cross-sectional view of one pixel unit PX in Figure 9.

FIG. 11 is a cross-sectional view of an embodiment of the display backlight unit BL of the present disclosure.

without

10:Substrate

11: Characteristics Department

12: Depression area

201: First semiconductor layer

201a: Upper surface

32: First extension

50:First protective structure

50a: First upper surface

52: Turning area

60:Second protective structure

60a: Second upper surface

Claims (10)

A semiconductor light-emitting element including: a semiconductor stack; a depressed area; A first protection structure is formed on the semiconductor stack and includes a first upper surface and a turning region formed corresponding to the recessed region, wherein the first protection structure includes a crack; and A second protective structure is located in the crack. The semiconductor light-emitting element of claim 1, further comprising an electrode located on the semiconductor stack, wherein the semiconductor stack includes a first semiconductor layer, a second semiconductor layer, and an active layer located on the first semiconductor layer and between the second semiconductor layer. The semiconductor light-emitting element of claim 2, wherein the recessed region is located between the semiconductor stack and the electrode. The semiconductor light-emitting element according to claim 1 or claim 3, wherein the crack is formed corresponding to the recessed area. The semiconductor light-emitting element of claim 1, wherein the first protection structure includes a DBR structure. The semiconductor light-emitting element of claim 5, wherein the first protection structure includes a first bottom layer located under the DBR structure, and/or the first protection structure includes a second bottom layer located above the DBR structure. The semiconductor light-emitting element of claim 6, wherein the first bottom layer or the second bottom layer includes a plurality of sub-layers. The semiconductor light-emitting element of claim 1, wherein the second protective structure includes a flowable material, wherein the flowable material includes an organic material or an inorganic material. The semiconductor light-emitting element of claim 8, wherein the organic material includes a photosensitive material or a polymer material. The semiconductor light-emitting element of claim 9, wherein the photosensitive material contains Su-8 or benzocyclobutene (BCB).

Images