TWI852572B - Semiconductor light-emitting device - Google Patents

Abstract

A semiconductor light-emitting device includes a semiconductor stack; a recess region; a first protective structure formed on the semiconductor stack, and including a first upper surface and a bending region formed corresponding to the recess region, wherein the first protective structure includes a seam; and a second protective structure disposed in the seam.

Description

Semiconductor light emitting device

This case relates to a semiconductor device, in particular a semiconductor light-emitting device.

Light-emitting diodes (LEDs) have good characteristics such as low energy consumption, low heat generation, long operating life, shock resistance, small size, and fast response speed, so they are suitable for various lighting and display purposes. In addition to good luminous efficiency, LEDs also need to have good reliability. An LED often needs to undergo many strict reliability tests to prove that it can last for a certain service life. How to make LEDs more reliable is the goal that the industry strives for.

A semiconductor light-emitting element includes a semiconductor stack; a recessed area; a first protective structure formed on the semiconductor stack and including a first upper surface and a turning area formed corresponding to the recessed area, wherein the first protective structure includes a crack; and a second protective structure located in the crack.

A semiconductor light-emitting element comprises a substrate; a semiconductor stack formed on the substrate; a plurality of recessed areas; a first protective structure formed above the semiconductor stack and the substrate, comprising a first upper surface and a first lower surface opposite to the first upper surface; a second protective structure formed between the first protective structure and the semiconductor stack and/or the substrate and located in the recessed area, wherein the second protective structure comprises a second upper surface and a second lower surface opposite to the second upper surface; wherein the first upper surface of the first protective structure corresponding to the recessed area and/or the second upper surface of the second protective structure corresponding to the recessed area are substantially flat surfaces.

In order to make the description of the present disclosure more detailed and complete, please refer to the description of the following embodiments and the related figures. However, the embodiments shown below are used to illustrate the semiconductor light-emitting elements of the present disclosure, and the present disclosure is not limited to the following embodiments. In addition, the size, material, shape, relative configuration, etc. of the components recorded in the embodiments in this manual are not limited to this, but are simply described. In addition, the size or position relationship of the components shown in each figure may be exaggerated for the purpose of clear description. In the following description, in order to appropriately omit detailed description, the same name or symbol is used to display the same or the same nature of the components.

FIG. 1 is a top view of an embodiment of a semiconductor light emitting device 1 disclosed in the present invention. FIG. 2 is a cross-sectional view of the semiconductor light emitting device 1 along the line segment A-A' of FIG. 1.

Referring to FIG. 1 and FIG. 2, according to an embodiment of the present disclosure, a semiconductor light-emitting element 1 includes a substrate 10, a semiconductor stack 20, a first electrode 30, a second electrode 40, a first protective structure 50, a second protective structure 60, a third electrode 70, and a fourth electrode 80. The semiconductor stack 20 is located on the upper surface 10a of the substrate 10. The semiconductor stack 20 includes a first semiconductor layer 201, an active layer 203, and a second semiconductor layer 202 in order from the upper surface 10a of the substrate. The first semiconductor layer 201 has an upper surface 201a that is not covered by the active layer 203 and the second semiconductor layer 202. The upper surface 10a of the substrate 10 has an exposed area 100 which is not covered by the first semiconductor layer 201, the active layer 203 and the second semiconductor layer 202. In one embodiment, the exposed area 100 surrounds the semiconductor stack 20. The first electrode 30 includes a first contact portion 31 and a first extension portion 32. The second electrode 40 includes a second contact portion 41 and a second extension portion 42. The first protective structure 50 covers the semiconductor stack 20, the substrate 10, the first electrode 30 and the second electrode 40. As shown in FIG. 1, the first protective structure 50 includes two openings 501 and 502 corresponding to the first contact portion 31 of the first electrode 30 and the second contact portion 41 of the second electrode 40. The second protective structure 60 covers a part or all of the first protective structure 50. The third electrode 70 and the fourth electrode 80 are formed above the first electrode 30 and the second electrode 40, respectively. The third electrode 70 is electrically connected to the first contact portion 31 of the first electrode 30 through the opening 501 of the first protective structure 50, and the fourth electrode 80 is electrically connected to the first contact portion 41 of the second electrode 40 through the opening 502 of the first protective structure 50.

The substrate 10 is a growth substrate for epitaxially growing a semiconductor stack 20. The substrate 10 includes a gallium arsenide (GaAs) wafer for epitaxially growing aluminum gallium indium phosphide (AlGaInP), or a sapphire (Al2O3) wafer, a gallium nitride (GaN) wafer, a silicon carbide (SiC) wafer, or an aluminum nitride (AlN) wafer for growing gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). Alternatively, the substrate 10 is a supporting substrate, including a conductive material, such as silicon (Si), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), silicon carbide (SiC) or alloys of the above materials, or a thermal conductive material, such as diamond, graphite, or aluminum nitride. The growth substrate originally used for epitaxial growth of the semiconductor stack 20 can be selectively removed according to the needs of the application, and then the semiconductor stack 20 is transferred to the aforementioned supporting substrate.

Referring to FIG. 2 , the surface of the substrate 10 that is in contact with the semiconductor stack 20 has a roughened surface, and the roughened surface can be a surface with an irregular shape or a surface with a regular shape. For example, the substrate 10 includes one or more feature portions 11 protruding or recessed on the upper surface 10a of the substrate 10, and the feature portion 11 is a component including a hemispherical shape, a cone shape, or a polygonal cone shape. In other embodiments, the surface of the substrate 10 that is in contact with the semiconductor stack 20 is a flat surface.

In one embodiment, a semiconductor stack, such as a semiconductor stack 20 having photoelectric properties, such as a light-emitting stack, is formed on the substrate 10 by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion plating, wherein the physical vapor deposition method includes sputtering or evaporation. Then, a platform is formed on the semiconductor stack 20 by an etching process to expose the upper surface 201a of the first semiconductor layer 201, and a portion of the semiconductor stack 20 is removed to form an exposed area 100 on the substrate 10.

The wavelength of light emitted by the semiconductor light-emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers (e.g., the first semiconductor layer 201, the second semiconductor layer 202, and the active layer 203) in the semiconductor stack 20. The material of the semiconductor stack 20 includes a III-V semiconductor material, such as _{AlxInyGa (1-xy) N or AlxInyGa (1-xy)} P, where x≧0, y≦1, and (x+y)≦1. When the material of the semiconductor stack 20 is an AlInGaP series material, red light with a wavelength between 610 nm and 650 nm or green light with a wavelength between 530 nm and 570 nm can be emitted. When the material of the semiconductor stack 20 is an InGaN series material, blue light with a wavelength between 400 nm and 490 nm can be emitted. When the material of the semiconductor stack 20 is an AlGaN series or AlInGaN series material, ultraviolet light with a wavelength between 400 nm and 250 nm can be emitted.

The first semiconductor layer 201 and the second semiconductor layer 202 may be cladding layers, and the two have different conductivity types, electrical properties, polarities, or provide electrons or holes by doping elements. For example, the first semiconductor layer 201 is an n-type semiconductor, and the second semiconductor layer 202 is a p-type semiconductor. The active layer 203 is formed between the first semiconductor layer 201 and the second semiconductor layer 202. The electrons and holes are combined in the active layer 203 under the driving of a current, and the electrical energy is converted into light energy to emit a light. The active layer 203 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the active layer 203 may be a neutral, p-type, or n-type electrical semiconductor. The first semiconductor layer 201, the second semiconductor layer 202, or the active layer 203 may be a single layer or a structure including multiple layers.

In addition, the semiconductor stack 20 further includes a buffer layer (not shown) between the first semiconductor layer 201 and the substrate 10, which is used to release the stress generated by the material lattice mismatch between the substrate 10 and the semiconductor stack 20, so as to reduce dislocation and lattice defects, thereby improving the epitaxial quality. The buffer layer can be a single layer or a structure including multiple layers. The material of the buffer layer includes GaN, AlGaN or AlN. In one embodiment, the buffer structure includes multiple sub-layers (not shown). The sub-layers include the same material or different materials. In one embodiment, the buffer structure includes two sublayers, wherein the first sublayer is grown by sputtering, and the second sublayer is grown by MOCVD. In one embodiment, the buffer layer further includes a third sublayer. The third sublayer is grown by MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second and third sublayers include the same material, such as AlN, or different materials, such as a combination of AlN, GaN and AlGaN. In other embodiments, PVD-aluminum nitride (PVD-AlN) is used as a buffer layer, and a target material used to form PVD-aluminum nitride is composed of aluminum nitride, or a target material composed of aluminum is used to reactively form aluminum nitride in a nitrogen source environment.

The materials of the first electrode 30 and the second electrode 40 include metals, such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), silver (Ag), tin (Sn), nickel (Ni), rhodium (Rh) or platinum (Pt) or alloys or stacks of the above materials. In some embodiments, the first electrode 30 and/or the second electrode 40 is a single layer, or a structure including multiple layers such as a Ti/Au layer, a Ti/Al layer, a Ti/Pt/Au layer, a Cr/Au layer, a Cr/Pt/Au layer, a Ni/Au layer, a Ni/Pt/Au layer, a Ti/Al/Ti/Au layer, a Cr/Ti/Al/Au layer, a Cr/Al/Ti/Au layer, a Cr/Al/Ti/Au layer, a Cr/Al/Ti/Pt layer or a Cr/Al/Cr/Ni/Au layer, or a combination thereof.

Referring to FIG. 2 , the first protective structure 50 is a single-layer or multi-layer structure and includes a first upper surface 50a. In one embodiment, the first protective structure 50 is a single-layer structure including a non-conductive material such as a dielectric material such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). In another embodiment, the first protective structure 50 is a structure including multiple layers, such as two or more material layers with different refractive indices alternately stacked to form a distributed Bragg reflector (DBR) structure for reflecting light from the active layer 203 to one side of the substrate 10. For example, a high reflectivity DBR structure is formed by stacking _SiO2 / _TiO2 or _{SiO2 / Nb2O5} . When the wavelength of light emitted by the semiconductor light-emitting element 1 is λ, the optical thickness of the distributed Bragg reflector (DBR) structure is set to an integer multiple of λ/4. The optical thickness of the distributed Bragg reflector (DBR) structure may have a deviation of ±30% based on the integer multiple of λ/4. In one embodiment, the first protective structure 50 is formed by physical vapor deposition (PVD), electron beam evaporation (E-gun Evaporation), thermal evaporation (Thermal Evaporation), atomic layer deposition (Atomic Layer Deposition, ALD) or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD).

The material of the second protective structure 60 includes a flowable material. Since the material of the second protective structure 60 has the property of being flowable, it can be formed anisotropically in the turning area 52 and/or the crack 54 of the first protective structure 50, which will be described in detail later. In one embodiment, the second protective structure 60 is composed of a rotationally coated medium. The flowable material includes an organic material or an inorganic material. The organic material includes a photosensitive material, a polymer material or a combination thereof. The photosensitive material includes Su-8 and benzocyclobutene (BCB). The polymer material includes perfluorocyclobutane (PFCB), epoxy, acrylic resin, cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (PI), or fluorocarbon polymer. The inorganic material includes a silicon-containing material such as siloxane. The second protective structure 60 can be formed on the semiconductor light-emitting element 1 by anisotropically forming the above-mentioned flowable material. The anisotropic formation method includes a rotational coating method.

The materials of the third electrode 70 and the fourth electrode 80 include metals, such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), silver (Ag), tin (Sn), nickel (Ni), rhodium (Rh) or platinum (Pt) or alloys or stacks of the above materials. In some embodiments, the third electrode 70 and/or the fourth electrode 80 is a single layer, or includes a multi-layer structure. In some embodiments, an electrode bonding pad (not shown) is formed on the third electrode 70 and/or the fourth electrode 80. In another embodiment, the electrode bonding pad can be formed in the same process as the third electrode 70 and/or the fourth electrode 80, or the third electrode 70 and/or the fourth electrode 80 can be made of suitable materials and each is an electrode bonding pad. The electrode bonding pad includes a single layer or a multi-layer stacking structure composed of metal materials such as Sn, Au and other metal elements or their alloys such as Sn/Ag, Sn/Au, Sn/AuSn, SnAg/Sn, SnAg/AuSn, SnAg/Sn/AuSn, or a combination thereof, which is used to connect the carrier in the wire bonding or welding process to electrically connect the semiconductor light-emitting element 1 to an external power source or an external electronic element.

In some embodiments, the first electrode 30, the second electrode 40, the third electrode 70 and the fourth electrode 80 each have a thickness between 1 μm and 100 μm, preferably between 1.2 μm and 60 μm, and more preferably between 1.5 μm and 6 μm.

In some embodiments, a transparent conductive layer 28 is formed on the upper surface 202a of the second semiconductor layer 202 and is electrically connected to the second semiconductor layer 202 for dispersing the current laterally. The first electrode 30 is located on the upper surface 201a of the first semiconductor layer 201 and is electrically connected to the first semiconductor layer 201. The second electrode 40 is located on the upper surface 202a of the second semiconductor layer 202 and is electrically connected to the second semiconductor layer 202 through the transparent conductive layer 28. The material of the transparent conductive layer 28 includes a material that is transparent to the light emitted by the active layer 203, such as a metal or a transparent conductive oxide. The metal transparent conductive layer 28 is selected from a thin metal layer having light transmittance. Transparent conductive oxides include graphene, indium tin oxide (ITO), gallium zinc oxide (GZO), aluminum zinc oxide (AZO) or indium zinc oxide (IZO).

Referring to FIG. 2 , the semiconductor light-emitting element 1 may further include a current blocking layer 26 between the transparent conductive layer 28 and the second semiconductor layer 202 and/or between the first electrode 30 and the first semiconductor layer 201 (not shown). The transparent conductive layer 28 includes an opening (not shown) below the second contact portion 41 of the second electrode 40 to expose the second semiconductor layer 202 and/or the current blocking layer 26 . The second contact portion 41 may contact the second semiconductor layer 202 through the opening of the transparent conductive layer 28 . In other embodiments, the current blocking layer between the first electrode 30 and the first semiconductor layer 201, and/or the current blocking layer 26 between the transparent conductive layer 28 and the second semiconductor layer 201 further includes a plurality of discontinuous current blocking blocks respectively arranged corresponding to the first electrode 30 and the second electrode 40. In one embodiment, the current blocking block is located below the first contact portion 31 and the first extension portion 32, and/or below the second contact portion 41 and the second extension portion 42, and the width of the current blocking block is greater than or less than the width of the first contact portion 31 and the first extension portion 32, and/or the second contact portion 41 and the second extension portion 42.

The current blocking layer 26 is formed of a non-conductive material, including a dielectric material such as aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx). In a variation, the current blocking layer 26 may include a distributed Bragg reflector (DBR) structure, wherein the DBR structure is formed by stacking insulating materials with different refractive indices. In order to increase the light extraction efficiency of the semiconductor light-emitting element 1, the current blocking layer 26 has a light reflectivity of more than 80% for the light emitted by the active layer 203.

FIG. 3 is a partial cross-sectional SEM photograph of an embodiment of a semiconductor light emitting element 1 of the present disclosure, showing a portion of the substrate 10 of FIG. 2 , the first semiconductor layer 201 , and the first extension portion 32 , the first protection structure 50 , and the second protection structure 60 thereon.

Referring to FIGS. 2 and 3 , the semiconductor light emitting element 1 itself has one or more recessed regions 12 due to height differences. For example, the height difference between the first semiconductor layer 201 and the first electrode 30, such as the first extension portion 32, causes the recessed region 12; the height difference between the semiconductor stack 20 and the surface of the substrate 10 causes the recessed region 12; and the height difference of the roughened surface of the substrate 10 itself causes multiple recessed regions 12. In one embodiment, the recessed region 12 is located at the junction of the first semiconductor layer 201 and the first electrode 30 (such as the first extension portion 32), at the junction of the semiconductor stack 20 and the substrate 10, and/or between the feature portions 11 of the substrate 10. In other embodiments, the height difference between the first semiconductor layer 201 and the first contact portion 31 of the first electrode 30, the second contact portion 41 and/or the second extension portion 42 of the second electrode 40 and the second semiconductor layer 202 and/or the transparent conductive layer 28 may also cause a recessed area (not shown).

Because the first protective structure 50 covers the recessed area 12, especially covers it in accordance with the morphology of the recessed area, the film properties of the first protective structure 50 are affected, such as uneven film thickness or insufficient film quality. In one embodiment, the film layer of the first protective structure 50 located in the recessed area 12 is thinner than that of the area outside the recessed area 12, or the film thickness is relatively uneven due to the height difference of the recessed area 12. In another embodiment, the first protective structure 50 located in the recessed area 12 has an uneven plating rate due to the height difference of the recessed area 12, thereby making the film in the recessed area 12 insufficiently dense, resulting in defects such as gaps or film discontinuity.

FIG. 4 is a partially enlarged SEM photograph of the first extension portion 32 and the first semiconductor layer 201 in FIG. 3 .

Please refer to FIG. 3 and FIG. 4 together. When the first protective structure 50 covers the recessed area 12, the first protective structure 50 generates a turning area 52 at a position corresponding to the recessed area 12. In this embodiment, if the angle θ between the side surface of the first extension portion 32 of the first electrode 30 and the upper surface 201a of the first semiconductor layer 201 thereunder is too large (for example, greater than 30 degrees, greater than 40 degrees, or greater than 60 degrees), the turning range of the turning area 52 of the first protective structure 50 will be too large, thereby causing poor film properties of the first protective structure 50, such as poor step coverage resulting in uneven film thickness, thereby causing defects or poor density. In other embodiments, if the angle θ between the second extension portion 42 of the second electrode 40 and the upper surface 202a of the second semiconductor layer 202 thereunder is too large (for example, greater than 30 degrees, greater than 40 degrees, or greater than 60 degrees), the film properties of the first protection structure 50 may be poor.

Due to the height difference of the semiconductor light-emitting element 1 itself, the problem of poor coating step coverage is generated, which in turn causes the thin film, such as the first protective structure 50, to have poor characteristics, affecting the life of the semiconductor light-emitting element 1. In this embodiment, the second protective structure 60 covers a part or all of the turning area 52 of the first protective structure 50 to fill or repair the turning area 52 and/or cracks 54 of the first protective structure 50. In one embodiment, the second protective structure 60 directly contacts and covers the first upper surface 50a of the first protective structure 50 at least at the turning area 52. In this embodiment, the second protective structure 60 is non-conformally formed on the first protective structure 50. The second protective structure 60 has a second upper surface 60a, and the second upper surface 60a is flatter or smoother than the first upper surface 52 at a position corresponding to the turning area 52. In one embodiment, the material constituting the second protective structure 60 can be selected to have flowability. Due to the flowability of the material, it can be anisotropically deposited in the turning area 52 by, for example, a rotary coating method. In one embodiment, after the second protective structure is formed by rotary coating, it can be further cured by heating. According to the material of the second protective structure 60, a suitable heating temperature is selected. For example, when the second protective structure 60 includes an organic material, the heating temperature is not higher than 300°C, for example, about 100°C to 300°C, or about 100°C to 200°C; when the second protective structure 60 includes an inorganic material, the heating temperature is about 300°C to 400°C. Therefore, the thickness of the second protective structure 60 at the position corresponding to the turning area 52 is not uniform, and the film coating thickness increases as the turning amplitude of the turning area 52 increases, and the thickness gradually decreases in the direction away from the turning area 52. For example, when the angle θ increases, that is, when the turning amplitude of the recessed area 12 and the turning area 52 increases, the thickness of the second protective structure 60 at the position corresponding to the turning area 52 will also increase, and the thickness gradually decreases in the direction away from the turning area 52, and can be reduced to 0 at the minimum.

In one embodiment, the second upper surface 60a of the second protective structure 60 presents a substantially flat surface at a position corresponding to the turning area 52. In some embodiments, the second upper surface 60a of the second protective structure 60 presents a smooth and curved surface at a position corresponding to the turning area 52. When the second protective structure 60 covers the turning area 52 of the first protective structure 50, the second upper surface 60a of the second protective structure 60 forms a flatter or smoother morphology than the first upper surface 50a of the first protective structure 50 at a position corresponding to the turning area 52, thereby effectively alleviating the unevenness of the surface of the semiconductor light-emitting element 1 caused by the turning area 52, and enabling subsequent processes, such as other film layers formed on the first protective structure 50, to obtain better surface quality. In another embodiment, the second protective structure 60 can be filled into the crack 54 by the flowable property of the material of the second protective structure 60 to further prevent moisture from penetrating, or the metal, such as the electrode, formed in the subsequent process may diffuse along the crack 54 and invade the semiconductor stack 20 when the element is actuated, thereby reducing the reliability of the semiconductor light-emitting element 1, or because the crack 54 has a weak structural strength, the stress generated in the subsequent process may affect it and cause further structural damage.

FIG. 5 is a SEM photograph of a semiconductor light emitting device 1 according to another embodiment, showing partial structures of a portion of the substrate 10, the first semiconductor layer 201, the first protective structure 50, and the second protective structure 60.

As shown in FIG. 5 , in this embodiment, the main structure and materials of the semiconductor light-emitting element 1 are similar to those of the aforementioned embodiments, except that the first protective structure 50 of the semiconductor light-emitting element 1 of this embodiment includes a DBR structure 56 and a bottom layer 58 located between the DBR structure 56 and the substrate 10 and/or the semiconductor layer (e.g., the first semiconductor layer 201). The bottom layer 58 includes a single layer or multiple sub-layers. In one embodiment, the bottom layer 58 includes a single layer, and the DBR structure 56 is located above the bottom layer 58. In another embodiment, the bottom layer 58 includes multiple sub-layers, and the DBR structure is formed between multiple bottom layers 58. In a specific embodiment, the first protection structure 50 is formed by stacking the bottom layer 58/DBR structure 56/bottom layer 58 in sequence (not shown), such as SiO2/DBR/SiO2. In an embodiment, the bottom layer 58 and the DBR structure 56 are formed by physical vapor deposition (PVD), electron beam evaporation (E-gun Evaporation), thermal evaporation (Thermal Evaporation), atomic layer deposition (Atomic Layer Deposition, ALD) or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD). In one embodiment, the bottom layer 58 and the DBR structure are formed in different ways. The bottom layer 58 is formed by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD), and the DBR structure is formed by physical vapor deposition (PVD).

In one embodiment, the first protection structure 50 includes a turning area 52, and at least one crack 54 is formed corresponding to the turning area 52. When the first protection structure 50 covers the recessed area 12, if the recessed area 12 turns too much, or the depth of the recessed area 12 increases due to a large height difference, a crack 54 is formed in the turning area 52 of the first protection structure 50, and extends from the first upper surface 50a into the first protection structure 50. External moisture and metal in the process invade the semiconductor stack 20 along the crack 54, thereby reducing the reliability of the semiconductor light-emitting element 1.

Please continue to refer to FIG. 5. In some embodiments, a portion of the second protective structure 60 is located in the crack 54 and fills it, and another portion of the second protective structure 60 covers the turning area 52 and the crack 54. As mentioned above, since the second upper surface 60a of the second protective structure 60 located on the turning area 52 has a flatter morphology than the first upper surface 50a located in the turning area 52, the film layer covered thereon can maintain a certain flatness to avoid defects. Furthermore, by filling the crack 54 with the second protective structure 60, metal and moisture can be effectively prevented from unintentionally diffusing into the semiconductor stack 20 through the crack 54, thereby greatly improving the reliability of the device surface. In other embodiments, the second protection structure 60 only fills the crack 54 without covering the turning area 52 , so that the second upper surface 60 a of the second protection structure 60 is located at the opening of the crack 54 (not shown).

FIG. 6 is a cross-sectional view of another embodiment of a semiconductor light-emitting element 1′ of the present disclosure, showing the partial structures of the substrate 10, the first semiconductor layer 201, the first protective structure 50 and the second protective structure 60.

Please refer to FIG. 6 . The main structure of the semiconductor light-emitting element 1′ is similar to that of the semiconductor light-emitting element 1 . The difference is that the second protective structure 60 of the semiconductor light-emitting element 1′ is located between the substrate 10 and the first protective structure 50. In the present embodiment, the semiconductor light-emitting element 1′ includes a substrate 10, a semiconductor stack 20 is formed on the substrate 10, and the substrate 10 has an exposed area 100 not covered by the semiconductor stack 20. The substrate 10 includes a plurality of feature portions 11 located on the upper surface 10a of the substrate 10 and protruding upward, and the height difference between the feature portions 11 of the substrate 10 forms a plurality of recessed areas 12. In another embodiment, as in the light-emitting element described in the aforementioned embodiments, the recessed area 12 may be formed at the junction of the electrode (not shown) and the semiconductor stack 20. The first protection structure 50 is formed on the substrate 10 and/or the semiconductor stack 20, and includes a first upper surface 50a and a first lower surface 50b opposite to the first upper surface 50a, and the first upper surface 50a is a substantially flat surface. The second protection structure 60 is formed between the first protection structure 50 and the substrate 10 and/or the semiconductor stack 20, and includes a second upper surface 60a and the first lower surface 50b of the first protection structure 50 overlapping each other, and a second lower surface 60b opposite to the second upper surface 60a.

The second protective structure 60 covers the exposed area 100 of the upper surface 10a of the substrate 10. Due to the flowability of the material of the second protective structure 60, it can be anisotropically deposited in the recessed area 12, such as the recessed area 12 between the features 11 or the recessed area on the semiconductor stack 20 (not shown) by, for example, spin coating. In one embodiment, after the second protective structure is formed by spin coating, it can be further cured by heating. According to the material of the second protective structure 60, an appropriate heating temperature is selected. For example, when the second protective structure 60 includes an organic material, the heating temperature is not higher than 300°C, for example, about 100°C to 300°C, or for example, 100°C to 200°C; when the second protective structure 60 includes an inorganic material, the heating temperature is about 300°C to 400°C. By virtue of the characteristics of the second protective structure 60, the height difference caused by the recessed area 12 can be mitigated or filled. In one embodiment, the second protective structure 60 completely covers the feature portion 11 of the substrate 10, so that the top portion 11a of the feature portion 11 is located below the second upper surface 60a of the second protective structure 60. Let D1 be the distance from the top 11a of the feature portion 11 to the upper surface 10a of the substrate 10, and let D2 be the distance between the second upper surface 60a of the second protective structure 60 and the upper surface 10a of the substrate 10. Then, the distance D2 between the second upper surface 60a of the second protective structure 60 and the upper surface 10a of the substrate 10 is greater than the distance D1 from the top 11a of the feature portion 11 to the upper surface 10a of the substrate 10 (i.e., the height of the feature portion 11).

In another embodiment, the top 11a of the feature portion 11 is coplanar with the second upper surface 60a of the second protective structure 60 (not shown), that is, the distance D2 between the second upper surface 60a of the second protective structure 60 and the upper surface 10a of the substrate 10 in the exposed area 100 is equal to the distance D1 from the top 11a of the feature portion 11 to the upper surface 10a of the exposed area 100 of the substrate 10 (not shown).

By forming the second protective structure 60 between the first protective structure 50 and the substrate 10, and contacting the second upper surface 60a of the second protective structure 60 with the first lower surface 50b of the first protective structure 50, that is, the first protective structure 50 is directly formed on the second upper surface 60a of the second protective structure 60, the flatness of the first protective structure 50 is greatly improved, and the formation of turning areas and/or defects such as cracks is reduced or avoided, thereby improving the thin film properties of the first protective structure 50 and improving the reliability of the device.

FIG. 7 is a schematic diagram of a light-emitting device L1 of an embodiment of the present disclosure. The semiconductor light-emitting elements 1 and 1' in the aforementioned embodiments are mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in the form of a flip chip. The first pad 511 and the second pad 512 are electrically insulated by an insulating portion 513 comprising an insulating material. The flip chip mounting is to set the side of the growth substrate opposite to the electrode pad forming surface as the main light extraction surface. In order to increase the light extraction efficiency of the light-emitting device L1, a reflective structure RF can be set around the semiconductor light-emitting elements 1 and 1'.

FIG. 8 is a schematic diagram of a light emitting device L2 according to an embodiment of the present disclosure. The light emitting device L2 is a bulb lamp including a lampshade 602, a reflector 604, a light emitting module 610, a lamp holder 612, a heat sink 614, a connecting portion 616, and an electrical connecting element 618. The light emitting module 610 includes a supporting portion 606, and a plurality of light emitting units 608 located on the supporting portion 606, wherein the plurality of light emitting units 608 may be the semiconductor light emitting elements 1, 1' or the light emitting device L1 in the aforementioned embodiments.

FIG. 9 is a schematic top view of a display M according to an embodiment of the present disclosure. As shown in FIG. 9 , the display M includes a display substrate 90, wherein the display substrate 90 includes a display area 901 and a non-display area 902, and a plurality of pixel units PX are arranged in the display area 901 of the display substrate 90, and each pixel unit PX includes a first sub-pixel PX_A, a second sub-pixel PX_B, and a third sub-pixel PX_C. A data line driving circuit DL and a scanning line driving circuit SL are provided in the non-display area 902. The data line driving circuit DL is connected to a data line (data line) of each pixel unit PX (not shown) to transmit a data signal to each pixel unit PX. The scanning line driving circuit SL is connected to the scanning line (scan line) (not shown) of each pixel unit PX to transmit the scanning signal to each pixel unit PX. The pixel unit PX includes the semiconductor light-emitting element 1, 1' of any of the aforementioned embodiments. Each sub-pixel emits light of a different color. In some embodiments, the first sub-pixel PX_A, the second sub-pixel PX_B and the third sub-pixel PX_C are, for example, red sub-pixels, green sub-pixels and blue sub-pixels, respectively. Light-emitting elements that emit light of different wavelengths can be selected as sub-pixels, so that each sub-pixel presents a different color. In some embodiments, any sub-pixel includes the semiconductor light-emitting element 1, 1' of any of the aforementioned embodiments, and the light emitted by the semiconductor light-emitting element 1, 1' passes through a wavelength conversion element (not shown) so that each sub-pixel presents a different color. By combining the red, green and blue light emitted by each sub-pixel, the display M can emit a full-color image. However, the number and arrangement of sub-pixels in the pixel unit PX in this embodiment are not limited thereto, and can be implemented in different ways according to user requirements, such as color saturation, resolution, contrast, etc.

FIG. 10 is a cross-sectional view of a pixel unit PX in FIG. 9. As mentioned above, the pixel unit PX includes the semiconductor light-emitting element 1, 1' of any of the aforementioned embodiments. In some embodiments, any sub-pixel includes a light-emitting element package PKG, and the light-emitting element package PKG encapsulates the semiconductor light-emitting element 1, 1' of any of the aforementioned embodiments. The light-emitting element package PKG is bonded to the display substrate 90 in a flip-chip manner. A circuit layer 91 and circuit bonding pads 6a and 6b are provided on the display substrate 90. The circuit layer 91 is electrically connected to the circuit bonding pads 6a and 6b, and the circuit layer 91 may include active electronic components, such as transistors. The electrodes 6c and 6d of the light-emitting element package PKG are respectively bonded to the circuit bonding pads 6a and 6b by welding, for example, and are electrically connected to the display driving circuit (i.e., the data line driving circuit DL and the scanning line driving circuit SL) through the circuit layer 91. In this way, the semiconductor light-emitting elements 1 and 1' in the pixel unit PX can be controlled by the data line driving circuit DL, the scanning line driving circuit SL and the circuit layer 91. In some embodiments (not shown), the pixel unit PX includes a light-emitting element package PKG, and a plurality of semiconductor light-emitting elements 1 and 1' are simultaneously sealed in a single light-emitting element package PKG, and each semiconductor light-emitting element 1 and 1' constitutes a sub-pixel. In some embodiments (not shown), any sub-pixel includes a semiconductor light-emitting element 1, 1' according to any embodiment of the present disclosure, and the first electrode 30 and the second electrode 40, or the third electrode 70 and the fourth electrode 80 of the semiconductor light-emitting element 1, 1' are respectively bonded to the circuit bonding pads 6a and 6b on the display substrate 90 by flip-chip method.

FIG. 11 is a cross-sectional view of a display backlight unit BL according to an embodiment of the present disclosure. The display backlight unit BL includes a bottom shell 700, in which a light source module 71 is accommodated, and an optical film 72 is arranged above the light source module 71. The optical film 72 is, for example, a light diffuser. In some embodiments, the backlight unit BL is a direct-type backlight unit. The light source module 71 includes a circuit carrier 710 and a plurality of light sources 711 mounted and arranged on its upper surface. In some embodiments, the light source 711 includes a semiconductor light-emitting element 1, 1' of any of the aforementioned embodiments, which is mounted on the upper surface of the circuit carrier 710 in a flip-chip manner. In some embodiments, the light source 711 includes a light-emitting element package PKG, in which a semiconductor light-emitting element 1, 1' of any of the aforementioned embodiments is encapsulated, which is mounted on the upper surface of the circuit carrier 710 in a flip-chip manner. In some embodiments, a single light-emitting device package PKG encloses a plurality of semiconductor light-emitting devices 1, 1'.

However, the above embodiments are only for illustrative purposes to illustrate the principles and effects of this application, and are not intended to limit this application. Any person with ordinary knowledge in the technical field to which this application belongs can modify and change the above embodiments without violating the technical principles and spirit of this application. All equivalent changes and modifications made according to the shape, structure, features and spirit described in the patent scope of this application should be included in the patent scope of this application.

1, 1': semiconductor light-emitting element 10: substrate 100: exposed area 10a: upper surface 11: feature part 11a: top 12: recessed area 20: semiconductor stack 20b: side surface 201: first semiconductor layer 201a: upper surface 202: second semiconductor layer 202a: upper surface 203: active layer 30: first electrode 31: first contact part 32: second extension part 40: second electrode 41: second contact part 42: second extension part 50: first protective structure 50a: first upper surface 50b: first lower surface 52: turning area 54: crack 60: second protective structure 60a: second upper surface 60b: second lower surface 70: third electrode 80: fourth electrode D1, D2: distance θ: angle L1: light-emitting device 51: package substrate 511: first pad 512: second pad 53: insulation part RF: reflection structure L2: light-emitting device 602: lampshade 604: reflector 606: carrier 608: light-emitting unit 610: light-emitting module 612: lamp holder 614: heat sink 616: connection part 618: electrical connection element M: display 90: display substrate 901: display area 902: non-display area PX: pixel unit PX_A: first sub-pixel PX_B: second sub-pixel PX_C: third sub-pixel PKG: light-emitting element package 6a, 6b: circuit bonding pads 6c, 6d: electrodes BL: backlight unit 700: bottom shell 71: light source module 710: circuit carrier 711: light source 72: optical film

FIG. 1 is a top view of an embodiment of a semiconductor light emitting device disclosed herein.

FIG. 2 is a cross-sectional view of the semiconductor light emitting element taken along line segment A-A' in FIG. 1.

FIG. 3 is a scanning electron microscopy (SEM) photograph of a local cross-section of an embodiment of a semiconductor light-emitting element disclosed herein.

FIG. 4 is a partially enlarged SEM photograph of the electrode and the first semiconductor layer in FIG. 3, and the recessed area formed therebetween.

FIG. 5 is a cross-sectional view of another embodiment of a semiconductor light emitting device disclosed herein.

FIG6 is a cross-sectional view of another embodiment of a semiconductor light emitting element disclosed herein.

FIG. 7 is a schematic diagram of an embodiment of a light emitting device L1 disclosed herein.

FIG. 8 is a schematic top view of an embodiment of a light emitting device L2 disclosed herein.

FIG. 9 is a schematic top view of an embodiment of a display M disclosed herein.

FIG. 10 is a cross-sectional view of a pixel unit PX in FIG. 9 .

FIG. 11 is a cross-sectional view of an embodiment of a display backlight unit BL disclosed herein.

without

10: Substrate

11: Features Department

12: Depression area

201: First semiconductor layer

201a: Upper surface

32: First extension part

50: First protection structure

50a: first upper surface

52: Turning point

60: Second protection structure

60a: Second upper surface

Claims (10)

A semiconductor light-emitting element comprises: a semiconductor stack; a recessed area; a first protective structure formed on the semiconductor stack and comprising a first upper surface and a turning area formed corresponding to the recessed area, wherein the first protective structure comprises a crack; and a second protective structure located in the crack; wherein the second protective structure is non-metallic and comprises an organic material or an inorganic material. The semiconductor light-emitting element as described in claim 1 further includes an electrode located on the semiconductor stack, wherein the semiconductor stack includes a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer. A semiconductor light-emitting element as described in claim 2, wherein the recessed area is located between the semiconductor stack and the electrode. A semiconductor light-emitting element as described in claim 1 or claim 3, wherein the crack is formed corresponding to the recessed area. A semiconductor light-emitting element as described in claim 1, wherein the first protective structure comprises a DBR structure. A semiconductor light-emitting element as described in claim 5, wherein the first protective structure includes a first bottom layer located below the DBR structure, and/or the first protective structure includes a second bottom layer located above the DBR structure. A semiconductor light-emitting element as described in claim 6, wherein the first bottom layer or the second bottom layer comprises a plurality of sub-layers. A semiconductor light-emitting element as described in claim 1, wherein the second protective structure comprises a flowable material. A semiconductor light-emitting element as described in claim 8, wherein the organic material comprises a photosensitive material or a polymer material. A semiconductor light-emitting element as described in claim 9, wherein the photosensitive material comprises Su-8 or benzocyclobutene (BCB).

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