TW202249092A - Ohmic contact manufacturing method of group III-nitride semiconductor component characterized by reducing the contact resistance of the group III-nitride semiconductor component - Google Patents

Abstract

The present invention provides an ohmic contact manufacturing method capable of reducing the contact resistance of the group III-nitride semiconductor component, which mainly uses fluoride gas plasma to perform etching and surface treatment and performs annealing treatment to realize the ohmic contact of ultra-low contact resistance. The present manufacturing method does not cause damage to the surface of the semiconductor channel, the whole manufacturing process is relatively simple, and the group III-nitride semiconductor component produced by the present manufacturing method has excellent reliability and can be used in the group III-nitride transistors and the diodes.

Description

A kind of ohmic contact manufacturing method of group III nitride semiconductor device

The present invention relates to a III-nitride semiconductor device, and in particular to a method for manufacturing an ohmic contact of the III-nitride semiconductor device.

Nowadays, in the field of power electronics, it is a future trend to introduce wide bandgap semiconductor components to improve the energy efficiency of equipment and modules and reduce energy consumption. In particular, gallium nitride high-frequency power components, due to their excellent performance, have become the most promising semiconductor components in the next generation of high-power and high-frequency devices that exceed the limit of silicon materials. Group III nitride semiconductor devices, such as gallium nitride (GaN) semiconductor high electron mobility transistors (HEMTs), usually form a two-dimensional electron gas (2DEG, two-dimensional electron gas) to achieve high frequency operation with high power output.

Taking metal-insulator-semiconductor (MIS) high electron mobility (HEMT) group III nitride semiconductor devices as an example, the turn-on resistance is roughly related to the contact resistance, the resistance between the source and gate of the two-dimensional electron gas , the resistance between the gate and the drain of the two-dimensional electron gas and the channel resistance, among which the contact resistance accounts for the largest part of the turn-on resistance, so it is necessary to reduce its resistance value in the design to become an ohmic contact, so as to achieve high on-state current and low Power loss, low heat generation and long life cycle.

There are two known methods of reducing contact resistance in the formation of ohmic contacts, which are described below. One of them is to etch the contact electrode region of the barrier layer and re-grow heavily doped N-type channel layer (for example, N+ GaN layer) on both sides of the barrier layer and on the channel layer, and then form Ti/Au metal source and drain to form ohmic contacts on the N-type channel layer. However, this method may have the following disadvantages: low yield rate; high manufacturing cost; damage to the inside of the barrier layer after etching causes defects and easily causes leakage; and requires complex and expensive molecular beam epitaxy (MBE) to re- A heavily doped N-type channel layer is grown.

Another approach to reduce contact resistance is to selectively bury the source and gate portions of the Ti/Au metal in the barrier layer. However, this approach may have the following disadvantages: it is difficult to control the etch depth and sidewall slope accuracy; there may be non-uniformity in the wafer-scale wafer process; there may be residue and etch damage; and it is very difficult A HEMT group III nitride semiconductor element with an ultra-thin AlN or Al(Ga)N barrier layer is realized (note: because it is not easy to control the etching depth). Accordingly, there is still an urgent need in the industry for a low-complexity, low-cost and high-yield ohmic contact manufacturing method with low contact resistance.

According to the object of the present invention, a method for manufacturing an ohmic contact of a III-nitride semiconductor device is provided, and the III-nitride semiconductor device includes a transistor and a diode. The manufacturing method of the ohmic contact of the group III nitride semiconductor device includes: providing a group III nitride semiconductor structure without forming source and drain electrodes; forming a protective layer on the barrier layer of the group III nitride semiconductor structure; Form a mask layer with a pattern (for example, a photoresist layer or other material layer that can resist fluoride gas plasma corrosion) to define the position of the source and drain; use fluoride gas plasma to III-nitride The protective layer of the semiconductor structure is etched, wherein the part of the protective layer corresponding to the position of the source and the drain is etched at least to the surface of the barrier layer; using fluoride gas plasma to expose the barrier of the Group III nitride semiconductor structure Surface treatment of the barrier layer; removal of the mask layer, and annealing; after the annealing, implanting metal at the position of the source and the drain to form the source and the drain; and forming the source and the drain Rapid annealing is performed on the III-nitride semiconductor structure of the drain.

According to the purpose of the present invention, there is provided a semi-finished product of a group III nitride semiconductor element, which is manufactured by using the ohmic contact manufacturing method of the aforementioned group III nitride semiconductor element, including: a group III nitride semiconductor structure; and a protective layer, source and The drain is formed on the barrier layer of the III-nitride semiconductor structure.

According to the purpose of the present invention, there is provided a III-nitride semiconductor device, which includes another III-nitride semiconductor device semi-finished and a gate formed by removing part of the protective layer of the above-mentioned III-nitride semiconductor device semi-finished product , wherein the gate is formed on the barrier layer and is located between the source and the drain in the horizontal direction.

In a word, compared with the prior art, the ohmic contact manufacturing method of the III-nitride semiconductor device provided by the embodiment of the present invention has technical effects such as low manufacturing cost, high production yield and simple manufacturing process.

For the benefit of the examiner to understand the technical features, content and advantages of the present invention and the effects that can be achieved, the present invention is hereby described in detail in the form of embodiments in conjunction with the accompanying drawings, and the drawings used therein, its The subject matter is only for illustration and auxiliary instructions, and not necessarily the true proportion and precise configuration of the present invention after implementation, so it should not be interpreted based on the proportion and configuration relationship of the attached drawings, and limit the scope of rights of the present invention in actual implementation. Together first describe.

In order to solve the technical problems of low manufacturing yield and high manufacturing cost of the ohmic contact of the III-nitride semiconductor device in the prior art, the present invention proposes a novel and feasible manufacturing method for reducing the ohmic contact of the III-nitride semiconductor device, which will not The surface damage of the semiconductor channel is caused, the overall manufacturing process is relatively simple, and the reliability of the manufactured III-nitride semiconductor device is good, and even the resistivity of the contact resistance can reach as low as 0.1 ohm·mm. Further, the ohmic contact manufacturing method for reducing the contact resistance of the III-nitride semiconductor device of the present invention is mainly to form a protective layer on the barrier layer on the III-nitride semiconductor structure without the source electrode and the drain electrode, and then, After defining a pattern through a mask material (for example, photoresist), use fluoride gas plasma to perform etching and surface treatment on the protective layer not covered by the mask material, then remove the photoresist, and perform annealing treatment, Metal is implanted to form the source and gate, and finally rapid annealing is performed to achieve ohmic contact with ultra-low contact resistance.

In the manufacturing method of the ohmic contact of the group III nitride semiconductor device of the present invention, due to the existence of the protective layer, the fluoride gas plasma treatment will not damage the surface of the channel layer, and by controlling the power and processing time, the fluorine ions will not will penetrate to the channel layer. In addition, the annealing treatment can remove residual fluoride ions. Accordingly, the ohmic contact manufacturing method for reducing the contact resistance of III-nitride semiconductor devices according to the embodiment of the present invention has technical effects such as low manufacturing cost, high production yield and simple manufacturing process. In addition, an embodiment of the present invention also provides a III-nitride semiconductor device and a semi-finished product manufactured by using the method for manufacturing an ohmic contact of the III-nitride semiconductor device.

Please refer to FIG. 2H , a schematic cross-sectional view of a semi-finished Group III nitride semiconductor device according to an embodiment of the present invention is shown in FIG. 2H . The III-nitride semiconductor structure 11 includes the III-nitride semiconductor structure 11 without the source 12 and the drain 13, the source 12, the drain 13 and the protection layer 14, wherein the source 12, the drain 13 and the protection layer 14 Located on the surface of the barrier layer 115 of the III-nitride semiconductor structure 11 , and in the horizontal direction, part of the passivation layer 14 is located between the sidewalls of the source 12 and the sidewalls of the drain 13 . Due to the etching and surface treatment by fluoride gas plasma, and the vacuum annealing treatment and rapid annealing treatment, the resistivity of the source electrode 12 and the drain electrode 13 relative to the contact resistance of the barrier layer 115 can reach 0.1 to 0.2 ohm·km centimeters (including 0.1 and 0.2 ohm mm).

In the embodiment of the present invention, the protection layer 14 is a dielectric material, and may be a SiN _x layer, a SiO ₂ layer or a Si layer, where x represents any number greater than 0. The thickness of the protective layer 14 can be selected between 5 and 100 nm (including 5 nm and 100 nm), preferably, between 5 and 40 nm (including 5 nm and 40 nm) . In addition, the thickness selection of the protective layer 14 is related to the material, fluoride gas plasma power and processing time, and its main purpose is to protect the two-dimensional electron gas (2DEG) layer 1141 from damage during the fluoride gas plasma treatment. Each of the source 12 and the drain 13 may be a metal stack structure, which includes a first structural layer and a second structural layer arranged from bottom to top, the first structural layer may be a Ti/Al double-layer structure, and the second structural layer may be a Ti/Al double-layer structure. The two-structure layer may be a Ni/Au double-layer structure, a Ti/Ta double-layer structure, a Ti layer, a TiN layer, a Cu layer or a W layer, and the present invention is not limited thereto.

In the embodiment of FIG. 1 and FIG. 2A to FIG. 2H, the III-nitride semiconductor structure 11 is a HEMT semiconductor structure, and the final III-nitride semiconductor device semi-finished product 1 does not have a gate, so it can be used as a HEMT diode , but the present invention is not limited thereto, and in other embodiments, the III-nitride semiconductor element semi-finished product 1 may be formed with a gate, and in the horizontal direction, the gate is located on the sidewall of the source 12 and the drain 13 between the side walls. The III-nitride semiconductor structure 11 includes a substrate 111, a nucleation layer 112, a buffer layer 113, a channel layer 114, and a barrier layer 115, wherein the nucleation layer 112 is formed on the surface of the substrate 111, and the buffer layer 113 is formed On the surface of the nucleation layer 112 , the channel layer 114 is formed on the surface of the buffer layer 113 , and the barrier layer 115 is formed on the surface of the channel layer 114 . In the III-nitride semiconductor structure 11 , the two-dimensional electron gas layer 1141 is formed in the interface between the channel layer 114 and the barrier layer 115 .

The substrate 111 is, for example, silicon, silicon-on-insulator (SOI), silicon carbide (SiC), sapphire substrate or other substrates capable of epitaxial III-nitride semiconductors, and the present invention is not limited thereto. The nucleation layer 112 is, for example, a low-temperature GaN layer, a low-temperature AlN layer, a high-temperature GaN layer or a high-temperature AlN layer, and the present invention is not limited thereto. The buffer layer 113 can be, for example, an AlN layer, an AlGaN layer, an InGaN layer, a super crystal (super lattice) AlN/GaN layer, a super crystal AlGaN/GaN layer, a super crystal AlN/AlGaN, a carbon-doped GaN layer, an iron-doped GaN layer or an undoped GaN layer, and the present invention is not limited thereto. When the buffer layer 113 is an AlGaN layer, the chemical composition formula of AlGaN is _{AlyGa1 -yN} , 5%<=y. The channel layer 114 can be, for example, a GaN layer, an AlGaN layer, an InN layer or an InGaN layer, and the present invention is not limited thereto. The barrier layer 115 can be, for example, an AlGaN layer, an InAlN layer, an InAlGaN layer, an InGaN layer or an AlN layer, and the present invention is not limited thereto. When the barrier layer 115 is an AlGaN layer, the chemical composition formula of AlGaN is AlxGa1 _{- xN} , 0<=x<=40%, for example, x can be 20%, and the thickness of the barrier layer 115 is 20 nanometers m, and the sheet resistance value of the two-dimensional electron gas layer 1141 at this time is <450 ohm/□.

Please refer to Fig. 1, Fig. 2A to Fig. 2H, Fig. 1 is the flow chart of the manufacturing method of reducing the ohmic contact of Group III nitride semiconductor device of the embodiment of the present invention, and Fig. 2A to Fig. 2H is the III of the embodiment of the present invention Schematic cross-sectional view of each step of the ohmic contact manufacturing method of the group nitride semiconductor device.

First, in step S31, a III-nitride semiconductor structure 11 having no source 12 and drain 13 and having a two-dimensional electron gas as shown in FIG. 2A is provided, which is similar in structure to the III-nitride semiconductor in FIG. 1 Structure 11. Next, in step S32, a protection layer 14' is formed on the barrier layer 115 of the III-nitride semiconductor structure 11, as shown in FIG. (PECVD) deposition method, the material of the protective layer 14 ′ is as mentioned above, and the thickness is selected from below 40 nm, for example, 10, 20 or 40 nm. In addition, the way of depositing the protective layer 14' can be in-situ metal organic vapor phase epitaxy (in-situ MOCVD), any chemical vapor deposition (CVD), any physical vapor deposition (PVD) or any atomic layer deposition (ALD). Afterwards, in step S33 , a patterned mask layer 17 is formed on the protection layer 14 ′ to define the positions of the source 12 and the drain 13 , as shown in FIG. 2C .

Next, in step S34, the protective layer 14' of the group III nitride semiconductor structure 11 is etched by dry etching using fluoride gas plasma, as shown in FIG. 2D; in step S35, using fluoride gas plasma The slurry is surface treated as shown in Figure 2E. Etching and surface treatment, for example, can generate CF4 plasma through an inductively coupled plasma (ICP) system, wherein the portion of the protection layer ₁₄ corresponding to the source electrode 12 and the drain electrode 13 will be etched to the surface of the barrier layer 115. The process of forming the protective layer 14 and realizing the ohmic region. The power of the fluoride gas plasma is selected from 50 to 300 watts (including 50 and 300 watts), and the treatment time is selected from 5 to 300 seconds (including 5 and 300 seconds), preferably selected from 5 to 300 seconds Between 50 seconds (including 5 and 50 seconds). When the thickness of the protection layer 14' is between 10 and 40 nm, the processing time may be 50 seconds, and the optimum thickness of the protection layer 14' is 30 nm. In addition, in addition to CF ₄ plasma, SF ₆ , CHF ₃ or C ₄ F ₈ plasma can also be selected, and Ar plasma can be mixed more selectively. Furthermore, in addition to the inductively coupled plasma system, a reactive ion etching (RIE) or inductively coupled plasma-reactive ion etching (ICP-RIE) system may also be selected. When the protective layer 14' is about 20 nm, the fluoride gas plasma treatment for about 30 and 50 seconds can reduce the resistivity of the original contact resistance from 0.8 to 0.44 and 0.2 ohm·mm, respectively. Incidentally, the type, power and processing time of the fluoride gas plasma for etching and surface treatment may be the same or different from each other.

Next, in step S36 , the mask layer 17 is removed, and the surface heat treatment is performed by vacuum annealing to remove fluorine ion bonds, as shown in FIG. 2F . The annealing treatment here can be a multi-step annealing treatment or a single-step annealing treatment, for example, the number of steps of the annealing treatment is preferably 1 to 4 (including 1 and 4). Then, after the annealing treatment, in step S37, the metal is implanted, as shown in FIG. 2G. The metal implantation method can be, for example, deposited through an electron beam gun to form the source 12 and the drain 13 . The annealing treatment can be performed in a vacuum chamber or in an Ar environment, and other gases can be introduced in the Ar environment. The annealing treatment may be rapid annealing treatment or other types of annealing treatment, the temperature of the annealing treatment is approximately between 450 degrees Celsius and 650 degrees Celsius (including 450 and 650 degrees), and the total time of the annealing treatment is approximately between 30 and 240 seconds ( Including 30 and 240 seconds), if multi-step annealing treatment is performed, the time of each step is between 15 and 60 seconds (including 15 and 60 seconds).

Then, in step S38, rapid annealing is performed to achieve ultra-low contact resistance, as shown in Figure 2H, wherein the temperature of rapid annealing is 750 to 850 degrees Celsius (including 750 and 850 degrees), and the total time of rapid annealing is about 10 to 60 seconds (including 10 and 60 seconds, preferably 30 seconds), and the resistivity of the contact resistance can be reduced to 0.1 to 0.15 ohm·mm.

Please refer to FIG. 3A . FIG. 3A is a schematic cross-sectional view of a III-nitride semiconductor device according to an embodiment of the present invention. In FIG. 3A , the III-nitride semiconductor device 3 is a HEMT III-nitride semiconductor device. The Group III nitride semiconductor element 3 is realized as follows. First, mesa etching is performed on the semi-finished Group III nitride semiconductor device 1 shown in FIG. 2H to define an isolation region RI. Next, a portion of the protection layer 14 between the source 12 and the drain 13 in the horizontal direction is removed to define a gate region. Next, the gate 15 on the barrier layer 115 is formed at the gate region.

Please refer to FIG. 3B . FIG. 3B is a schematic cross-sectional view of a III-nitride semiconductor device according to another embodiment of the present invention. Different from the embodiment shown in FIG. 3A , after the group III nitride semiconductor device 4 removes part of the protective layer 14 , a dielectric layer with a thickness of approximately 1 to 10 nm (including both endpoints of 1 and 10 nm) is deposited. Layer 88 is over capping layer 14 and barrier layer 115 at the gate region. Gate 15 is then formed over dielectric layer 88 at the gate region.

Please refer to FIG. 3C . FIG. 3C is a schematic cross-sectional view of a III-nitride semiconductor device according to another embodiment of the present invention. Different from the embodiment shown in FIG. 3B , when the III-nitride semiconductor device 5 removes part of the protection layer 14 , part of the barrier layer 115 is further removed, so the gate 15 is located above the recess of the barrier layer 115 .

Specifically, the ohmic contact manufacturing method for reducing the contact resistance of III-nitride semiconductor devices according to the embodiment of the present invention uses fluoride gas plasma treatment and annealing treatment with a protective layer to reduce the contact resistance twice, so the contact resistance The resistivity can be effectively reduced. Furthermore, compared with the prior art, the ohmic contact manufacturing method of the III-nitride semiconductor device according to the embodiment of the present invention has technical effects such as low manufacturing cost, high production yield and simple manufacturing process.

Looking at the above, it can be seen that the present invention has indeed achieved the effect of the desired enhancement under the breakthrough of the previous technology, and it is not easy for those who are familiar with the art to think about it. Moreover, the present invention has not been disclosed before the application, and its features Progressiveness and practicability have obviously met the requirements for patent application. I file a patent application in accordance with the law. I sincerely request your office to approve this invention patent application to encourage inventions. I am very grateful.

The above-described embodiments are only to illustrate the technical ideas and characteristics of the present invention, and its purpose is to enable those skilled in this art to understand the content of the present invention and implement it accordingly, and should not limit the patent scope of the present invention. That is to say, all equivalent changes or modifications made according to the spirit disclosed in the present invention should still be covered by the patent scope of the present invention.

1: Semi-finished products of III-nitride semiconductor components 3~5: Group III nitride semiconductor devices 11: III-nitride semiconductor structure 111: Substrate 112: nucleation layer 113: buffer layer 114: Channel layer 115: barrier layer 12: source 13: drain 14, 14': protective layer 15:Gate 88:Dielectric layer 17: mask layer S31～S38: steps RI: isolated area 1141: Two-dimensional electron gas layer

The multiple drawings of the present invention are only used to make the present invention easy to be understood by those skilled in the art to which the present invention belongs, and the dimensions and configuration relationships thereof are only for illustration, and are not used to limit the present invention. A brief description of each of the drawings is as follows : Fig. 1 is the flow chart of the manufacturing method of the ohmic contact resistance of the group III nitride semiconductor element of the embodiment of the present invention; 2A to 2H are schematic cross-sectional views of each step of the method for manufacturing the ohmic contact resistance of the III-nitride semiconductor device according to the embodiment of the present invention; 3A is a schematic cross-sectional view of a III-nitride semiconductor device according to an embodiment of the present invention; 3B is a schematic cross-sectional view of a III-nitride semiconductor device according to another embodiment of the present invention; 3C is a schematic cross-sectional view of a III-nitride semiconductor device according to yet another embodiment of the present invention.

1: Semi-finished products of III-nitride semiconductor components

11: III-nitride semiconductor structure

111: Substrate

112: nucleation layer

113: buffer layer

114: Channel layer

115: barrier layer

12: source

13: drain

14: Protective layer

1141: Two-dimensional electron gas layer

Claims (13)

A method for manufacturing an ohmic contact of a III-nitride semiconductor device, comprising: providing a Group III nitride semiconductor structure (11') without forming a source (12) and a drain (13); forming a protective layer (14') on a barrier layer (115) of the III-nitride semiconductor structure (11); forming a patterned mask layer (17) on the protective layer (14') to define the positions of the source (12) and the drain (13); Etching the protection layer (14') of the III-nitride semiconductor structure (11') using fluoride gas plasma, wherein the protection layer (14') corresponds to the source (12) and the drain The portion at the position of (13) is etched at least to the surface of the barrier layer (115); using the fluoride gas plasma to perform surface treatment on the barrier layer (115) exposed by the III-nitride semiconductor structure (11); and removing the mask layer (17), and performing an annealing treatment; After the annealing treatment, implanting metal at the positions of the source (12) and the drain (13) to form the source (12) and the drain (13); and A rapid annealing treatment is performed on the Group III nitride semiconductor structure (11) formed with the source (12) and the drain (13). The ohmic contact manufacturing method of a group III nitride semiconductor device as claimed in claim 1, wherein the protective layer (14') is a _SiNx layer or a _SiO2 layer, and the thickness of the protective layer (14') is 5 to 100 between nanometers. The method for manufacturing an ohmic contact of a III-nitride semiconductor device according to claim 2, wherein the fluoride gas plasma is CF ₄ , SF ₆ or C ₄ F ₈ plasma. According to the method for manufacturing an ohmic contact of a III-nitride semiconductor device as described in Claim 3, the power of the fluoride gas plasma is between 50 and 300 watts. The method for manufacturing an ohmic contact of a III-nitride semiconductor device according to claim 4, wherein the treatment time of the fluoride gas plasma is between 5 and 300 seconds. The method for manufacturing an ohmic contact of a III-nitride semiconductor device according to Claim 1, wherein the temperature of the annealing treatment is between 450°C and 650°C. The method for manufacturing an ohmic contact of a III-nitride semiconductor device according to Claim 1, wherein the temperature of the rapid annealing treatment is between 750°C and 850°C. The method for manufacturing an ohmic contact of a III-nitride semiconductor device according to claim 1, wherein the barrier layer (115) is an AlGaN layer, and its chemical composition formula is AlxGa1 _{- xN} , 0<=x< =40%, alternatively, the barrier layer (115) is an AlN layer. A semi-finished Group III nitride semiconductor device manufactured using the ohmic contact manufacturing method for a Group III nitride semiconductor device as described in one of Claims 1 to 8, comprising: the III-nitride semiconductor structure (11); and The protection layer (14), the source (12) and the drain (13) are formed on the barrier layer (115) of the III-nitride semiconductor structure (11). The semi-finished Group III nitride semiconductor device according to Claim 9, wherein the resistivity of the contact resistance of the Group III nitride semiconductor device is between 0.1 and 0.2 ohm·mm. A group III nitride semiconductor device, comprising: Another III-nitride semiconductor device semi-finished product (1), which is formed after removing part of the protective layer (14) of a III-nitride semiconductor device semi-finished product (1) as described in Claim 9; and A gate (15), the gate (15) is formed on the barrier layer (115), and is located between the source (12) and the drain (13) in the horizontal direction. The Group III nitride semiconductor device as claimed in claim 11, further comprising: A dielectric layer (88) is located under the gate (15), on the barrier layer (115), and on the protection layer (14). The III-nitride semiconductor device according to claim 11, wherein part of the barrier layer (115) of the III-nitride semiconductor device semi-finished product (1) is further removed to form the barrier layer (115) The other III-nitride semiconductor device semi-finished product (1) has a groove, and the gate (15) is located on the groove.

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