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TW202220139A - 電子封裝件及其線路結構 - Google Patents

電子封裝件及其線路結構 Download PDF

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TW202220139A
TW202220139A TW109139527A TW109139527A TW202220139A TW 202220139 A TW202220139 A TW 202220139A TW 109139527 A TW109139527 A TW 109139527A TW 109139527 A TW109139527 A TW 109139527A TW 202220139 A TW202220139 A TW 202220139A
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layer
circuit
metal layer
layers
metal
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TW109139527A
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蔡芳霖
郭家妤
翁培耕
蔡偉聖
姜亦震
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矽品精密工業股份有限公司
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Priority to TW109139527A priority Critical patent/TW202220139A/zh
Priority to CN202011309537.8A priority patent/CN114496973A/zh
Priority to US17/135,161 priority patent/US11791300B2/en
Publication of TW202220139A publication Critical patent/TW202220139A/zh

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Abstract

一種電子封裝件，其線路部之介電層上係形成有線路層及具有複數開口之金屬層，以降低該金屬層所佔該介電層之面積比例，減少應力集中，避免該電子封裝件發生翹曲。

Description

電子封裝件及其線路結構
本發明係有關一種半導體封裝製程，尤指一種可提升可靠度之電子封裝件及其線路結構。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging，簡稱WLP)的技術。
圖1A至圖1D係為習知晶圓級半導體封裝件1之製法之剖面示意圖。
如圖1A所示，形成一熱化離型膠層(thermal release tape)11於一承載件10上。
接著，置放複數半導體元件12於該熱化離型膠層11上，該些半導體元件12具有相對之作用面12a與非作用面12b，各該作用面12a上均具有複數電極墊120，且各該作用面12a黏著於該熱化離型膠層11上。
如圖1B所示，形成一封裝膠體13於該熱化離型膠層11上，以包覆該半導體元件12。
如圖1C所示，進行烘烤製程以硬化該封裝膠體13，而同時該熱化離型膠層11因受熱後會失去黏性，故可一併移除該熱化離型膠層11與該承載件10，以外露該半導體元件12之作用面12a。
如圖1D所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，以形成一包含有介電層140及線路層141之線路重佈結構14於該封裝膠體13與該半導體元件12之作用面12a上，且令該線路重佈結構14電性連接該半導體元件12之電極墊120，其中，為了提升散熱功效，該線路重佈結構14之表面上佈設有大面積之圖案化金屬層141’，且該圖案化金屬層141’亦可供該半導體元件12作接地或傳遞電源之用。接著，形成一絕緣保護層15於該線路重佈結構14上，且該絕緣保護層15外露該線路重佈結構14之部分表面，以供結合如銲球之導電元件16。最後進行切單製程。
惟，習知半導體封裝件1中，該金屬層141’所佔面積比例過多，且該線路重佈結構14之線路層141之結構強度太弱，致使該線路重佈結構14之應力分佈容易不均，造成該線路重佈結構14之各層介電層140平整度不一致，故該半導體封裝件1容易發生翹曲，導致該線路層141無法有效電性連接該些半導體元件12之電極墊120，致使電性不良，進而造成良率過低及產品可靠度不佳等問題。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種線路結構，係包括：複數介電層；複數線路層，係設於該複數介電層上；至少一第一金屬層， 係設於該複數介電層之其中一者上且具有複數第一開口；以及至少一第二金屬層，係設於該複數介電層之其它至少一者上且具有複數第二開口，以令該第一金屬層及第二金屬層位於不同之介電層上，其中，該第一開口之位置係未對齊該第二開口之位置。
前述之線路結構中，該第一開口及/或第二開口係為矩形。
前述之線路結構中，該第一金屬層及第二金屬層係為虛銅片。
前述之線路結構中，該第一金屬層及第二金屬層係為線路層。
前述之線路結構中，第二金屬層係具有複數個，並設於該複數介電層之未設有第一金屬層之全部，且令位於不同介電層上之二該第二金屬層之第二開口之位置係未相互對齊。
本發明亦提供一種電子封裝件，係包括：包覆層，係具有相對之第一側與第二側；至少一電子元件，係嵌埋於該包覆層中；以及如前述之線路結構，係設於該包覆層之第一側上，且該線路層係電性連接該電子元件。
前述之電子封裝件中，該電子元件係外露於該包覆層之第二側。
前述之電子封裝件中，該第一金屬層及/或第二金屬層係未電性連接該電子元件。
前述之電子封裝件中，該第一金屬層及/或第二金屬層係電性連接該電子元件。
前述之電子封裝件中，復包括埋設於該包覆層中且電性連接該線路層之複數導電柱。
前述之電子封裝件中，復包括形成於該線路結構上且電性連接該線路層之複數導電元件。
由上可知，本發明之電子封裝件及其線路結構中，主要藉由於該介電層上形成具有開口之金屬層，以降低該金屬層所佔該介電層之面積比例，因 而能分散應力之分佈，故相較於習知技術，本發明能避免該線路結構發生翹曲，亦即避免該電子封裝件翹曲，令該線路層能有效電性連接該電子元件，進而提升產品良率及產品可靠度。
再者，藉由各金屬層之開口位置並未對齊，以避免該線路結構發生應力集中之問題，因而能增加該介電層之平整性，故相較於習知技術，本發明更能避免該電子封裝件或該線路結構發生翹曲。
1:半導體封裝件
10,9:承載件
11:熱化離型膠層
12:半導體元件
12a,20a:作用面
12b,20b:非作用面
120,200:電極墊
13:封裝膠體
14:線路重佈結構
140,240,250:介電層
141,241,251,251’:線路層
141’:金屬層
15,253:絕緣保護層
16,26:導電元件
2:電子封裝件
2a:線路結構
20:電子元件
21a:第一金屬層
21b,21c:第二金屬層
210:第一開口
210’,210”:第二開口
22:導電柱
23:包覆層
23a:第一側
23b:第二側
24:線路部
25:增層部
252:導電盲孔
26:導電元件
260:凸塊底下金屬層
3:電子裝置
90:離形層
91:結合層
S:切割路徑
圖1A至圖1D係為習知半導體封裝件之製法之剖面示意圖。
圖2A至圖2D係為本發明之電子封裝件之製法之剖面示意圖。
圖2B’係為圖2B之局部上視圖。
圖2E係為圖2D之後續製程之剖面示意圖。
圖3A、圖3B、圖3C及圖3D係為圖2D之不同態樣之局部上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中 所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2D係為本發明之電子封裝件2之製法的剖面示意圖。
如圖2A所示，提供一具有相對之第一側23a與第二側23b之包覆層23，且該包覆層23中嵌埋有至少一電子元件20及複數導電柱22。
於本實施例中，形成該包覆層23之材質係為絕緣材，如模封材(molding compound)、乾膜(dry film)、聚對二唑苯(Poly-p-Polybenzoxazole，簡稱PBO)、聚醯亞胺(polyimide，簡稱PI)、預浸材(prepreg，簡稱PP)、Ajinomoto build-up film(ABF)、環氧樹脂(epoxy)或光阻材。
再者，該電子元件20係為主動元件、被動元件或其組合者，其中，該主動元件係為半導體晶片，而該被動元件係為電阻、電容及電感。例如，該電子元件20係為半導體晶片，如電源管理晶片、動態隨機存取記憶體、應用處理器等，其具有相對之作用面20a與非作用面20b，該作用面20a具有複數電極墊200，且該電子元件20之非作用面20b齊平該包覆層23之第二側23b。可理解地，於其它實施例中，該包覆層23之第二側23b可覆蓋該電子元件20之非作用面20b。
又，該包覆層23與該電子元件20之製作方式繁多，例如，該包覆層23係以鑄模成型(molding)或壓合(Laminate)方式形成者，但並不限於此方式。具體地，可先將該電子元件20與該些導電柱22設於支撐件(圖略)上，再形成用以包覆該電子元件20與該些導電柱22之包覆層23，之後將該包覆層23之第二側23b結合於一承載件9上，才移除該支撐件。或者，先將該些導電柱22與該電子元件20以其非作用面20b設於該承載件9上，再形成用以包覆該電子元件20與該些導電柱22之包覆層23。
另外，形成該導電柱22之材質係為如銅之金屬材或銲錫材，且該承載件9上可依序形成有一離形層90與一結合層91，使該包覆層23之第二側23b與該電子元件20之非作用面20b結合於該結合層91上。具體地，該離形層90係例如熱化離型膠(thermal release tape)、光感離形膜或機械離形構造，且該結合層91係如黏著材。
如圖2B所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，以形成一線路部24於該包覆層23之第一側23a上，且該線路部24係電性連接該電子元件20與該些導電柱22，並形成一第一金屬層21a於該線路部24上。
於本實施例中，該線路部24係包含至少一介電層240及設於該介電層240之線路區上之線路層241，且該線路層241電性連接該電子元件20之電極墊200與該些導電柱22。
再者，該第一金屬層21a係設於該介電層240之非線路區上，且該第一金屬層21a與該線路層241可一同製作；或者，該第一金屬層21a與該線路層241可採用不同製程製作。因此，該第一金屬層21a之材質與該線路層241之材質可相同(如銅材)或不相同。
又，該第一金屬層21a係為網狀體(mesh)，其具有複數第一開口210，如圖2B’所示。應可理解地，該第一開口210之輪廓與數量不限於圖中所示之矩形(如正方形或如圖3B所示之長方形)，亦可為其它數量或其它形狀之輪廓。
如圖2C所示，進行另一線路重佈層(RDL)製程，以形成一增層部25於該線路部24與該第一金屬層21a上，以令該增層部25與該線路部24作為線路結構2a，且形成至少一第二金屬層21b,21c於該增層部25上。之後，形成複數導電元件26於該增層部25上。
於本實施例中，該增層部25具有至少一結合該第二金屬層21b,21c之介電層250、形成於該些介電層250上之線路層251,251’、及設於該些介電層250中的複數導電盲孔252，且藉由該些導電盲孔252電性連接該些線路層241,251，而該增層部25之最外側介電層250與線路層251’係形成有一絕緣保護層253，以令該最外側之部分線路層251’外露於該絕緣保護層253，俾供結合該些導電元件26於該線路層251’上。
再者，該第二金屬層21b,21c係設於該介電層250之非線路區上，且該第二金屬層21b,21c與該線路層251,251’可一同製作；或者，該第二金屬層21b,21c與該線路層251,251’可採用不同製程製作。因此，該第二金屬層21b,21c之材質與該線路層251之材質可相同(如銅材)或不相同。
請同時配合參閱圖3A至圖3D，該第二金屬層21b,21c係為網狀體(mesh)，其具有複數第二開口210’,210”，以令該線路層251沿該第二金屬層21b,21c之邊緣間隔佈設。應可理解地，該第二開口210’,210”之輪廓與數量不限於圖中所示之矩形(如正方形或長方形)，亦可為其它數量或其它形狀之輪廓。較佳者，相鄰兩層(即上下兩層)之金屬層之開口位置並未對齊，如圖3A、圖3B、圖3C及圖3D所示之相互錯位。
另外，該導電元件26係為銲球、金屬凸塊或金屬針等，且於形成該導電元件26前，可先於該線路層251’上形成凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)260，以利於結合該導電元件26。
如圖2D所示，移除該承載板9、離形層90及該結合層91，使該電子元件20之非作用面20b係外露於該包覆層23之第二側23b。之後，沿如圖2C所示之切割路徑S進行切單製程，以完成該電子封裝件2之製作。
於本實施例中，該第一金屬層21a及第二金屬層21b,21c係作為虛銅片(dummy Cu)，其未電性連接該電子元件20；或者，該第一金屬層21a及第二 金屬層21b,21c可依需求作為線路層，其電性連接該電子元件20之部分電極墊210，以供該電子元件20作散熱、接地及/或傳遞電源之用。
再者，於後續製程中，該電子封裝件2可藉由該些導電元件26結合至一如電路板之電子裝置3上，如圖2E所示。
本發明之電子封裝件2之線路結構2a主要藉由該第一金屬層21a及第二金屬層21b,21c具有複數第一開口210及第二開口210’,210”，以降低其所佔該介電層240,250之面積比例，因而能減少應力集中，故相較於習知技術，本發明能避免該線路結構2a發生翹曲，亦即避免該電子封裝件2翹曲，令該線路層241能有效電性連接該電子元件20，進而提升產品良率及產品之可靠度。
再者，藉由任兩層或相鄰兩層(即上下兩層)之金屬層之開口位置並未對齊，如圖3A、圖3B、圖3C及圖3D所示之相互錯位，以減少該線路結構2a發生應力集中之問題，因而能增加該介電層240,250之平整性，避免該電子封裝件2或該線路結構2a發生翹曲。
本發明提供一種線路結構2a，係包括：複數介電層240,250、設於該複數介電層240,250上之複數線路層241,251,251’、至少一第一金屬層21a以及至少一第二金屬層21b,21c。
所述之第一金屬層21a係設於該複數介電層240之其中一者上且具有複數第一開口210。
所述之第二金屬層21b,21c係設於該複數介電層250之其它至少一者上且具有複數第二開口210’,210”(該第一金屬層21a及第二金屬層21b,21c係位於不同層)，其中，該第一開口210之位置係未對齊該第二開口210’,210”之位置。
於一實施例中，該第一開口210及/或第二開口210’,210”係為矩形。
於一實施例中，該第一金屬層21a及第二金屬層21b,21c係為虛銅片。
於一實施例中，該第一金屬層21a及第二金屬層21b,21c係為線路層。
於一實施例中，複數第二金屬層21b,21c係設於未設有第一金屬層21a之該複數介電層250之全部，且令位於不同介電層250上之二該第二金屬層21b,21c之該第二開口210’,210”之位置係未相互對齊。
本發明亦提供一種電子封裝件2，係包括：一包覆層23、至少一電子元件20以及該線路結構2a。
所述之包覆層23係具有相對之第一側23a與第二側23b。
所述之電子元件20係嵌埋於該包覆層23中。
所述之線路結構2a係設於該包覆層23之第一側23a上，且該線路層241係電性連接該電子元件20。
於一實施例中，該電子元件20係外露於該包覆層23之第二側23b。
於一實施例中，該第一金屬層21a及/或第二金屬層21b,21c係未電性連接該電子元件20。
於一實施例中，該第一金屬層21a及/或第二金屬層21b,21c係電性連接該電子元件20。
於一實施例中，該電子封裝件2復包括埋設於該包覆層23中且電性連接該線路層241之複數導電柱22。
於一實施例中，該電子封裝件2復包括形成於該線路結構2a上且電性連接該線路層251’之複數導電元件26。
綜上所述，本發明之電子封裝件及其線路結構，主要藉由網狀體金屬層之設計，以降低其所佔該介電層之面積比例，因而能減少應力集中，故本發明能避免該線路結構發生翹曲，亦即避免該電子封裝件翹曲，令該線路層能有效電性連接該電子元件，進而提升產品良率及產品之可靠度。
再者，藉由各金屬層之開口位置並未對齊，以減少該線路結構發生應力集中之問題，增加該介電層之平整性，避免該電子封裝件或該線路結構發生翹曲。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
21a:第一金屬層
210:第一開口
24:線路部
240:介電層
241:線路層

Claims (11)

  1. 一種線路結構，係包括：
    複數介電層；
    複數線路層，係設於該複數介電層上；
    至少一第一金屬層，係設於該複數介電層之其中一者上且具有複數第一開口；以及
    至少一第二金屬層，係設於該複數介電層之其它至少一者上且具有複數第二開口，以令該第一金屬層及第二金屬層位於不同之介電層上，其中，該第一開口之位置係未對齊該第二開口之位置。
  2. 如請求項1所述之線路結構，其中，該第一開口及/或第二開口係為矩形。
  3. 如請求項1所述之線路結構，其中，該第一金屬層及第二金屬層係為虛銅片。
  4. 如請求項1所述之線路結構，其中，該第一金屬層及第二金屬層係為線路層。
  5. 如請求項1所述之線路結構，其中，該第二金屬層係具有複數個，並設於該複數介電層之未設有第一金屬層之全部，且令位於不同介電層上之二該第二金屬層之第二開口之位置係未相互對齊。
  6. 一種電子封裝件，係包括：
    包覆層，係具有相對之第一側與第二側；
    至少一電子元件，係嵌埋於該包覆層中；以及
    如請求項1至5之其中一者所述之線路結構，係設於該包覆層之第一側上，且令該線路層係電性連接該電子元件。
  7. 如請求項6所述之電子封裝件，其中，該電子元件係外露於該包覆層之第二側。
  8. 如請求項6所述之電子封裝件，其中，該第一金屬層及/或第二金屬層係未電性連接該電子元件。
  9. 如請求項6所述之電子封裝件，其中，該第一金屬層及/或第二金屬層係電性連接該電子元件。
  10. 如請求項6所述之電子封裝件，其中，復包括埋設於該包覆層中且電性連接該線路層之複數導電柱。
  11. 如請求項6所述之電子封裝件，其中，復包括形成於該線路結構上且電性連接該線路層之複數導電元件。
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