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TWI854498B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TWI854498B
TWI854498B TW112106316A TW112106316A TWI854498B TW I854498 B TWI854498 B TW I854498B TW 112106316 A TW112106316 A TW 112106316A TW 112106316 A TW112106316 A TW 112106316A TW I854498 B TWI854498 B TW I854498B
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layer
wiring layer
electronic package
circuit structure
manufacturing
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TW112106316A
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TW202435401A (zh
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蔡芳霖
蔡偉聖
羅崑源
翁培耕
楊昇樺
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矽品精密工業股份有限公司
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Priority to TW112106316A priority Critical patent/TWI854498B/zh
Priority to CN202310253820.0A priority patent/CN118538699A/zh
Priority to US18/327,097 priority patent/US20240282655A1/en
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Publication of TWI854498B publication Critical patent/TWI854498B/zh

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Abstract

一種電子封裝件及其製法，主要將電子元件係黏貼於一配置有複數導電柱之佈線層上，且以包覆層包覆該電子元件、導電柱與佈線層，並於該包覆層上形成一電性連接該電子元件與導電柱之線路結構，故於該佈線層上可直接形成該些導電柱而省略介電層，因而無需考量介電層之厚度，以利於薄化該電子封裝件。

Description

電子封裝件及其製法
本發明係有關一種半導體封裝製程，尤指一種電子封裝件及其製法。
目前應用於晶片封裝領域之技術，包含有例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組，或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊或PoP(Package on Package)封裝堆疊技術等。
圖1A至圖1G係為習知半導體封裝件1之製法的剖面示意圖。
如圖1A所示，於一承載板9上係形成一佈線層10，再以一如聚醯亞胺(Polyimide，簡稱PI)之介電層16包覆該佈線層10，且該介電層16係以圖案化曝光顯影方式形成有複數開口區160，以令該佈線層10之部分表面外露於該些開口區160，其中，該承載板9係例如為半導體材質之圓形板體，其上以塗佈方式依序形成有一離型層90與一如PI之結合層91，以於該結合層91上結合該佈線層10與該介電層16。
如圖1B所示，於該開口區160之佈線層10上形成複數如銅柱之導電柱14。
如圖1C所示，設置至少一半導體晶片13於該介電層16上，其中，該半導體晶片13係具有相對之作用面13a與非作用面13b，該半導體晶片13係以其非作用面13b藉由膠材133黏固於該介電層16上，且該作用面13a具有複數結合銅凸塊132之電極墊130，並於該作用面13a上可依需求形成有一絕緣層131，以令該絕緣層131覆蓋該些電極墊130與該些銅凸塊132。
如圖1D所示，形成一包覆層15於該介電層16上，以令該包覆層15包覆該半導體晶片13、該絕緣層131(或該些銅凸塊132)與該些導電柱14，再藉由整平製程，令該包覆層15之上表面齊平該絕緣層131之上表面、該導電柱14之端面與該銅凸塊132之端面，使該絕緣層131之上表面、該導電柱14之端面與該銅凸塊132之端面外露出該包覆層15。
如圖1E所示，形成一線路結構19於該包覆層15上，且令該線路結構19電性連接該些導電柱14與該些銅凸塊132，使該半導體晶片13藉由該銅凸塊132電性連接該線路結構19。
所述之線路結構19係包括複數介電層190、及設於該介電層190上之複數線路層191，且最外層之介電層190可作為防銲層，以令最外層之線路層191外露於該防銲層，供結合複數銲球17於最外層之線路層191上，以於後續接置如電路板之電子裝置(圖略)。
如圖1F所示，移除該承載板9及其上之離型層90與結合層91，以外露該介電層16。
如圖1G所示，於該介電層16上形成一如綠漆之防銲層18，且該防銲層18形成有複數開孔180，以令該佈線層10之部分表面外露於該些開孔180。
惟，習知半導體封裝件1中，於形成該介電層16之前，需於該佈線層10之表面進行表面處理作業(如粗糙化製程)，以增加該佈線層10與介電層16之間的黏著力，導致製程繁瑣，因而難以降低該半導體封裝件1之製作成本。
再者，習知半導體封裝件1之製法需於該結合層91上形成PI材之介電層16，故需烘烤該介電層16，因而大幅增加製程時間，導致難以提升製作該半導體封裝件1的產能(throughput)。
又，習知半導體封裝件1之製法需於該介電層16以圖案化曝光顯影方式形成該些開口區160，不僅大幅增加使用製作開口區160所用之曝光機之次數，因而增加該曝光機之損耗，且需考量曝光PI材用之光罩之成本，因而難以降低該半導體封裝件1之製作成本。
另外，習知半導體封裝件1之製法需於該結合層91上形成PI材之介電層16，故習知半導體封裝件1之最終整體厚度需考量該介電層16之厚度，因而難以縮減該半導體封裝件1之最終整體厚度，進而難以符合薄化之需求。
更甚者，由於該包覆層15與該介電層16之材質不相同，兩者之熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)不匹配(mismatch)，因而容易發生熱應力不均勻之情況，致使熱循環(thermal cycle)時，造成該半導體 封裝件1發生翹曲，導致該些銲球17於後續製程無法有效對齊接合該電路板之接點。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：包覆層，係具有相對之第一表面與第二表面；佈線層，係嵌埋於該包覆層之第一表面，以令該佈線層之外表面齊平該包覆層之第一表面；複數導電柱，係接觸結合於該佈線層上並埋設於該包覆層中；至少一電子元件，係藉由黏著層設於該佈線層上並埋設於該包覆層中；以及線路結構，係設於該包覆層之第二表面上並電性連接該電子元件與該導電柱。
本發明亦提供一種電子封裝件之製法，係包括：於一承載板之部分表面上形成一佈線層；於該佈線層上形成複數導電柱，且設置至少一電子元件於該佈線層上；形成一包覆層於該承載板上，以令該包覆層包覆該佈線層、該電子元件與該複數導電柱，其中，該包覆層係具有相對之第一表面與第二表面，使該包覆層以其第一表面結合該承載板；形成一線路結構於該包覆層之第二表面上，以令該線路結構電性連接該複數導電柱與該電子元件；以及移除該承載板，以外露該包覆層之第一表面及該佈線層。
前述之電子封裝件及其製法中，該電子元件係具有相對之作用面與非作用面，該電子元件係以其非作用面藉由該黏著層黏固於該佈線層上，且該作用面具有複數電極墊，以令該線路結構電性連接該複數電極墊。例如，該複數 電極墊上係結合導電體，以令該複數電極墊藉由該導電體電性連接該線路結構。進一步，該導電體之表面係齊平該包覆層之第二表面。
前述之電子封裝件及其製法中，該導電柱之端面係齊平該包覆層之第二表面。
前述之電子封裝件及其製法中，復包括形成複數導電元件於該線路結構上，以令該複數導電元件電性連接該線路結構。
前述之電子封裝件及其製法中，復包括於該包覆層之第一表面與該佈線層上形成絕緣保護層，且該絕緣保護層係具有複數開孔，以令該佈線層之部分表面外露於該些開孔。
由上可知，本發明之電子封裝件及其製法，主要藉由直接於該佈線層上形成導電柱，因而無需於該佈線層之表面進行表面處理作業，即無需進行習知用以增加佈線層與介電層之間的黏著力之相關製程，故相較於習知技術，本發明之製法可簡化製程，以降低該電子封裝件2之製作成本。
再者，本發明之製法因無需於該承載板上形成習知PI材介電層而能省去習知烘烤該介電層之時間，故相較於習知技術，本發明之製法可有效提升製作該電子封裝件的產能(throughput)。
又，本發明之製法因無需於該承載板上形成習知PI材介電層而無需形成開口區，故相較於習知技術，本發明之製法不僅可減少使用製作開口區所用之曝光機之次數，以降低該曝光機之損耗，且可降低曝光介電材用之光罩之成本，以降低該電子封裝件之製作成本。
另外，本發明之製法無需於該承載板上形成習知PI材介電層，故相較於習知技術，本發明之電子封裝件之最終整體厚度可大幅縮減，以符合薄化之需求。
進一步，本發明之製法因無需於該承載板上形成習知PI材介電層，而使該包覆層可直接包覆及接觸該佈線層，故相較於習知技術，本發明之包覆層內部能避免發生CTE不匹配(mismatch)之問題，因而可避免發生熱應力不均勻之情況，以於熱循環時，該電子封裝件不會發生翹曲，使該些導電元件於後續製程能有效對齊接合電路板之接點。
1:半導體封裝件
10,20:佈線層
13:半導體晶片
13a,23a:作用面
13b,23b:非作用面
130,230:電極墊
131,231:絕緣層
132:銅凸塊
133:膠材
14,24:導電柱
15,25:包覆層
16,190,290:介電層
160:開口區
17:銲球
18:防銲層
180,280:開孔
19,29:線路結構
191,291:線路層
2:電子封裝件
23:電子元件
232:導電體
233:黏著層
25a:第一表面
25b:第二表面
27:導電元件
28:絕緣保護層
8:電子裝置
80:接點
9:承載板
90:離型層
91:結合層
S:切割路徑
圖1A至圖1G係為習知半導體封裝件之製法之剖面示意圖。
圖2A至圖2G係為本發明之電子封裝件之製法之剖面示意圖。
圖2H係為圖2G之後續製程之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中 所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2G係為本發明之電子封裝件2之製法之剖面示意圖。
如圖2A所示，於一承載板9之部分表面上以圖案化電鍍銅方式形成一佈線層20。
於本實施例中，該承載板9係例如為半導體材質之圓形板體，其上以塗佈方式依序形成有一離型層90與一如如聚醯亞胺(Polyimide，簡稱PI)之結合層91，以令該佈線層20設於該結合層91之部分表面上。
如圖2B所示，於該佈線層20上形成複數導電柱24。
於本實施例中，該導電柱24係為如銅柱之金屬柱或柱狀銲錫材。例如，以電鍍銅方式形成該導電柱24，但不以此方式為限。
如圖2C所示，設置至少一電子元件23於該佈線層20上，其中，該電子元件23上係結合並電性連接複數導電體232。
於本實施例中，該電子元件23係為主動元件、被動元件或其二者組合，其中，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該電子元件23係為半導體晶片，其具有相對之作用面23a與非作用面23b，該電子元件23係以其非作用面23b藉由如膠材之黏著層233黏固於該佈線層20上，而該作用面23a具有複數電極墊230，以令該導電體232形成於該電極墊230上。
再者，該導電體232係為如銲球之圓球狀、或如銅柱、銲錫凸塊等金屬材之柱狀、或銲線機製作之釘狀(stud)，但不限於此。
又，於該作用面23a上可依需求形成有一絕緣層231，以令該絕緣層231覆蓋該些電極墊230與該些導電體232。或者，亦可令該導電體232外露於該絕緣層231。
如圖2D所示，形成一包覆層25於該結合層91上，以令該包覆層25包覆該佈線層20、該電子元件23、該絕緣層231(或該些導電體232)與該些導電柱24，其中，該包覆層25係具有相對之第一表面25a與第二表面25b，使該包覆層25以其第一表面25a結合該結合層91。
於本實施例中，形成該包覆層25之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)等絕緣材，但並不限於上述。例如，可用壓合(lamination)或模壓(molding)等方式將該包覆層25形成於該結合層91上。
再者，藉由整平製程，以令該包覆層25之第二表面25b齊平該絕緣層231之上表面、該導電柱24之端面與該導電體232之端面，使該絕緣層231之上表面、該導電柱24之端面與該導電體232之端面外露出該包覆層25。例如，該整平製程係藉由研磨方式，移除該導電柱24之部分材質、該絕緣層231之部分材質(依需求，可同時移除該導電體232之部分材質)、與該包覆層25之部分材質。
應可理解地，若該導電體232已外露於該絕緣層231，則移除該絕緣層231之部分材質，即可令該些導電體232外露於該包覆層25(依需求，亦可同時移除該絕緣層231之部分材質與該導電體232之部分材質，而令該些導電體232外露出該包覆層25)。
如圖2E所示，形成一線路結構29於該包覆層25之第二表面25b上，且令該線路結構29電性連接該些導電柱24與該些導電體232，使該電子元件23藉由該些導電體232電性連接該線路結構29。
於本實施例中，該線路結構29係包括複數介電層290、及設於該介電層290上之複數線路層291，如線路重佈層(redistribution layer，簡稱RDL)規格，且最外層之介電層290可作為防銲層，以令最外層之線路層291外露於該防銲層。或者，該線路結構29亦可僅包括單一介電層290及單一線路層291。
再者，形成該線路層291之材質係如銅材，且形成該介電層290之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。
又，形成複數如銲球之導電元件27於最外層之線路層291上。例如，可形成一凸塊底下佈線層(Under Bump Metallurgy，簡稱UBM)於最外層之線路層291上，以利於結合該導電元件27。
如圖2F所示，沿如圖2E所示之切割路徑S進行切單製程，且移除該承載板9及其離型層90與結合層91，以外露該包覆層25之第一表面25a及該佈線層20。
如圖2G所示，於該包覆層25之第一表面25a與該佈線層20上形成一作為防銲層之絕緣保護層28，且該絕緣保護層28係具有複數開孔280，以令該佈線層20之部分表面外露於該些開孔280。
於本實施例中，形成該絕緣保護層28之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它介電材。
另外，於後續製程中，如圖2H所示，該電子封裝件2可藉由回銲該複數導電元件27以接置於一如電路板之電子裝置8之接點80上。
因此，本發明之製法主要藉由直接於該佈線層20上形成導電柱24，因而無需於該佈線層20之表面進行表面處理作業，即無需進行習知用以增加佈線層與介電層之間的黏著力之相關製程，故相較於習知技術，本發明之製法能簡化製程，以降低該電子封裝件2之製作成本。
再者，本發明之製法因無需於該結合層91上形成習知PI材介電層而能省去習知烘烤該介電層之時間，故相較於習知技術，本發明之製法能提升製作該電子封裝件2的產能(throughput)。
又，本發明之製法因無需於該結合層91上形成習知PI材介電層而無需形成開口區，故相較於習知技術，本發明之製法不僅能減少使用製作開口區所用之曝光機之次數，以降低該曝光機之損耗，且能降低曝光介電材用之光罩之成本，以降低該電子封裝件2之製作成本。
另外，本發明之製法無需於該結合層91上形成習知PI材介電層，故相較於習知技術，本發明之電子封裝件2之最終整體厚度能大幅縮減，以符合薄化之需求。
進一步，本發明之製法因無需於該結合層91上形成習知PI材介電層，而使該包覆層25直接包覆及接觸該佈線層20，故相較於習知技術，本發明之包覆層25內部能避免發生熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)不匹配(mismatch)之問題，因而能避免發生熱應力不均勻之情況，以於熱循環(thermal cycle)時(如回銲該導電元件27)，該電子封裝件2不會發生翹 曲，使該些導電元件27於後續製程能有效對齊接合該電子裝置(如電路板)之接點。
本發明亦提供一種電子封裝件，係包括：一包覆層25、一佈線層20、複數導電柱24、至少一電子元件23以及一線路結構29。
所述之包覆層25係具有相對之第一表面25a與第二表面25b。
所述之佈線層20係嵌埋於該包覆層25之第一表面25a中，以令該佈線層20之外表面齊平該包覆層25之第一表面25a。
所述之導電柱24係接觸結合於該佈線層20上並埋設於該包覆層25中。
所述之電子元件23係藉由黏著層233設於該佈線層20上並埋設於該包覆層25中。
所述之線路結構29係設於該包覆層25之第二表面25b上並電性連接該電子元件23與該導電柱24。
於一實施例中，該電子元件23係具有相對之作用面23a與非作用面23b，該電子元件23係以其非作用面23b藉由該黏著層233黏固於該佈線層20上，且該作用面23a具有複數電極墊230，以令該線路結構29電性連接該複數電極墊230。例如，該複數電極墊230上係結合導電體232，以令該複數電極墊230藉由該導電體232電性連接該線路結構29。進一步，該導電體232之端面係齊平該包覆層25之第二表面25b。
於一實施例中，該導電柱24之端面係齊平該包覆層25之第二表面25b。
於一實施例中，所述之電子封裝件2復包括設於該線路結構29上之複數導電元件27，以令該複數導電元件27電性連接該線路結構29。
於一實施例中，所述之電子封裝件2復包括一設於該包覆層25之第一表面25a與該佈線層20上之絕緣保護層28，且該絕緣保護層28係具有複數開孔280，以令該佈線層20之部分表面外露於該些開孔280。
綜上所述，本發明之電子封裝件及其製法，係藉由直接於該佈線層上形成導電柱，因而無需於該佈線層之表面進行表面處理作業，即無需進行習知用以增加佈線層與介電層之間的黏著力之相關製程，故本發明之製法能簡化製程，以降低該電子封裝件之製作成本。
再者，本發明之製法因無需於該承載板上形成習知PI材介電層而能省去習知烘烤該介電層之時間，故本發明之製法能提升製作該電子封裝件的產能。
又，本發明之製法因無需於該承載板上形成習知PI材介電層而無需形成開口區，故本發明之製法不僅能減少使用製作開口區所用之曝光機之次數，以降低該曝光機之損耗，且能降低曝光介電材用之光罩之成本，以降低該電子封裝件之製作成本。
另外，本發明之製法無需於該承載板上形成習知PI材介電層，故本發明之電子封裝件之最終整體厚度能大幅縮減，以符合薄化之需求。
進一步，本發明之製法因無需於該承載板上形成習知PI材介電層，而使該包覆層直接包覆及接觸該佈線層，故本發明之包覆層內部能避免發生熱膨脹係數不匹配之問題，因而能避免發生熱應力不均勻之情況，以於熱循環 時，該電子封裝件不會發生翹曲，使該些導電元件於後續製程能有效對齊接合該電子裝置之接點。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
20:佈線層
23:電子元件
23a:作用面
23b:非作用面
230:電極墊
231:絕緣層
232:導電體
233:黏著層
24:導電柱
25:包覆層
25a:第一表面
25b:第二表面
27:導電元件
28:絕緣保護層
280:開孔
29:線路結構
290:介電層
291:線路層

Claims (14)

  1. 一種電子封裝件，係包括：單一包覆層，係具有相對之第一表面與第二表面；佈線層，係嵌埋於該包覆層之第一表面，且該佈線層之外表面齊平該包覆層之第一表面；複數導電柱，係接觸結合於該佈線層上並埋設於該包覆層中；電子元件，係藉由黏著層設於該佈線層上並埋設於該包覆層中；以及線路結構，係設於該包覆層之第二表面上並電性連接該電子元件與該導電柱。
  2. 如請求項1所述之電子封裝件，其中，該電子元件係具有相對之作用面與非作用面，該電子元件係以其非作用面藉由該黏著層黏固於該佈線層上，且該作用面具有複數電極墊，以令該線路結構電性連接該複數電極墊。
  3. 如請求項2所述之電子封裝件，其中，該複數電極墊上係結合複數導電體，且該複數電極墊藉由該複數導電體電性連接該線路結構。
  4. 如請求項3所述之電子封裝件，其中，該複數導電體之端面係齊平該包覆層之第二表面。
  5. 如請求項1所述之電子封裝件，其中，該複數導電柱之端面係齊平該包覆層之第二表面。
  6. 如請求項1所述之電子封裝件，復包括設於該線路結構上之複數導電元件，以令該複數導電元件電性連接該線路結構。
  7. 如請求項1所述之電子封裝件，復包括設於該包覆層之第一表面與該佈線層上之絕緣保護層，且該絕緣保護層係具有複數開孔，以令該佈線層之部分表面外露於該複數開孔。
  8. 一種電子封裝件之製法，係包括：於一承載板之部分表面上形成一佈線層；於該佈線層上形成複數導電柱，且設置電子元件於該佈線層上；形成單一包覆層於該承載板上，以令該包覆層包覆該佈線層、該電子元件與該複數導電柱，其中，該包覆層係具有相對之第一表面與第二表面，使該包覆層以其第一表面結合該承載板，且該佈線層之外表面齊平該包覆層之第一表面；形成一線路結構於該包覆層之第二表面上，以令該線路結構電性連接該複數導電柱與該電子元件；以及移除該承載板，以外露該包覆層之第一表面及該佈線層。
  9. 如請求項8所述之電子封裝件之製法，其中，該電子元件係具有相對之作用面與非作用面，該電子元件係以其非作用面藉由該黏著層黏固於該佈線層上，且該作用面具有複數電極墊，以令該線路結構電性連接該複數電極墊。
  10. 如請求項9所述之電子封裝件之製法，其中，該複數電極墊上係結合複數導電體，以令該複數電極墊藉由該複數導電體電性連接該線路結構。
  11. 如請求項10所述之電子封裝件之製法，其中，該複數導電體之端面係齊平該包覆層之第二表面。
  12. 如請求項8所述之電子封裝件之製法，其中，該複數導電柱之端面係齊平該包覆層之第二表面。
  13. 如請求項8所述之電子封裝件之製法，復包括形成複數導電元件於該線路結構上，以令該複數導電元件電性連接該線路結構。
  14. 如請求項8所述之電子封裝件之製法，復包括於該包覆層之第一表面與該佈線層上形成絕緣保護層，且該絕緣保護層係具有複數開孔，以令該佈線層之部分表面外露於該複數開孔。
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Publication number Priority date Publication date Assignee Title
TW201926605A (zh) * 2017-11-22 2019-07-01 矽品精密工業股份有限公司 電子封裝件及其製法
TW202220139A (zh) * 2020-11-12 2022-05-16 矽品精密工業股份有限公司 電子封裝件及其線路結構

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201926605A (zh) * 2017-11-22 2019-07-01 矽品精密工業股份有限公司 電子封裝件及其製法
TW202220139A (zh) * 2020-11-12 2022-05-16 矽品精密工業股份有限公司 電子封裝件及其線路結構

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