TW202042368A - Carrying substrate, electronic package having the carrying substrate, and methods for manufacturing the same - Google Patents

Abstract

This invention relates to an automatic labeling method for detecting moving objects, which is suitable for obtaining the object information in the multimedia image file to mark the range and position, and then storing the image, the object feature conversion string and the object tag coordinate in the feature object database in order to manage and use a huge amount of feature object data.

Description

Electronic package and its carrying substrate and manufacturing method

The invention relates to a packaging structure, in particular to an electronic packaging component and its supporting substrate and manufacturing method.

With the increase in the function and processing speed of electronic products, semiconductor chips, which are the core components of electronic products, need to have higher-density circuit components (Electronic Components) and electronic circuits (Electronic Circuits), so semiconductor chips will A large amount of heat energy is generated accordingly. In addition, the encapsulant system covering the semiconductor chip is a poor heat transfer material with a thermal conductivity of only 0.8Wm-1k-1 (that is, the heat dissipation efficiency is not good), so if it cannot effectively escape The heat generated by the dissipation will cause damage to the semiconductor chip or cause product reliability problems.

In order to quickly dissipate the heat energy into the atmosphere, the industry usually configures a heat sink (Heat Sink or Heat Spreader) in the semiconductor package structure. The heat sink is combined with a heat sink, such as a thermal interface material (TIM). To the back of the semiconductor chip to dissipate the heat generated by the semiconductor chip through the heat sink and heat sink, and then Furthermore, it is usually better to expose the encapsulant on the top surface of the heat sink or directly expose it to the atmosphere in order to obtain a better heat dissipation effect.

As shown in Figure 1, the conventional method for manufacturing a semiconductor package 1 is to first place a semiconductor chip 11 with its active surface 11a on a package substrate 10 by flip chip bonding (ie through conductive bumps 110 and primer 111). Then, a heat sink 13 is reflow-bonded to the non-acting surface 11b of the semiconductor chip 11 with its top sheet 130 through the TIM layer 12 (which includes a solder layer and flux), and the supporting legs of the heat sink 13 131 is mounted on the packaging substrate 10 via the adhesive layer 14. Then, a packaging press molding operation is performed to provide a packaging compound (not shown in the figure) to cover the semiconductor chip 11 and the heat sink 13, and to expose the packaging compound to the top plate 130 of the heat sink 13 to directly contact the atmosphere. After that, the semiconductor package 1 and its package substrate 10 are connected to a circuit board 8 through a plurality of solder balls 15.

During operation, the heat generated by the semiconductor chip 11 is conducted to the top sheet 130 of the heat sink 13 via the inactive surface 11b and the TIM layer 12 to dissipate heat to the outside of the semiconductor package 1.

However, with the development of industrial applications, in recent years, R&D has been gradually moving towards the trend of large-size packaging specifications for applications in high-end products with high-density circuits/high transmission speed/high stack count/large-size designs.

However, in the conventional semiconductor package 1, the requirement for a large-scale package substrate 10, such as the requirement of a board size of 100*100mm ² , is not yet mass-produced, and the production cost of a single board is extremely high. Not competitive in the market.

Therefore, how to overcome the above-mentioned problems of the conventional technology has actually become a problem that the industry urgently needs to overcome.

In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides a carrier substrate, which includes: a first circuit structure having opposite first and second sides; at least one circuit member arranged on the first circuit structure And a coating layer formed on the first side of the first circuit structure to cover the circuit member.

The present invention also provides a method for manufacturing a carrier substrate, which includes: providing a first circuit structure having opposite first and second sides; arranging at least one circuit member on the first side of the first circuit structure; and forming The coating layer is on the first side of the first circuit structure so that the coating layer covers the circuit component.

In the aforementioned carrier substrate and its manufacturing method, it further includes forming a second circuit structure on the coating layer, and electrically connecting the second circuit structure to the circuit member. For example, the circuit member is electrically connected to the second circuit structure through a plurality of conductors. The method further includes forming a conductive pillar on the first side of the first circuit structure, so that the coating layer covers the conductive pillar, and the conductive pillar is electrically connected to the first circuit structure and the second circuit structure. Alternatively, it may include forming a plurality of conductive bumps on the second circuit structure.

In the aforementioned carrier substrate and its manufacturing method, the coating layer covers at least four of the circuit components.

In the aforementioned carrier substrate and its manufacturing method, the circuit member is a package substrate.

In the aforementioned carrier substrate and its manufacturing method, the circuit component is a circuit structure without a core layer.

In the aforementioned carrier substrate and its manufacturing method, the circuit member has a silicon via structure.

In the aforementioned carrier substrate and its manufacturing method, the circuit member is electrically connected to the first circuit structure through a plurality of conductors.

Another electronic package of the present invention includes: a carrier substrate as described above; and at least one electronic component disposed on one of the first side and the second side of the carrier substrate.

The present invention further provides a method for manufacturing an electronic package, which includes: providing a carrier substrate as described above; and arranging at least one electronic component on one of the first side and the second side of the carrier substrate.

In the aforementioned electronic package and its manufacturing method, the electronic component is an active component, a passive component or a combination of both.

The aforementioned electronic package and its manufacturing method further include forming a plurality of conductive elements on the first side and the second side of the carrier substrate where the electronic element is not provided.

In the aforementioned electronic package and its manufacturing method, it further includes disposing a heat sink on the carrier substrate. For example, the heat sink is in contact with the electronic component.

It can be seen from the above that in the electronic package and its carrier substrate and manufacturing method of the present invention, the circuit components are mainly arranged on the first circuit structure and embedded in the cladding layer to increase the wiring area. According to the known technology, the present invention is not only mass-productive, but also extremely competitive in the market due to the requirement for packaging substrates with large-size boards.

Furthermore, the circuit structure is used to adjust the number of wiring layers of the circuit member, so that the number of wiring layers of the circuit member is reduced, so as to improve the production yield of the circuit member.

1‧‧‧Semiconductor package

10‧‧‧Packaging substrate

11‧‧‧Semiconductor chip

11a,30a‧‧‧working surface

11b,30b‧‧‧Non-acting surface

110,29‧‧‧Conductive bump

111,33‧‧‧ Primer

12‧‧‧TIM layer

13,3a‧‧‧Radiator

130‧‧‧Top Film

131,31‧‧‧Support foot

14,91,310‧‧‧Adhesive layer

15‧‧‧Solder ball

2,2’,2”,3a‧‧‧Carrier substrate

2a‧‧‧Circuit board

20‧‧‧The first line structure

20a‧‧‧First side

20b‧‧‧Second side

200‧‧‧First insulation layer

201,201’‧‧‧Relay layer of the first line

21‧‧‧Line components

21a‧‧‧Top surface

21b‧‧‧Bottom

210‧‧‧Line layer

211‧‧‧Insulator

212‧‧‧Protective Film

213‧‧‧Electrical contact pad

22,22’‧‧‧Conductor

22a,23a‧‧‧end face

23‧‧‧Conductive post

24‧‧‧Combination layer

25‧‧‧Coating

26‧‧‧Second line structure

260‧‧‧Second insulating layer

261‧‧‧Second line re-layout

27‧‧‧Conductive element

28‧‧‧Insulation protection layer

290‧‧‧Metal layer under bump

3,3’‧‧‧Electronic package

30‧‧‧Electronic components

300‧‧‧electrode pad

32‧‧‧Radiator

320‧‧‧ Thermal Interface Layer

4‧‧‧Electronic device

8‧‧‧Circuit board

9‧‧‧Carrier plate

90‧‧‧Release layer

S‧‧‧cutting path

Figure 1 is a schematic cross-sectional view of a conventional semiconductor package.

2A to 2E are schematic cross-sectional views of the first embodiment of the manufacturing method of the carrier substrate of the present invention.

2F to 2G are schematic cross-sectional views of the first embodiment of the manufacturing method of the electronic package of the present invention.

Fig. 2G' is a schematic cross-sectional view of another aspect of Fig. 2G.

Figure 2G" is a schematic cross-sectional view of another aspect of Figure 2E.

3A to 3B are schematic cross-sectional views of the second embodiment of the manufacturing method of the carrier substrate of the present invention.

3C to 3D are schematic cross-sectional views of the second embodiment of the manufacturing method of the electronic package of the present invention.

The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this manual are only used to match the contents disclosed in the manual for the understanding and reading of those familiar with the art, and are not intended to limit the implementation of the present invention Therefore, it does not have any technical significance. Any structural modification, proportional relationship change, or size adjustment should still fall within the scope of the present invention without affecting the effects and objectives that can be achieved. The technical content disclosed by the invention can be covered. At the same time, the terms such as "on", "first", "second" and "one" cited in this manual are only for ease of description, not to limit the scope of the present invention. The scope of implementation, and the change or adjustment of the relative relationship, shall be regarded as the scope of the present invention which can be implemented without substantially changing the technical content.

2A to 2E are schematic cross-sectional views of the first embodiment of the manufacturing method of the carrier substrate 2 of the present invention.

As shown in FIG. 2A, a circuit board 2a is provided, which includes a plurality of circuit members 21.

In this embodiment, the circuit member 21 is a package substrate with a core layer and a circuit structure or a circuit structure without a core layer (coreless in the figure), which has an insulator 211 and a combination The plurality of circuit layers 210 of the insulator 211, such as a fan out (fan out) redistribution layer (RDL), and the material forming the insulator 211 is, for example, polybenzoxazole (PBO) , Polyimide (PI for short), Prepreg (PP for short) or other dielectric materials; alternatively, the circuit member 21 may have a Through Silicon Via (TSV for short) structure. It should be understood that the circuit member 21 can also be other boards configured with wiring, such as organic material, silicon, ceramic, or other carrier boards with metal routing. It is not limited to the above.

Furthermore, a plurality of conductors 22 are combined and electrically connected to the circuit member 21, and the conductor 22 is a column of metal materials such as a conductive circuit, a solder ball, or a metal material such as a copper column, a solder bump, etc. Shape, or stud made by wire bonding machine, but not limited to this. In addition, the top surface 21a of the circuit member 21 can be formed with a protective film 212 such as a passivation material, so that a part of the circuit layer 210 (such as a plurality of electrical contact pads 213) is exposed to the protective film 212, and the conductor 22 is formed on The protective film 212 protrudes on the electrical contact pad 213.

As shown in Figure 2B, the circuit block 2a is cut to obtain a plurality of circuit members 21, and then one or more (more than four as shown in the figure) circuit members 21 are arranged on a first circuit structure 20, wherein, The first circuit structure 20 is formed on the supporting board 9 and has a first side 20a and a second side 20b opposite to each other. The first circuit structure 20 is connected to the supporting board 9 with its second side 20b, and the circuit The member 21 is arranged on the first side 20 a of the first circuit structure 20. On the other hand, a plurality of conductive pillars 23 electrically connected to the first circuit structure 20 are also formed on the first side 20a of the first circuit structure 20, wherein the arrangement order of the circuit member 21 and the conductive pillar 23 can be The order of demand selection.

In this embodiment, the first circuit structure 20 includes at least a first insulating layer 200 and a first redistributed circuit layer (RDL) 201 disposed on the first insulating layer 200. For example, the material for forming the first circuit redistribution layer 201 is copper, and the material for forming the first insulating layer 200 is such as polypara-diazole benzene (PBO), polyimide (PI), and prepreg. (PP) or other dielectric materials.

Furthermore, the carrier board 9 is, for example, a circular board made of semiconductor material (such as silicon or glass), on which a release layer 90 and an adhesive layer 91 are sequentially formed by coating for the first circuit The structure 20 is provided on the adhesive layer 91.

In addition, the conductive pillar 23 is disposed on the first circuit redistribution layer 201 and electrically connected to the first circuit redistribution layer 201, and the material for forming the conductive pillar 23 is a metal material such as copper or a solder material.

In addition, the circuit member 21 is fixed on the first side 20a of the first circuit structure 20 with its bottom surface 21b through a bonding layer 24 such as glue.

As shown in FIG. 2C, a coating layer 25 is formed on the first side 20a of the first circuit structure 20, so that the coating layer 25 covers the circuit member 21, the bonding layer 24, and the plurality of conductors 22 And the plurality of conductive pillars 23, and then through the leveling process, the end surface 23a of the conductive pillar 23 and the The end surface 22 a of the conductor 22 is exposed to the coating layer 25, so that the outer surface of the coating layer 25 is flush with the end surface 23 a of the conductive pillar 23 and the end surface 22 a of the conductor 22.

In this embodiment, the coating layer 25 is an insulating material, such as an epoxy resin encapsulant, which can be formed on the first side of the first circuit structure 20 by lamination or molding. On 20a.

Furthermore, the leveling process is to remove part of the material of the conductive pillar 23, part of the material of the conductor 22, and part of the material of the coating layer 25 by grinding.

As shown in FIG. 2D, a second circuit structure 26 is formed on the cladding layer 25, and the second circuit structure 26 is electrically connected to the conductive pillar 23 and the conductor 22.

In this embodiment, the second circuit structure 26 includes a plurality of second insulating layers 260, and a plurality of second circuit redistribution layers (RDL) 261 disposed on the second insulating layer 260, and the second outermost layer The insulating layer 260 can be used as a solder mask, so that the outermost second circuit redistribution layer 261 is exposed from the solder mask. Alternatively, the second circuit structure 26 can also only include a single second insulating layer 260 and a single second circuit redistribution layer 261.

Furthermore, the material for forming the second circuit redistribution layer 261 is copper, and the material for forming the second insulating layer 260 is, for example, polyparabenzol (PBO) or polyimide (PI for short) , Prepreg (PP) or other dielectric materials.

As shown in FIG. 2E, the carrier board 9 and the release layer 90 and adhesive layer 91 thereon are removed to expose the first circuit structure 20, thereby forming the carrier substrate 2 of the present invention.

Therefore, in the manufacturing method of the carrier substrate 2 of the present invention, the circuit member 21 is embedded in the cladding layer 25 mainly by the existing packaging process to increase the wiring area. Therefore, compared with the conventional technology, it is suitable for large-size boards. The requirements of the packaging substrate of the present invention, the manufacturing method of the carrier substrate 2 of the present invention is not It only has mass production, and the manufacturing cost of a single carrier substrate 2 is extremely low, so it is extremely competitive in the market.

Furthermore, the first circuit structure 20 (or the second circuit structure 26) is used to adjust the number of wiring layers of the circuit member 21 to reduce the number of wiring layers of the circuit member 21 to improve the production of the circuit member 21 Yield rate.

As shown in Figure 2F, the carrier substrate 2 can be connected to the outermost second circuit redistribution layer 261 with one or more electronic components 30 to form an electronic package 3, and the carrier substrate 2 can be placed on the first A plurality of conductive elements 27 such as solder balls are formed on the second side 20b of the circuit structure 20.

In this embodiment, an insulating protective layer 28 such as a solder mask can be formed on the second side 20b of the first circuit structure 20, and a plurality of openings can be formed on the insulating protective layer 28 to make the first The circuit redistribution layer 201 is exposed to the plurality of openings for bonding the plurality of conductive elements 27.

Furthermore, the electronic component 30 is an active component, a passive component, or a combination of the two, etc., wherein the active component is a semiconductor chip, and the passive component is a resistor, a capacitor, and an inductor. For example, the electronic component 30 is a semiconductor chip, which has an opposite active surface 30a and a non-active surface 30b, and the electrode pad 300 of its active surface 30a is arranged in a flip-chip manner by a plurality of conductive bumps 29 such as solder material. The second circuit redistribution layer 261 is electrically connected to the second circuit redistribution layer 261, and the conductive bump 29 is covered with a primer 33; or, the electronic component 30 is disposed on the non-active surface 30b On the second circuit structure 26, the second circuit redistribution layer 261 can be electrically connected by multiple bonding wires (the figure omitted); or through conductive materials such as conductive glue or solder (the figure omitted) The second line redistribution layer 261 is electrically connected. However, the manner in which the electronic component 30 is electrically connected to the second circuit redistribution layer 261 is not limited to the above.

In addition, an under bump metallurgy (UBM) 290 can be formed on the outermost second circuit redistribution layer 261 to facilitate the bonding of the conductive bump 29.

As shown in Fig. 2G, a singulation process is performed along the cutting path S shown in Fig. 2F, so that the carrier substrate 2 is connected to a package structure or a circuit board by the conductive element 27 in the subsequent process.的电子装置4上。 The electronic device 4 on.

In this embodiment, the electronic package 3 can be configured with a heat sink 3a according to requirements, which includes a supporting leg 31 and a heat sink 32, and the supporting leg 31 is bonded to the second circuit structure 26 through an adhesive layer 310 And the heat sink 32 of the heat sink 3a is combined with the electronic component 30 through the thermal interface layer 320. For example, a plurality of supporting legs 31 are integrally formed on the heat sink 32; or, a plurality of supporting legs 31 may also be provided on the heat sink 32 in a joint manner.

Furthermore, the thermally conductive interface layer 320 can also be formed on the heat sink 32 first, and then the radiator 32 is bonded to the non-active surface 30b of the electronic component 30 by the thermally conductive interface layer 320. Similarly, the adhesive layer 310 can also be formed on the supporting leg 31 first, and then the supporting leg 31 is bonded to the second circuit structure 26 through the adhesive layer 310.

In addition, in order to improve the bonding strength between the thermally conductive interface layer 320 and the electronic component 30, the surface of the electronic component 30 may be coated with gold (the so-called Coating Gold On Chip Back). Specifically, a gold layer is formed on the non-acting surface 30b of the electronic component 30 and the surface of the heat sink 32, and a flux is further added to facilitate the thermal interface layer 320 to adhere to the gold layer.

In addition, in other embodiments, the carrier substrate 2'can omit the production of the conductive pillar 23, as shown in Figure 2G'. Or, as shown in the carrier substrate 2" shown in Figure 2G", the circuit member 21 is combined on opposite sides and electrically connected to a plurality of conductors 22, 22', and one of the two The conductor 22 is electrically connected to the second circuit structure 26, and the conductor 22' on the other side is electrically connected to the first circuit redistribution layer 201' of the first circuit structure 20.

3A to 3B are schematic cross-sectional views of the second embodiment of the manufacturing method of the carrier substrate 3a of the present invention. The difference between this embodiment and the first embodiment is that the manufacturing process of the second circuit structure is omitted, and the other manufacturing processes are substantially the same, so the same points will not be repeated below.

As shown in Figure 3A, the circuit member 21 shown in Figure 2G" is used to perform the manufacturing process shown in Figures 2A to 2C, including: providing a plurality of circuit members 21, each of which is combined on opposite sides The plurality of conductors 22, 22' are electrically connected, the plurality of circuit members 21 and the plurality of conductive pillars 23 are electrically connected to the first circuit structure 20 on the carrier board 9, and then the coating layer 25 is formed and the leveling process is performed.

As shown in FIG. 3B, the carrier board 9 and the release layer 90 and adhesive layer 91 thereon are removed to expose the second side 20b of the first circuit structure 20, thereby forming the carrier substrate 3a of the present invention.

Therefore, in the manufacturing method of the carrier substrate 3a of the present invention, the circuit member 21 is embedded in the cladding layer 25 mainly by the existing packaging process to increase the wiring area. Therefore, compared with the conventional technology, it is suitable for large-size boards. The manufacturing method of the carrier substrate 3a of the present invention is not only mass-productive, but also the manufacturing cost of a single carrier substrate 3a is extremely low, so it is extremely competitive in the market.

Furthermore, the first circuit structure 20 is used to adjust the number of wiring layers of the circuit member 21 to reduce the number of wiring layers of the circuit member 21 so as to improve the manufacturing yield of the circuit member 21.

As shown in Figure 3C, the carrier substrate 3a can be connected to the first circuit redistribution layer 201 of the second side 20b of the first circuit structure 20 with one or more electronic components 30, and the carrier substrate 3a can be mounted on the On the circuit member 21, a plurality of conductive elements such as solder balls are combined by the conductors 22 A member 27, so that the carrier substrate 3a is connected to the electronic device 4 as shown in FIG. 2G by the conductive elements 27 in the subsequent manufacturing process.

As shown in Fig. 3D, the singulation process is performed along the cutting path S shown in Fig. 3C to obtain the electronic package 3'.

The present invention also provides an electronic package 3, 3', which includes a carrier substrate 2, 2', 2", 3a and at least one electronic device arranged on one side of the carrier substrate 2, 2', 2", 3a The component 30, wherein the carrier substrate 2, 2', 2", 3a includes: a first circuit structure 20, a circuit member 21 and a coating layer 25.

The first circuit structure 20 has a first side 20a and a second side 20b opposite to each other. A plurality of conductive pillars 23 can be formed on the first side 20a as required, and the conductive pillars 23 are electrically connected to the first circuit Structure 20.

The circuit member 21 is arranged on the first side 20a of the first circuit structure 20, and the circuit member 21 is combined and electrically connected to a plurality of conductive bodies 22, 22'.

The coating layer 25 is formed on the first side 20a of the first circuit structure 20, so that the coating layer 25 covers the circuit member 21, the conductors 22, 22' and the conductive pillar 23, And the end surface 23a of the conductive pillar 23 and the end surface 22a of the conductor 22 are exposed to the coating layer 25.

In one embodiment, the circuit member 21 is electrically connected to the first circuit structure 20 through a plurality of conductors 22'.

In an embodiment, the electronic package 3, 3'includes a plurality of conductive elements 27 formed on the other side of the carrier substrate 2, 2', 2", 3a.

In one embodiment, the carrier substrate 2, 2', 2" includes a second circuit structure 26 formed on the coating layer 25, and the second circuit structure 26 is electrically connected to the conductive pillar 23 , And electrically connected to the circuit member 21 by the conductor 22. It also includes a plurality of conductive bumps 29 formed on the second circuit structure 26.

In one embodiment, the electronic component 30 is an active component, a passive component or a combination of both.

In one embodiment, the electronic package 3 further includes a heat sink 3 a disposed on the second circuit structure 26. For example, the heat sink 3a is in contact with the electronic component 30.

To sum up, in the electronic package and its carrier substrate and manufacturing method of the present invention, the circuit component is arranged on the first circuit structure and embedded in the cladding layer by the existing packaging process to increase the wiring area. In response to the demand for packaging substrates with large dimensions, the carrier substrate of the present invention not only has mass productivity, but also has extremely low manufacturing costs for a single carrier substrate, which makes it extremely competitive in the market.

Furthermore, the circuit structure can be used to adjust the number of wiring layers of the circuit component, so that the number of wiring layers of the circuit component is reduced, thereby improving the production yield of the circuit component.

The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone who is familiar with the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

2‧‧‧Carrier substrate

20‧‧‧The first line structure

20a‧‧‧First side

20b‧‧‧Second side

21‧‧‧Line components

22‧‧‧Conductor

23‧‧‧Conductive post

25‧‧‧Coating

26‧‧‧Second line structure

Claims (30)

A carrier substrate includes: a first circuit structure having opposite first and second sides; at least one circuit member arranged on the first side of the first circuit structure; and a coating layer, Is formed on the first side of the first circuit structure to cover the circuit member. The carrier substrate described in item 1 of the scope of the patent application further includes a second circuit structure formed on the coating layer and electrically connected to the circuit member. According to the carrier substrate described in item 2 of the scope of the patent application, the circuit member is electrically connected to the second circuit structure through a plurality of conductors. The carrier substrate described in item 2 of the scope of the patent application includes conductive pillars formed in the coating layer to electrically connect the first circuit structure and the second circuit structure. The carrier substrate described in item 2 of the scope of the patent application includes a plurality of conductive bumps formed on the second circuit structure. According to the carrier substrate described in claim 1, wherein the coating layer covers at least four of the circuit members. According to the carrier substrate described in item 1 of the scope of patent application, the circuit member is a package substrate. According to the carrier substrate described in item 1 of the scope of patent application, the circuit member is a circuit structure without a core layer. According to the carrier substrate described in item 1 of the scope of patent application, the circuit member has a silicon through hole structure. According to the carrier substrate described in claim 1, wherein the circuit member is electrically connected to the first circuit structure through a plurality of conductors. An electronic package including: A carrier substrate as described in one of items 1 to 10 in the scope of the patent application; and at least one electronic component is disposed on one of the first side and the second side of the carrier substrate. The electronic package described in item 11 of the scope of patent application, wherein the electronic component is an active component, a passive component or a combination of both. For example, the electronic package described in item 11 of the scope of patent application includes a plurality of conductive elements, which are arranged on the first side and the second side of the carrier substrate on which the electronic element is not provided. The electronic package described in item 11 of the scope of the patent application includes a heat sink arranged on the carrier substrate. The electronic package described in item 14 of the scope of patent application, wherein the heat sink is in contact with the electronic component. A method for manufacturing a carrier substrate includes: providing a first circuit structure having opposite first and second sides; arranging at least one circuit member on the first side of the first circuit structure; and forming a coating layer on the On the first side of the first circuit structure, the coating layer covers the circuit member. The manufacturing method of the carrier substrate as described in item 16 of the scope of patent application includes forming a second circuit structure on the coating layer, and electrically connecting the second circuit structure to the circuit member. According to the manufacturing method of the carrier substrate described in claim 17, wherein the circuit member is electrically connected to the second circuit structure through a plurality of conductors. For example, the manufacturing method of the carrier substrate described in the scope of the patent application includes forming a conductive pillar on the first side of the first circuit structure, and making the coating layer cover the conductive pillar to pass electricity through the conductive pillar. The first circuit structure and the second circuit structure are sexually connected. The manufacturing method of the carrier substrate as described in item 17 of the scope of patent application includes forming a plurality of conductive bumps on the second circuit structure. According to the manufacturing method of the carrier substrate described in item 16 of the scope of patent application, the coating layer covers at least four of the circuit members. According to the manufacturing method of the carrier substrate described in item 16 of the scope of patent application, the circuit member is a package substrate. The manufacturing method of the carrier substrate as described in item 16 of the scope of patent application, wherein the circuit member is a circuit structure without a core layer. According to the manufacturing method of the carrier substrate described in item 16 of the scope of patent application, the circuit member has a silicon through hole structure. According to the manufacturing method of the carrier substrate described in claim 16, wherein the circuit member is electrically connected to the first circuit structure through a plurality of conductors. A method for manufacturing an electronic package includes: providing a carrier substrate as described in one of items 1 to 10 of the scope of the patent application; and disposing at least one electronic component on the first side and the second side of the carrier substrate One of them. The method for manufacturing an electronic package as described in item 26 of the scope of patent application, wherein the electronic component is an active component, a passive component or a combination of both. The manufacturing method of the electronic package described in item 26 of the scope of the patent application includes forming a plurality of conductive elements on the first side and the second side of the carrier substrate where the electronic element is not provided. The manufacturing method of the electronic package as described in item 26 of the scope of patent application includes disposing a heat sink on the carrier substrate. The method for manufacturing an electronic package described in item 29 of the scope of patent application, wherein the heat sink is in contact with the electronic component.

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