TWI802726B - Carrying substrate, electronic package having the carrying substrate, and methods for manufacturing the same - Google Patents

Abstract

A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

Description

Electronic package, carrier substrate and manufacturing method thereof

The invention relates to a packaging structure, especially to an electronic package, its carrying substrate and its manufacturing method.

With the improvement of the function and processing speed of electronic products, semiconductor chips, which are the core components of electronic products, need to have higher density circuit components (Electronic Components) and electronic circuits (Electronic Circuits), so semiconductor chips will A large amount of heat energy is generated accordingly. In addition, the encapsulant system covering the semiconductor chip is a poor heat transfer material with a thermal conductivity of only 0.8Wm-1k-1 (that is, the heat dissipation efficiency is not good), so if it cannot be effectively released The heat generated by dissipating will cause damage to the semiconductor chip or cause product reliability problems.

In order to quickly dissipate heat energy into the atmosphere, the industry usually configures a heat sink (Heat Sink or Heat Spreader) in the semiconductor package structure. To the back of the semiconductor chip to dissipate the heat generated by the semiconductor chip through the heat dissipation glue and the heat sink, and then Or, it is usually better to expose the top surface of the heat sink to the encapsulant or directly to the atmosphere, so as to obtain a better heat dissipation effect.

As shown in FIG. 1 , the conventional manufacturing method of semiconductor package 1 is to first place a semiconductor chip 11 with its active surface 11 a on a package substrate 10 by means of flip-chip bonding (that is, through conductive bumps 110 and primer 111 ). Then, a heat sink 13 is bonded to the non-active surface 11b of the semiconductor chip 11 by reflowing the TIM layer 12 (which includes a solder layer and flux) with its top sheet 130, and the supporting legs of the heat sink 13 131 is erected on the package substrate 10 through the adhesive layer 14 . Next, the encapsulation molding operation is carried out, so that the encapsulant (not shown) covers the semiconductor chip 11 and the heat sink 13, and the top sheet 130 of the heat sink 13 exposes the encapsulant and directly contacts with the atmosphere. Afterwards, the semiconductor package 1 and its package substrate 10 are connected to a circuit board 8 via a plurality of solder balls 15 .

During operation, the heat energy generated by the semiconductor chip 11 is conducted to the top sheet 130 of the heat sink 13 through the non-active surface 11 b and the TIM layer 12 to dissipate heat to the outside of the semiconductor package 1 .

However, with the development of industrial applications, in recent years, research and development has gradually moved towards the trend of large-size packaging specifications, so as to be applied to high-end products with high-density lines/high transmission speed/high stacking number/large-size design.

However, in the conventional semiconductor package 1, the requirement for a package substrate 10 with a large-sized board, such as a board size of 100*100mm ² , is not yet mass-producible, and the manufacturing cost of a single board is extremely high, so Not competitive in the market.

Therefore, how to overcome the various problems of the above-mentioned conventional technologies has become a difficult problem to be overcome urgently in the industry at present.

In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides a carrier substrate, which includes: a first circuit structure having opposite first and second sides; at least one circuit component is arranged on the first circuit structure on the first side of the first wiring structure; and a covering layer is formed on the first side of the first wiring structure to cover the wiring member.

The present invention also provides a method for manufacturing a carrier substrate, which includes: providing a first wiring structure with opposite first and second sides; disposing at least one wiring member on the first side of the first wiring structure; and forming The cladding layer is on the first side of the first circuit structure, so that the cladding layer covers the circuit component.

In the aforementioned carrying substrate and its manufacturing method, further comprising forming a second circuit structure on the cladding layer, and electrically connecting the second circuit structure to the circuit member. For example, the circuit component is electrically connected to the second circuit structure through a plurality of conductors. It also includes forming a conductive post on the first side of the first circuit structure, so that the cladding layer covers the conductive post, and the conductive post is electrically connected to the first circuit structure and the second circuit structure. Alternatively, it may include forming a plurality of conductive bumps on the second circuit structure.

In the aforementioned carrier substrate and its manufacturing method, the cladding layer covers at least four of the circuit components.

In the aforementioned carrier substrate and its manufacturing method, the circuit component is a packaging substrate.

In the aforementioned carrier substrate and its manufacturing method, the circuit component is a circuit structure without a core layer.

In the aforementioned carrier substrate and its manufacturing method, the circuit component has a TSV structure.

In the aforementioned carrier substrate and its manufacturing method, the circuit component is electrically connected to the first circuit structure through a plurality of conductors.

Another electronic package of the present invention includes: the aforementioned carrier substrate; and at least one electronic component disposed on one of the first side and the second side of the carrier substrate.

The present invention further provides a method for manufacturing an electronic package, which includes: providing the aforementioned carrier substrate; and disposing at least one electronic component on one of the first side and the second side of the carrier substrate.

In the aforementioned electronic package and its manufacturing method, the electronic element is an active element, a passive element or a combination thereof.

In the aforementioned electronic package and its manufacturing method, it further includes forming a plurality of conductive elements on the first side and the second side of the carrier substrate that are not provided with the electronic element.

In the aforementioned electronic package and its manufacturing method, it further includes disposing a heat dissipation element on the carrier substrate. For example, the heat sink is in contact with the electronic component.

It can be seen from the above that in the electronic package and its carrier substrate and manufacturing method of the present invention, the wiring components are mainly arranged on the first wiring structure and embedded in the cladding layer to increase the wiring area, so compared with the conventional According to the known technology, the present invention is not only capable of mass production, but also has a very low manufacturing cost for a single carrier substrate, so it is very competitive in the market.

Furthermore, the circuit structure is used to adjust the number of wiring layers of the circuit component, so as to reduce the number of wiring layers of the circuit component, so as to improve the production yield of the circuit component.

1‧‧‧Semiconductor package

10‧‧‧Package Substrate

11‧‧‧semiconductor chip

11a, 30a‧‧‧Action surface

11b, 30b‧‧‧non-action surface

110,29‧‧‧Conductive bump

111,33‧‧‧Primer

12‧‧‧TIM layer

13,3a‧‧‧Heat sink

130‧‧‧top sheet

131,31: Supporting feet

14,91,310: Adhesive layer

15: solder ball

2, 2’, 2”, 3b: carrier substrate

2a: Circuit board

20: The first line structure

20a: First side

20b: Second side

200: first insulating layer

201,201': the first line redistribution layer

21: Line components

21a: top surface

21b: bottom surface

210: line layer

211: insulator

212: Protective film

213: Electrical contact pad

22,22': Conductor

22a, 23a: end face

23: Conductive column

24: Bonding layer

25: cladding layer

26: Second line structure

260: second insulating layer

261: Second line redistribution layer

27: Conductive element

28: Insulation protective layer

290: metal layer under the bump

3,3': electronic package

30: Electronic components

300: electrode pad

32: radiator

320: thermal interface layer

4: Electronic device

8: Circuit board

9: Loading board

90: release layer

S: cutting path

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package.

2A to 2E are schematic cross-sectional views of the first embodiment of the manufacturing method of the carrier substrate of the present invention.

2F to 2G are schematic cross-sectional views of the first embodiment of the manufacturing method of the electronic package of the present invention.

Fig. 2G' is a schematic cross-sectional view of another aspect of Fig. 2G.

Figure 2G" is a schematic cross-sectional view of another aspect of Figure 2E.

3A to 3B are schematic cross-sectional views of the second embodiment of the manufacturing method of the carrier substrate of the present invention.

Figures 3C to 3D are schematic cross-sectional views of the second embodiment of the manufacturing method of the electronic package of the present invention.

The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for the understanding and reading of those familiar with this technology, and are not used to limit the implementation of the present invention Therefore, it has no technical substantive meaning. Any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of this invention without affecting the effect and purpose of the present invention. The technical content disclosed by the invention must be within the scope covered. At the same time, terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the present invention. The scope of implementation and the change or adjustment of its relative relationship shall also be regarded as the scope of implementation of the present invention without substantive changes in the technical content.

2A to 2E are schematic cross-sectional views of the first embodiment of the manufacturing method of the carrier substrate 2 of the present invention.

As shown in FIG. 2A , a circuit board 2a is provided, which includes a plurality of circuit components 21 .

In this embodiment, the circuit member 21 is a package substrate (substrate) with a core layer and a circuit structure or a circuit structure without a core layer (coreless) (the figure shows a coreless type), which has an insulator 211 and a bonding The plurality of circuit layers 210 of the insulator 211 are, for example, fan-out (redistribution layer, RDL for short), and the material forming the insulator 211 is, for example, polybenzoxazole (PBO for short). , Polyimide (PI for short), Prepreg (PP for short), or other dielectric materials; or, the circuit component 21 may have a through silicon via (TSV for short) structure. It should be understood that the circuit member 21 can also be other boards with wiring, such as organic material, semiconductor board (silicon), ceramic board (ceramic) or other carrier boards with metal wiring (routing), It is not limited to the above.

Furthermore, the circuit member 21 is combined and electrically connected with a plurality of conductors 22, and the conductors 22 are balls such as conductive lines, solder balls, or pillars of metal materials such as copper pillars and solder bumps. shape, or a stud made by a wire bonding machine, but not limited thereto. In addition, a protective film 212 such as a passivation material may be formed on the top surface 21a of the circuit member 21, so that part of the circuit layer 210 (such as a plurality of electrical contact pads 213) is exposed to the protective film 212, and the conductor 22 is formed on The electrical contact pad 213 protrudes from the protection film 212 .

As shown in Figure 2B, the circuit board 2a is cut to obtain a plurality of circuit components 21, and then one or a plurality (more than four as shown) circuit components 21 are arranged on a first circuit structure 20, wherein, The first circuit structure 20 is formed on the carrier board 9 and has opposite first side 20a and second side 20b, the first circuit structure 20 is bonded to the carrier board 9 with its second side 20b, and the circuit The component 21 is disposed on the first side 20a of the first wiring structure 20 . On the other hand, a plurality of conductive pillars 23 electrically connected to the first wiring structure 20 are also formed on the first side 20a of the first wiring structure 20, wherein the arrangement sequence of the wiring member 21 and the conductive pillars 23 can be determined according to Requirements are selected in order of precedence.

In this embodiment, the first circuit structure 20 includes at least one first insulating layer 200 and a first redistribution layer (RDL) 201 disposed on the first insulating layer 200 . For example, the material forming the first redistribution layer 201 is copper, and the material forming the first insulating layer 200 is such as polyparabenazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

Moreover, the carrier plate 9 is, for example, a circular plate made of semiconductor material (such as silicon or glass), on which a release layer 90 and an adhesive layer 91 are sequentially formed by coating for the first circuit. The structure 20 is disposed on the adhesive layer 91 .

Moreover, the conductive column 23 is disposed on the first circuit redistribution layer 201 and electrically connected to the first circuit redistribution layer 201 , and the material forming the conductive column 23 is a metal material such as copper or a solder material.

In addition, the wiring member 21 is fixed on the first side 20a of the first wiring structure 20 with its bottom surface 21b via a bonding layer 24 such as an adhesive material.

As shown in FIG. 2C, a cladding layer 25 is formed on the first side 20a of the first wiring structure 20, so that the cladding layer 25 covers the wiring member 21, the bonding layer 24, and the plurality of conductors 22. and the plurality of conductive pillars 23, and then through the leveling process, the end surface 23a of the conductive pillar 23 is aligned with the The end surface 22 a of the conductor 22 is exposed on the coating layer 25 , so that the outer surface of the coating layer 25 is flush with the end surface 23 a of the conductive column 23 and the end surface 22 a of the conductor 22 .

In this embodiment, the cladding layer 25 is an insulating material, such as epoxy resin encapsulant, which can be formed on the first side of the first circuit structure 20 by lamination or molding. 20a on.

Moreover, the flattening process removes part of the material of the conductive pillar 23 , part of the material of the conductor 22 and part of the material of the cladding layer 25 by grinding.

As shown in FIG. 2D , a second circuit structure 26 is formed on the cladding layer 25 , and the second circuit structure 26 is electrically connected to the conductive column 23 and the conductor 22 .

In this embodiment, the second circuit structure 26 includes a plurality of second insulating layers 260 and a plurality of second redistribution layers (RDL) 261 disposed on the second insulating layers 260, and the second outermost layer The insulating layer 260 can be used as a solder resist layer, so that the outermost second redistribution layer 261 is exposed on the solder resist layer. Alternatively, the second circuit structure 26 may only include a single second insulating layer 260 and a single second circuit redistribution layer 261 .

Moreover, the material forming the second redistribution layer 261 is copper, and the material forming the second insulating layer 260 is such as polyparabenazole (PBO), polyimide (Polyimide, PI for short). , Prepreg (PP for short) or other dielectric materials.

As shown in FIG. 2E , the carrier board 9 and the release layer 90 and the adhesive layer 91 on it are removed to expose the first circuit structure 20 , thereby forming the carrier substrate 2 of the present invention.

Therefore, in the manufacturing method of the carrier substrate 2 of the present invention, the circuit member 21 is embedded in the cladding layer 25 mainly through the existing packaging process to increase the wiring area. In order to meet the needs of the packaging substrate on the surface, the method of making the carrier substrate 2 of the present invention is not It is only mass-producible, and the manufacturing cost of a single carrier substrate 2 is extremely low, so it is highly competitive in the market.

Furthermore, the first circuit structure 20 (or the second circuit structure 26) is used to adjust the number of wiring layers of the circuit component 21, so that the number of wiring layers of the circuit component 21 is reduced to improve the production of the circuit component 21. yield.

As shown in Figure 2F, the carrier substrate 2 can be connected with one or a plurality of electronic components 30 on the outermost second circuit redistribution layer 261 to form an electronic package 3, and the carrier substrate 2 can be placed on the first A plurality of conductive elements 27 such as solder balls are formed on the second side 20b of the wiring structure 20 .

In this embodiment, an insulating protective layer 28 such as a solder mask can be formed on the second side 20b of the first circuit structure 20, and a plurality of openings are formed on the insulating protective layer 28, so that the first The circuit redistribution layer 201 is exposed to the plurality of openings for combining the plurality of conductive elements 27 .

Furthermore, the electronic component 30 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 30 is a semiconductor chip, which has an opposite active surface 30a and a non-active surface 30b, and the electrode pad 300 on the active surface 30a is provided in a flip-chip manner by a plurality of conductive bumps 29 such as solder materials. On the second circuit redistribution layer 261 and electrically connected to the second circuit redistribution layer 261, and the conductive bump 29 is covered with primer 33; or, the electronic component 30 is disposed on the non-active surface 30b The second circuit structure 26 can be electrically connected to the second circuit redistribution layer 261 by a plurality of bonding wires (not shown); or through conductive materials such as conductive glue or solder (not shown). Electrically connected to the second redistribution layer 261 . However, the way the electronic component 30 is electrically connected to the second redistribution layer 261 is not limited to the above.

In addition, an under bump metallurgy (UBM) 290 may be formed on the outermost second redistribution layer 261 to facilitate the bonding of the conductive bump 29 .

As shown in FIG. 2G, the singulation process is performed along the cutting path S shown in FIG. 2F, so that the carrier substrate 2 is connected to a packaging structure or a circuit board through the conductive element 27 in the subsequent manufacturing process. On the electronic device 4.

In this embodiment, the electronic package 3 can be configured with a heat sink 3a as required, which includes a support leg 31 and a heat sink 32, and the support leg 31 is combined with the second circuit structure 26 through an adhesive layer 310 and make the heat sink 32 of the heat sink 3 a combined with the electronic component 30 through the thermal interface layer 320 . For example, the plurality of supporting legs 31 are integrally formed on the heat sink 32 ; or, the plurality of supporting legs 31 can also be arranged on the heat sink 32 in a joint manner.

Moreover, the heat conduction interface layer 320 can also be formed on the heat sink 32 first, and then the heat sink 32 is bonded to the non-active surface 30b of the electronic component 30 by the heat conduction interface layer 320 . Similarly, the adhesive layer 310 can also be formed on the supporting foot 31 first, and then the supporting foot 31 is combined to the second circuit structure 26 through the adhesive layer 310 .

Moreover, in order to enhance the bonding strength between the thermal interface layer 320 and the electronic component 30, the surface of the electronic component 30 can be coated with gold (so-called Coating Gold On Chip Back). Specifically, a gold layer is formed on the non-active surface 30 b of the electronic component 30 and the surface of the heat sink 32 , and flux is further added to facilitate the heat conduction interface layer 320 to adhere to the gold layer.

In addition, in other embodiments, the carrier substrate 2' can omit the fabrication of the conductive pillars 23, as shown in FIG. 2G'. Or, as shown in the 2G "carrier substrate 2", the line member 21 is combined and electrically connected to a plurality of conductors 22, 22' on opposite sides, and one side of the The conductor 22 is electrically connected to the second circuit structure 26, and the conductor 22' on the other side is electrically connected to the first circuit redistribution layer 201' of the first circuit structure 20.

3A to 3B are schematic cross-sectional views of the second embodiment of the manufacturing method of the carrier substrate 3b of the present invention. The difference between this embodiment and the first embodiment is that the manufacturing process of the second circuit structure is omitted, and the other manufacturing processes are substantially the same, so the similarities will not be repeated below.

As shown in Figure 3A, the process shown in Figures 2A to 2C is carried out using the circuit components 21 shown in Figure 2G', including: providing a plurality of circuit components 21, each of which is on opposite sides. Combining and electrically connecting a plurality of conductors 22, 22', electrically connecting a plurality of circuit components 21 and a plurality of conductive columns 23 to the first circuit structure 20 on the carrier board 9, and then forming a cladding layer 25 and performing a leveling process .

As shown in FIG. 3B , the carrier board 9 and the release layer 90 and adhesive layer 91 on it are removed to expose the second side 20b of the first circuit structure 20 , thereby forming the carrier substrate 3b of the present invention.

Therefore, in the manufacturing method of the carrier substrate 3b of the present invention, the circuit member 21 is embedded in the cladding layer 25 mainly through the existing packaging process to increase the wiring area. In order to meet the needs of the packaging substrate, the manufacturing method of the carrier substrate 3b of the present invention is not only mass-producible, but also the manufacturing cost of a single carrier substrate 3b is extremely low, so it is very competitive in the market.

Furthermore, the first circuit structure 20 is used to adjust the number of wiring layers of the circuit component 21 to reduce the number of wiring layers of the circuit component 21 to improve the production yield of the circuit component 21 .

As shown in FIG. 3C, the carrier substrate 3b can be connected with one or a plurality of electronic components 30 on the first circuit redistribution layer 201 of the second side 20b of the first circuit structure 20, and the carrier substrate 3b can be placed on the On the circuit member 21, a plurality of conductive elements such as solder balls are combined by these conductors 22 27, so that the carrier substrate 3b is connected to an electronic device 4 as shown in FIG. 2G through the conductive elements 27 in the subsequent process.

As shown in FIG. 3D, a singulation process is performed along the cutting path S shown in FIG. 3C to obtain an electronic package 3'.

The present invention also provides an electronic package 3, 3', which includes a carrier substrate 2, 2', 2", 3b and at least one electronic package on one side of the carrier substrate 2, 2', 2", 3b. Component 30 , wherein the carrier substrate 2 , 2 ′, 2 ″, 3 b includes: a first circuit structure 20 , a circuit component 21 and a cladding layer 25 .

The first circuit structure 20 has a first side 20a and a second side 20b opposite to each other. A plurality of conductive columns 23 can be formed on the first side 20a as required, and the conductive columns 23 are electrically connected to the first circuit. Structure 20.

The line member 21 is arranged on the first side 20a of the first line structure 20, and the line member 21 is combined and electrically connected with a plurality of conductors 22, 22'.

The cladding layer 25 is formed on the first side 20a of the first wiring structure 20, so that the cladding layer 25 covers the wiring member 21, the conductors 22, 22' and the conductive pillars 23, And the end surface 23 a of the conductive pillar 23 and the end surface 22 a of the conductor 22 are exposed to the cladding layer 25 .

In one embodiment, the circuit member 21 is electrically connected to the first circuit structure 20 through a plurality of conductors 22'.

In one embodiment, the electronic package 3, 3' includes a plurality of conductive elements 27 formed on the other side of the carrier substrate 2, 2', 2", 3b.

In one embodiment, the carrier substrate 2, 2', 2" further includes a second circuit structure 26 formed on the cladding layer 25, and the second circuit structure 26 is electrically connected to the conductive column 23 , and electrically connect the circuit member 21 through the conductor 22. It also includes a plurality of conductive bumps 29 formed on the second circuit structure 26.

In one embodiment, the electronic component 30 is an active component, a passive component or a combination thereof.

In one embodiment, the electronic package 3 further includes a heat sink 3 a disposed on the second circuit structure 26 . For example, the heat sink 3 a is in contact with the electronic component 30 .

To sum up, in the electronic package and its carrier substrate and its manufacturing method of the present invention, the circuit components are arranged on the first circuit structure and embedded in the cladding layer through the existing packaging process to increase the wiring area, so To meet the demand for packaging substrates with large-size boards, the carrier substrate of the present invention not only has the capability of mass production, but also the manufacturing cost of a single carrier substrate is extremely low, so it is very competitive in the market.

Furthermore, the circuit structure can be used to adjust the number of wiring layers of the circuit component, so as to reduce the number of wiring layers of the circuit component, thereby improving the production yield of the circuit component.

The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of the patent application described later.

2: Carrier substrate

20: The first line structure

20a: First side

20b: Second side

21: Line components

22: Conductor

23: Conductive column

25: cladding layer

26: Second line structure

Claims (24)

A carrier substrate includes: a first circuit structure having opposite first and second sides; a circuit component having a plurality of redistribution circuit layers, and the circuit component does not include a semiconductor chip, so that the circuit The component is disposed on the first side of the first circuit structure by a plurality of first conductors, wherein the circuit component further has an opposite lower side and an upper side to respectively form the plurality of first conductors and the plurality of second conductors and a covering layer formed on the first side of the first wiring structure to cover the wiring member, wherein the covering layer is further formed between the first side of the first wiring structure and the wiring member between the lower sides and formed on the upper side of the wiring member, so that the plurality of first conductors directly covered between the first side of the first wiring structure and the lower side of the wiring member by the cladding layer and The plurality of second conductors directly coated on the upper side of the circuit member, wherein the plurality of first conductors directly contact the coating layer between the first side of the first circuit structure and the lower side of the circuit member , and the plurality of second conductors directly contact the cladding layer on the upper side of the circuit member. The carrier substrate as described in item 1 of the scope of the patent application further includes a second wiring structure formed on the cladding layer and electrically connected to the wiring member. The carrier substrate as described in claim 2 of the patent application, wherein the circuit component is electrically connected to the second circuit structure through the plurality of second conductors. The carrier substrate as described in item 2 of the scope of the patent application further includes a conductive post formed in the cladding layer, which is used to electrically connect the first circuit structure and the second circuit structure. The carrier substrate as described in claim 2 of the patent application further includes a plurality of conductive bumps formed on the second circuit structure. The carrier substrate described in item 1 of the scope of the patent application, wherein the circuit component is a package substrate. The carrier substrate as described in item 1 of the scope of the patent application, wherein the wiring component is a wiring structure without a core layer. An electronic package, comprising: a carrier substrate as described in any one of items 1 to 7 of the scope of the patent application; and at least one electronic component disposed on one of the first side and the second side of the carrier substrate one up. The electronic package as described in claim 8 of the patent application, wherein the electronic component is an active component, a passive component or a combination of both. The electronic package as described in item 8 of the scope of the patent application further includes a plurality of conductive elements arranged on the first side and the second side of the carrier substrate which are not provided with the electronic element. The electronic package as described in item 8 of the scope of the patent application further includes a heat dissipation element disposed on the carrier substrate. The electronic package as described in claim 11, wherein the heat sink is in contact with the electronic component. A method for manufacturing a carrier substrate, comprising: providing a first wiring structure with opposite first and second sides; disposing a wiring member on the first side of the first wiring structure through a plurality of first conductors , wherein, the circuit member has a plurality of redistribution circuit layers, the circuit member does not include a semiconductor chip, and the circuit member further has an opposite lower side and an upper side so that the plurality of first conductors and the plurality of second conductors are respectively formed and forming a covering layer on the first side of the first wiring structure to cover the wiring member, wherein the covering layer is further formed between the first side of the first wiring structure and the lower side of the wiring member and formed on the upper side of the wiring member, so as to be directly covered on the first wiring structure by the cladding layer The plurality of first conductors between the first side and the lower side of the circuit member directly cover the plurality of second conductors on the upper side of the circuit member, wherein the plurality of first conductors are directly in contact with the first conductors The covering layer between the first side of the circuit structure and the lower side of the circuit member, and the plurality of second conductors directly contact the covering layer on the upper side of the circuit member. The manufacturing method of the carrier substrate as described in item 13 of the scope of the patent application further includes forming a second circuit structure on the cladding layer, and electrically connecting the second circuit structure to the circuit member. The method for manufacturing a carrier substrate as described in claim 14 of the scope of the patent application, wherein the wiring member is electrically connected to the second wiring structure through the plurality of second conductors. The manufacturing method of the carrier substrate as described in item 14 of the scope of the patent application further includes forming a conductive column on the first side of the first circuit structure, and making the cladding layer cover the conductive column to conduct electricity through the conductive column. Sexually connect the first line structure and the second line structure. The method for manufacturing a carrier substrate as described in item 14 of the scope of the patent application further includes forming a plurality of conductive bumps on the second circuit structure. The method for manufacturing a carrier substrate as described in claim 13, wherein the circuit component is a packaging substrate. The method for manufacturing a carrier substrate as described in claim 13 of the patent application, wherein the wiring component is a wiring structure without a core layer. A method of manufacturing an electronic package, comprising: providing a carrier substrate as described in any one of items 1 to 7 of the scope of the patent application; and arranging at least one electronic component between the first side and the second side of the carrier substrate one of them. The method for manufacturing an electronic package as described in claim 20 of the patent application, wherein the electronic component is an active component, a passive component or a combination of both. The method for manufacturing an electronic package as described in claim 20 further includes forming a plurality of conductive elements on one of the first side and the second side of the carrier substrate that is not provided with the electronic element. The method for manufacturing an electronic package as described in item 20 of the scope of the patent application further includes disposing a heat sink on the carrier substrate. The method for manufacturing an electronic package as described in claim 23, wherein the heat sink is in contact with the electronic component.

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