TW202026713A - Pixel structure - Google Patents

Abstract

A pixel structure includes a channel layer, a gate insulator layer, a first gate, a second gate, a dielectric layer, and a connecting electrode. The channel layer is disposed on a substrate and has a first area, a second area, and a third area. The second area is located between the first and third areas, and the second area has an electrical conductivity greater than those of the first and third areas. The channel layer is covered by the gate insulator layer. The first and second gates are disposed on the gate insulator layer and are respectively located on the first and third areas. The dielectric layer in disposed on the gate insulator layer. The connecting electrode is disposed on the dielectric layer and is electrically connected to the first and second gates. A vertical projection of the connecting electrode onto the channel layer at least partially overlaps the first, second, and third areas.

Description

Pixel structure

This disclosure is about a pixel structure.

Among various electronic products of household appliances, liquid crystal displays using thin film transistors (TFT) have been widely used. The thin film transistor type liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter layer and a liquid crystal layer. The thin film transistor array substrate includes a plurality of thin film transistors arranged in an array, and is connected to each thin film transistor. The pixel electrodes are arranged correspondingly to the crystal to form a pixel structure. In addition, a metal layer is also provided on the thin film transistor array substrate for use as data lines or scan lines.

In the pixel structure, if the opaque layer blocks the light, it will affect the aperture ratio and cause the aperture ratio to decrease. When the aperture ratio decreases, the image display quality of the liquid crystal display may be affected. . Therefore, the layout configuration of the pixel structure of the liquid crystal display has been one of the current research and development topics in related fields.

An embodiment of the present invention provides a pixel structure, including communication Road layer, gate insulating layer, first gate, second gate, dielectric layer and connection electrode. The channel layer is disposed on the substrate and has a first area, a second area, and a third area. The second area is located between the first area and the third area, and the conductivity of the second area is greater than that of the first area and the third area. Three-zone conductivity. The gate insulating layer covers the channel layer. The first gate and the second gate are arranged on the gate insulating layer, and are respectively located on the first area and the third area. The dielectric layer is arranged on the gate insulating layer. The connecting electrode is arranged on the dielectric layer and electrically connected to the first gate and the second gate. The vertical projection of the connecting electrode on the channel layer at least partially overlaps the first, second, and third regions.

In some embodiments, the first zone, the second zone and the third zone are arranged along the same direction.

In some embodiments, the first area and the second area are arranged along the first direction, and the second area and the third area are arranged along the second direction, and the first direction and the second direction are different.

In some embodiments, the pixel structure further includes scan lines. The scan line extends along a direction and is connected to the first gate, wherein the arrangement direction of the first area, the second area and the third area is parallel to this direction.

In some embodiments, the pixel structure further includes scan lines and pixel electrodes. The scan line extends along a direction and connects to the first gate. The pixel electrode is arranged on the dielectric layer and connected to the channel layer to form an interface with the channel layer, wherein the first area, the second area, the third area and the interface are arranged in different directions from this direction, and The vertical projection of the two gates on the channel layer is located between the interface and the vertical projection of the first gate on the channel layer.

In some embodiments, the pixel structure further includes scan lines and Pixel electrode. The scan line extends along one direction and is connected to the second gate. The pixel electrode is arranged on the dielectric layer and connected to the channel layer to form an interface with the channel layer, wherein the first area, the second area, the third area and the interface are arranged in different directions from this direction, and The vertical projection of the two gates on the channel layer is located between the interface and the vertical projection of the first gate on the channel layer.

In some embodiments, the channel layer further has a fourth area and a fifth area, the fourth area is located between the third area and the fifth area, and the conductivity of the fourth area is greater than that of the fifth area. The pixel structure further includes a third gate, wherein the third gate is disposed on the gate insulating layer and located on the fifth region. The connection electrode is further electrically connected to the third gate electrode, and the vertical projection of the connection electrode on the channel layer at least partially overlaps the third area, the fourth area and the fifth area.

In some embodiments, the pixel structure further includes source/drain electrodes and a flat layer. The source/drain electrode is arranged on the dielectric layer and connected to the channel layer, wherein the source/drain electrode and the connection electrode comprise the same material. The flat layer is arranged on the dielectric layer and covers the source/drain electrodes and the connection electrodes.

In some embodiments, the pixel structure further includes a flat layer and pixel electrodes. The flat layer is disposed on the dielectric layer, and the connection electrode is located on the flat layer. The pixel electrode is arranged on the flat layer and connected to the channel layer, wherein the pixel electrode and the connection electrode comprise the same material.

In some embodiments, the pixel structure further includes conductive pads. The conductive pads are arranged on the dielectric layer and are respectively connected to the first gate and the second gate. The connection electrodes are located on the dielectric layer and the conductive pad, and are electrically connected to the first gate and the second gate through the conductive pads. The second gate electrode and the connection electrode include a metal material.

In some embodiments, the connecting electrode includes a connecting portion and a For the electrode pads, the connection part is between the electrode pads, and the width of the connection part is smaller than the width of the electrode pad.

In some embodiments, the vertical projection areas of the first gate and the second gate on the substrate are larger than the vertical projection areas of the first and third regions on the substrate, respectively.

With the above configuration, the first gate and the second gate can form more than one transistor together with the channel layer, and the pixel electrode can be driven by the formed transistor. Since more than one transistor is used to drive the pixel electrodes, leakage current can be suppressed. When the vertical projection of the connecting electrode on the channel layer falls within the boundary of the channel layer, the connecting electrode can electrically connect the first gate to the second gate without affecting the aperture ratio. The arrangement position of the connecting electrode will not be pushed out to the arrangement position and area of the pixel electrode, so that the pixel electrode can have a more flexible arrangement position and area, thereby increasing the aperture ratio of the pixel structure.

100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I‧‧‧Pixel structure

102‧‧‧Substrate

104‧‧‧Pixel area

110A, 110B‧‧‧scan line

112A, 112B‧‧‧Data line

120‧‧‧Passage layer

130‧‧‧Gate insulation layer

132‧‧‧First Gate

134‧‧‧Second Gate

136、152‧‧‧Dielectric layer

138‧‧‧Source/Drain electrode

140‧‧‧Connecting electrode

140A‧‧‧Connecting part

140B, 140C‧‧‧electrode pad

142‧‧‧flat layer

144‧‧‧Pixel electrode

150A, 150B‧‧‧Conductive pad

160‧‧‧third gate

1B-1B’, 8B-8B’‧‧‧ line segment

A1‧‧‧District 1

A2‧‧‧Second District

A3‧‧‧The third area

A4‧‧‧Area 4

A5‧‧‧District 5

A6‧‧‧Sixth district

A7‧‧‧District 7

D1‧‧‧First direction

D2‧‧‧Second direction

I1‧‧‧Interface

P+‧‧‧Heavy doped area

P-‧‧‧Lightly doped area

TH1‧‧‧First contact hole

TH2‧‧‧Second contact hole

TH3‧‧‧The third contact hole

TH4‧‧‧The fourth contact hole

TH5‧‧‧Fifth contact hole

TH6‧‧‧The sixth contact hole

TH7‧‧‧The seventh contact hole

TH8‧‧‧Eighth contact hole

TH9‧‧‧Ninth contact hole

W1, W2, W3, W4‧‧‧Width

FIG. 1A is a schematic top view showing the pixel structure according to the first embodiment of the present disclosure.

Figure 1B is a schematic cross-sectional view taken along the line 1B-1B' of Figure 1A.

FIG. 2 is a schematic cross-sectional view of the pixel structure according to the second embodiment of the present disclosure.

FIG. 3 is a schematic cross-sectional view of the pixel structure according to the third embodiment of the present disclosure.

Figure 4 is a drawing of the pixel structure according to the fourth embodiment of the present disclosure Top view schematic.

FIG. 5 is a schematic top view showing the pixel structure according to the fifth embodiment of the present disclosure.

FIG. 6 is a schematic top view showing a pixel structure according to the sixth embodiment of the present disclosure.

FIG. 7 is a schematic top view of a pixel structure according to the seventh embodiment of the present disclosure.

FIG. 8A is a schematic top view of the pixel structure according to the eighth embodiment of the present disclosure.

Fig. 8B is a schematic cross-sectional view taken along the line 8B-8B' of Fig. 8A.

FIG. 9 is a schematic top view showing a pixel structure according to the ninth embodiment of the present disclosure.

Hereinafter, a plurality of embodiments of the present invention will be disclosed in drawings. For clear description, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventionally used structures and elements are shown in the drawings in a simple and schematic manner. In this article, the terms first, second, third, etc. are used to identify different elements, regions, and layers, rather than to limit the content of the disclosure.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals indicate the same element. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connections.

As used herein, "about" or "approximately" or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the measurement The specific amount of associated error (ie, the limit of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%.

Please see FIG. 1A and FIG. 1B. FIG. 1A is a schematic top view showing the pixel structure 100A according to the first embodiment of the present disclosure, and FIG. 1B shows the line segment 1B-1B along the line 1A in FIG. 'S schematic cross-section. For the convenience of description, Figure 1A shows the first direction D1 and the second direction D2, and the first direction D1 and the second direction D2 are different, for example, the first direction D1 and the second direction D2 are respectively shown in Figure 1A The transverse direction and the longitudinal direction are orthogonal to each other.

The pixel structure 100A can be applied as a display panel (not shown), for example, can be combined with a liquid crystal layer (not shown) and a color filter substrate (not shown) to form a display panel. The pixel structure 100A is disposed on a substrate 102, where the substrate 102 may be a transparent substrate, such as a glass substrate. The pixel structure 100A includes scan lines 110A and 110B, data lines 112A and 112B, channel layer 120, gate insulating layer 130, first gate 132, second gate 134, dielectric layer 136, source/drain The electrode 138, the connection electrode 140, the flat layer 142, and the pixel electrode 144.

The scan lines 110A and 110B extend along the first direction D1 and are arranged along the second direction D2, while the data lines 112A and 112B extend along the second direction D2 and are arranged along the first direction D1, and the scan lines 110A and 110B so arranged The data lines 112A and 112B are interlaced with each other to define the pixel area 104 therebetween.

The channel layer 120 is disposed on the substrate 102, and in a top view (as depicted in FIG. 1A), the channel layer 120 extends from the data line 112A into the pixel area 104 and intersects the scan line 110A. The channel layer 120 has a first area A1, a second area A2, a third area A3, a fourth area A4, and a fifth area A5 (in order not to make Figure 1A too complicated, the labels of these areas are marked in Figure 1B ), where the second area A2 is located between the first area A1 and the third area A3, and the first area A1, the second area A2, and the third area A3 are located between the fourth area A4 and the fifth area A5. Specifically, the fourth area A4 of the channel layer 120 overlaps the data line 112A, and the fourth area A4 extends from the overlap in the first direction D1, turns and then extends along the second direction D2. The first area A1 is connected to the fourth area A4 and overlaps the scan line 110A, and the first area A1, the second area A2, the third area A3, and the fifth area A5 are arranged in order along the second direction D2, that is, the channel The arrangement direction of the first area A1, the second area A2, the third area A3, and the fifth area A5 of the layer 120 are arranged along the same direction and different from the extension direction of the scan lines 110A and 110B.

The material of the channel layer 120 may include crystalline silicon material or amorphous silicon material, such as monocrystalline silicon, microcrystalline silicon, polycrystalline silicon, metal oxide, or the like, and the channel layer 120 may be diffused, ion implanted, and electrically conductive. Paste treatment or other suitable processes to change the conductivity of some areas to define the conductor area (can be Used for channel area) and semiconductor area. Taking Figure 1B as an example, the second area A2, the fourth area A4, and the fifth area A5 may include a heavily doped area P+ and a lightly doped area P-, and the heavily doped area P+ and the lightly doped area P- The doping concentration is greater than that of the first area A1 and the third area A3, so that the conductivity of the second area A2, the fourth area A4, and the fifth area A5 is greater than that of the first area A1 and the third area A3 . This configuration is only an example, and in other embodiments, the lightly doped region may be omitted or other doping distribution configurations may be adopted. In this configuration, the first area A1 and the third area A3 can be semiconductor areas and can be used as channel areas, while the second area A2, fourth area A4, and fifth area A5 can be conductor areas and can be used as The source/drain region is used. In other embodiments, the second area A2, the fourth area A4, and the fifth area A5 may also be N-type dopants to form a heavily doped area N+ and a lightly doped area N-, which will not be repeated here. .

The gate insulating layer 130 covers the channel layer 120. The material of the gate insulating layer 130 may include inorganic materials (for example, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof). The first gate 132 and the second gate 134 are disposed on the gate insulating layer 130, and the first gate 132 and the second gate 134 are respectively located in the first area A1 and the third area A3 of the channel layer 120 Above, that is, the vertical projection of the first gate 132 on the channel layer 120 will overlap with the first area A1, and the vertical projection of the second gate 134 on the channel layer 120 will overlap with the third area A3.

In addition, the vertical projection area of the first gate 132 and the second gate 134 on the substrate 102 may be larger than the vertical projection area of the first area A1 and the third area A3 on the substrate 102, respectively. For example, the width W1 of the second gate electrode 134 (that is, its length in the first direction D1) is greater than the width W2 of the channel layer 120 in the pixel region 104 (that is, its length in the first direction D1) , So that the second gate 134 is suitable As a mask for the channel layer 130 during doping. In other words, when the channel layer 120 is doped, the boundary position of the first area A1 and the third area A3 of the channel layer 120 can be defined by the first gate 132 and the second gate 134, and therefore, the doping is performed After doping, as shown in FIG. 1B, the boundaries of the first gate 132 and the second gate 134 will be aligned with the first area A1 and the third area A3 of the channel layer 120, respectively. In addition, the width of each layer can be determined according to a design rule. For example, in some embodiments, the width W2 of the channel layer 120 can be between 2 μm and 3 μm, such as 2.5 μm. The scan lines 110A and 110B, the first gate 132 and the second gate 134 may be formed by patterning the same metal layer, wherein the scan line 110A and the first gate 132 are connected to each other, or the first gate 132 may be connected to each other. A gate 132 is regarded as part of the scan line 110A.

The dielectric layer 136 is disposed on the gate insulating layer 130 and has a first contact hole TH1 in common with the gate insulating layer 130, wherein the first contact hole TH1 is located on the fourth region A4 of the channel layer 120. The material of the dielectric layer 136 can be an organic material or an inorganic material, such as epoxy resin, silicon oxide (SiOx), silicon nitride (SiNx), a composite layer composed of silicon oxide and silicon nitride, or other suitable materials. Dielectric materials.

The source/drain electrode 138 is disposed on the dielectric layer 136. The source/drain electrode 138 and the data line 112A are connected to each other, or the source/drain electrode 138 can also be regarded as a part of the data line 112A. For example, the data line 112A is connected to the fourth area A4 of the channel layer 120. The overlap can be regarded as the source/drain electrode 138. The source/drain electrode 138 may be connected to the fourth area A4 of the channel layer 120 through the first contact hole TH1 and form an interface.

The connecting electrode 140 is disposed on the dielectric layer 136 and is connected to the source/ The drain electrodes 138 are separated from each other. The dielectric layer 136 may further have a second contact hole TH2 and a third contact hole TH3, which are respectively located on the first gate 132 and the second gate 134, so that the connection electrode 140 can pass through the second contact hole TH2 and The third contact hole TH3 is respectively connected to the first gate 132 and the second gate 134 and forms an interface, thereby electrically connecting the first gate 132 and the second gate 134. Since the connecting electrode 140 can be electrically connected to the first gate 132 and the second gate 134, when a voltage is applied to the first gate 132 through the scan line 110A, the applied voltage can be transmitted to the first gate 132 through the connecting electrode 140 The second gate 134 makes the first area A1 and the third area A3 of the channel layer 120 in a conductive state.

In the top view angle (ie, the view angle as depicted in FIG. 1A), the connecting electrode 140 overlaps the channel layer 120 and falls within the boundary range of the channel layer 120. Specifically, the vertical projection of the connecting electrode 140 on the channel layer 120 will at least partially overlap the first area A1, the second area A2, and the third area A3 of the channel layer 120. In this regard, since the connecting electrode 140 falls within the boundary range of the channel layer 120 in a top view, it is possible to electrically connect the first gate electrode 132 and the second gate electrode 132 without affecting the aperture ratio of the pixel structure 100A. Gate 134.

In addition, the data lines 112A and 112B, the source/drain electrodes 138 and the connection electrode 140 can be formed by patterning the same metal layer. Therefore, the manufacturing process of the pixel structure 100A will not cause the manufacturing process due to the need to form the connection electrode 140 Too complicated. In the case where the data lines 112A and 112B, the source/drain electrodes 138 and the connection electrode 140 are formed by the same metal layer, the data lines 112A and 112B, the source/drain electrodes 138 and the connection electrode 140 may include the same Materials, such as metallic materials, such as copper, molybdenum, tungsten or other suitable metals.

The flat layer 142 is disposed on the dielectric layer 136 and covers the source/ The drain electrode 138 and the connection electrode 140, and the flat layer 142 can be made of organic or inorganic materials, such as epoxy resin, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide and silicon nitride. Composite layer or other suitable dielectric materials. The gate insulating layer 130, the dielectric layer 136, and the flat layer 142 may have a fourth contact hole TH4 in common, and the fourth contact hole TH4 is located on the fifth area A5 of the channel layer 120.

The pixel electrode 144 is disposed on the dielectric layer 136 and the flat layer 142 and is located in the pixel area 104. The material of the pixel electrode 144 may include a transparent conductive material, such as indium tin oxide, indium zinc oxide, zinc oxide, indium gallium zinc oxide, or other suitable materials. The pixel electrode 144 can be connected to the fifth area A5 of the channel layer 120 through the fourth contact hole TH4, and forms an interface I1 with the channel layer 120, and the vertical projection of the second gate 134 on the channel layer 120 is located at the interface I1 and the first gate 132 are between the vertical projection of the channel layer 120.

With the above configuration, the channel layer 120 can form two transistors together with the first gate 132 and the second gate 134, and since the vertical projection of the second gate 134 on the channel layer 120 is located at the interface I1 and the first gate A gate 132 is between the vertical projections of the channel layer 120, so the two transistors and the pixel electrode 144 are connected in series. By using two transistors in series with the pixel electrode 144, leakage current can be suppressed. When the scan line 110A provides voltage to the first gate 132 connected to it, the voltage can also be provided to the second gate 134 through the connecting electrode 140 to drive the transistor formed by the channel layer 120, so that the picture The element electrode 144 is coupled out of the electric field.

Since the connection electrode 140 can electrically connect the first gate electrode 132 to the second gate electrode 134 without affecting the aperture ratio, the connection electrode 140 The arrangement position of the pixel electrode 144 does not interfere with the arrangement area of the pixel electrode 144. Furthermore, if the first gate electrode 132 is electrically connected to the second gate electrode 134 to be achieved by using a layer that reduces the aperture ratio, this layer will be squeezed to the area of the pixel electrode 144 . That is to say, compared to using a layer that will reduce the aperture ratio, the above configuration can increase the area of the pixel electrode 144, thereby improving the image display quality of the display panel using the pixel structure 100A. Although Figure 1B does not depict other structures on the pixel electrode 144, in other embodiments, a display medium layer (such as a liquid crystal layer), a filter layer, a light shielding layer, or Other layers.

Please refer to FIG. 2. FIG. 2 is a schematic cross-sectional view of the pixel structure 100B according to the second embodiment of the present disclosure. The cross-sectional position depicted in FIG. 2 is along the channel layer 120, which is similar to the cross-sectional position in FIG. 1B. At least one difference between this embodiment and the first embodiment is that the connection electrode 140 of this embodiment can be located on the flat layer 142. Specifically, the connection electrode 140 and the pixel electrode 144 are disposed on the flat layer 142 and separated from each other. The dielectric layer 136 and the flat layer 142 may have a fifth contact hole TH5 and a sixth contact hole TH6 together, and the fifth contact hole TH5 and the sixth contact hole TH6 are located between the first gate 132 and the second gate 134, respectively on. The connecting electrode 140 can connect to the first gate 132 and the second gate 134 through the fifth contact hole TH5 and the sixth contact hole TH6, respectively, and form an interface.

The connection electrode 140 and the pixel electrode 144 may be formed by patterning the same layer, and therefore they may include the same material. For example, the connection electrode 140 and the pixel electrode 144 may include the same transparent conductive material and have the same thickness (thickness located on the flat layer 142). And due to the connection electrode The pixel electrode 140 and the pixel electrode 144 can be formed by patterning the same layer, so the manufacturing process of the pixel structure 100B will not be too complicated due to the requirement of forming the connection electrode 140.

Please refer to FIG. 3, which is a schematic cross-sectional view of the pixel structure 100C according to the third embodiment of the present disclosure. The cross-sectional position depicted in FIG. 3 is along the channel layer 120, which is similar to the cross-sectional position in FIG. 1B. At least one difference between this embodiment and the first embodiment is that the pixel structure 100C further includes conductive pads 150A and 150B and a dielectric layer 152. The dielectric layer 152 is located between the dielectric layer 136 and the flat layer 142. The conductive pads 150A and 150B and the source/drain electrodes 138 are located on the dielectric layer 136 and are jointly covered by the dielectric layer 152. In addition, the conductive pads 150A and 150B and the source/drain electrodes 138 can be formed by patterning the same metal layer, and therefore they will contain the same material and have the same thickness (the thickness above the dielectric layer 136). ). The conductive pads 150A and 150B can respectively connect the first gate 132 and the second gate 134 through the second contact hole TH2 and the third contact hole TH3 to form an interface, thereby electrically connecting the first gate 132 and the second gate 134.

The dielectric layer 152 may have a seventh contact hole TH7 and an eighth contact hole TH8, and the seventh contact hole TH7 and the eighth contact hole TH8 are respectively located on the conductive pads 150A and 150B, and are also located on the first gate respectively 132 and the second gate 134. The connection electrode 140 is located on the dielectric layer 152 and the conductive pads 150A and 150B, and is connected to the conductive pads 150A and 150B through the seventh contact hole TH7 and the eighth contact hole TH8, respectively, to be electrically connected through the conductive pads 150A and 150B, respectively The first gate 132 and the second gate 134. The connection electrode 140 may include a metal material, such as copper, molybdenum, tungsten, or other suitable metals. The connection electrode 140 can It is formed through a patterned metal layer. For the remaining metal layer after patterning, a part of the remaining metal layer will be the connecting electrode 140, and the other part of the remaining metal layer may be a circuit layer, such as It can be a circuit layer used to connect touch electrodes (not shown) or a circuit layer used to connect other layers. In other words, the connecting electrode 140 can be formed together with other circuit layers used in the pixel structure 100C. Therefore, the manufacturing process of the pixel structure 100C will not be too complicated due to the requirement of forming the connecting electrode 140.

Please refer to FIG. 4, which is a schematic top view of the pixel structure 100D according to the fourth embodiment of the present disclosure. At least one difference between this embodiment and the first embodiment is that the first area A1 and the second area A2 of the channel layer 120 of this embodiment are arranged along the first direction D1, while the second area A2 of the channel layer 120 And the third area A3 is arranged along the second direction D2. In other words, the channel layer 120 of this embodiment will have a bent appearance at the second area A2. Similarly, the connecting electrode 140 overlaps the channel layer 120 and falls within the boundary of the channel layer 120, and the vertical projection of the connecting electrode 140 on the channel layer 120 corresponds to the first area A1, the second area A2, and the third area A3. At least partially overlap. Since the channel layer 120 has a bent appearance at the second area A2, the connecting electrode 140 also has a bent appearance at the second area A2 corresponding to the channel layer 120. In other words, the pattern of the connection electrode 140 can be adjusted corresponding to the pattern shape of the channel layer 120, so that even if the layout configuration changes, the connection electrode 140 will not affect the aperture ratio due to the change.

Please refer to FIG. 5. FIG. 5 is a schematic top view of the pixel structure 100E according to the fifth embodiment of the present disclosure. At least one difference between this embodiment and the first embodiment is that the channel layer 120 of this embodiment has The arrangement direction of the first area A1, the second area A2, and the third area A3 is parallel to the extending direction of the scan lines 110A and 110B. Specifically, the scan lines 110A and 110B extend along the first direction D1, and the first area A1, the second area A2, and the third area A3 of the channel layer 120 are also arranged along the first direction D1. Similarly, the connecting electrode 140 overlaps the channel layer 120 and falls within the boundary of the channel layer 120, and the vertical projection of the connecting electrode 140 on the channel layer 130 is the same as the first area A1, the second area A2, and the third area A3. At least partially overlap. Since the first area A1, the second area A2, and the third area A3 of the channel layer 120 are arranged along the first direction D1, the connection electrode 140 will correspondingly extend along the first direction D1 and be connected to the scan lines 110A and 110A. 110B parallel. In other words, even if the layout is changed, the connection electrode 140 will not affect the aperture ratio due to the change.

Please refer to FIG. 6, which is a schematic top view of a pixel structure 100F according to a sixth embodiment of the present disclosure. At least one difference between this embodiment and the first embodiment is that the scan line 110A and the second gate (not marked with component symbols; it corresponds to the third area A3 of the channel layer 120 and overlaps the connection electrode 140) are mutually Connect, or consider the second gate as part of the scan line 110A. In addition, similarly, the connecting electrode 140 overlaps the channel layer 120 and falls within the boundary of the channel layer 120, and the vertical projection of the connecting electrode 140 on the channel layer 120 corresponds to the first area A1, the second area A2, and the third area. Area A3 overlaps at least partially. In other words, even if the layout is changed, the connection electrode 140 will not affect the aperture ratio due to the change.

Please refer to FIG. 7, which is a schematic top view of a pixel structure 100G according to a seventh embodiment of the present disclosure. At least one difference between this embodiment and the first embodiment is that the connection electrode 140 of this embodiment is The width of the middle part can be smaller than the width of the two ends. Specifically, the connecting electrode 140 includes a connecting portion 140A and a pair of electrode pads 140B and 140C, wherein the connecting portion 140A is located between the electrode pads 140B and 140C. The vertical projection of the connecting portion 140A of the connecting electrode 140 on the channel layer 120 will partially overlap with the second area A2 of the channel layer 120, and the vertical projection of the electrode pads 140B and 140C of the connecting electrode 140 on the channel layer 120 will respectively overlap with the channel layer 120. The first area A1 and the third area A3 partially overlap. The width W3 of the connecting portion 140A is smaller than the width W4 of the electrode pads 140B and 140C. Furthermore, the length of the connecting portion 140A in the first direction D1 is smaller than the length of the electrode pads 140B and 140C in the first direction D1. In this embodiment, the shape of the connecting electrode 140 can be adjusted correspondingly according to the size or resolution of the pixel structure 100G. Furthermore, if the design rules permit, the shape of the connecting electrode 140 can be designed as shown in FIG. 7 to reduce the parasitic capacitance coupled by the connecting electrode 140.

Please refer to FIG. 8A and FIG. 8B. FIG. 8A is a schematic top view of the pixel structure 100H according to the eighth embodiment of the present disclosure, and FIG. 8B shows the line segment 8B-8B' along the line of FIG. 8A. Schematic diagram of the cross-section. At least one difference between this embodiment and the first embodiment is that the channel layer 120 of this embodiment can form more than two transistors. Specifically, the channel layer 120 further has a sixth area A6 and a seventh area A7. The third area A3, the sixth area A6, the seventh area A7, and the fifth area A5 are arranged in order along the second direction D2. That is, the sixth area A6 and the seventh area A7 will be located between the third area A3 and the fifth area A5, and the sixth area A6 will be located between the third area A3 and the seventh area A7. The conductivity of the sixth area A6 can be greater than the conductivity of the seventh area A7. The difference in conductivity between the sixth area A6 and the seventh area A7 can be caused by diffusion, ion implantation, plasma treatment or other suitable processes. Come Reached.

The pixel structure 100H further includes a third gate 160, wherein the third gate 160 is disposed on the gate insulating layer 130 and covered by the dielectric layer 136, and is located on the seventh area A7. The channel layer 120 can form three transistors together with the first gate 132, the second gate 134, and the third gate 160 to further prevent leakage current. The dielectric layer 136 may further have a ninth contact hole TH9, and the ninth contact hole TH9 is located on the seventh area A7. The connecting electrode 140 can extend from above the first area A1, through the second area A2, the third area A3, and the sixth area A6 to above the seventh area A7, and the vertical projection of the connecting electrode 140 on the channel layer 120 is the same as The second area A2, the third area A3, the sixth area A6, and the seventh area A7 at least partially overlap. The connection electrode 140 extending to the seventh area A7 can be connected to the third gate electrode 160 through the ninth contact hole TH9 and form an interface to electrically connect the third gate electrode 160. The pixel electrode 144 is still connected to the fifth area A5 of the channel layer 120 through the fourth contact hole TH4, and forms an interface I1 with the channel layer 120. The second gate electrode 134 and the third gate electrode 160 are in the channel layer 120 The vertical projection is located between the interface I1 and the vertical projection of the first gate 132 on the channel layer 120.

With this configuration, when the scan line 110A provides voltage to the second gate 134 connected to it, the voltage can also be provided to the first gate 132 and the third gate 160 through the connecting electrode 140 to drive the channel layer The transistor formed by 120 can couple the pixel electrode 144 out of the electric field. When the channel layer 120 is designed to form more than two transistors, in a top view, the connection electrode 140 still overlaps the channel layer 120 and falls within the boundary range of the channel layer 120. Therefore, the connection electrode 140 It will not affect the aperture ratio due to changes in the layout.

Please refer to FIG. 9, which is a schematic top view of a pixel structure 100I according to a ninth embodiment of the present disclosure. At least one difference between this embodiment and the eighth embodiment is that the scan line 110A of this embodiment is the same as the first gate (unmarked component symbol; it is the first area A1 corresponding to the channel layer 120 and is connected to the connecting electrode 140 overlap) are interconnected, or the first gate can also be regarded as a part of the scan line 110A. Similarly, the connection electrode 140 overlaps the channel layer 120 and falls within the boundary range of the channel layer 120. Therefore, even if the layout of the pixel structure 100I is changed, the connection electrode 140 will not affect the aperture ratio due to the change in the layout.

In summary, the pixel structure of the present disclosure includes a channel layer, a first gate, a second gate, a connection electrode, and a pixel electrode. The first gate and the second gate are arranged on the channel layer, and together with the channel layer form more than one transistor. The pixel electrode is electrically connected to the channel layer and can be driven by a transistor formed by the channel layer, the first gate and the second gate. Since more than one transistor is used to drive the pixel electrodes, leakage current can be suppressed. The connecting electrode is arranged on the channel layer and electrically connected to the first gate and the second gate, and the vertical projection of the connecting electrode on the channel layer will fall within the boundary of the channel layer, so that the connecting electrode can not affect the opening In the case of high efficiency, the first gate electrode is electrically connected to the second gate electrode, so the arrangement position of the connection electrode will not be pushed out of the arrangement position and area of the pixel electrode. In addition, when the vertical projection of the connection electrode on the channel layer falls within the boundary of the channel layer, even when the layout of the pixel structure changes, the connection electrode can adjust its pattern shape corresponding to the change, so that The connection electrode will not affect the aperture ratio due to changes. Therefore, the connecting electrodes configured in this way can be adapted to a variety of different pixel structure layouts, and the aperture ratio of different layouts can be improved.

Although the present invention has been disclosed in various embodiments as above, it is not intended to limit the present invention. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of the attached patent application.

102‧‧‧Substrate

120‧‧‧Passage layer

130‧‧‧Gate insulation layer

132‧‧‧First Gate

134‧‧‧Second Gate

136‧‧‧Dielectric layer

138‧‧‧Source/Drain electrode

140‧‧‧Connecting electrode

142‧‧‧flat layer

144‧‧‧Pixel electrode

A1‧‧‧District 1

A2‧‧‧Second District

A3‧‧‧The third area

A4‧‧‧Area 4

A5‧‧‧District 5

I1‧‧‧Interface

P+‧‧‧Heavy doped area

P-‧‧‧Lightly doped area

TH1‧‧‧First contact hole

TH2‧‧‧Second contact hole

TH3‧‧‧The third contact hole

TH4‧‧‧The fourth contact hole

1B-1B’‧‧‧line segment

Claims (12)

A pixel structure includes: a channel layer disposed on a substrate and having a first area, a second area and a third area, wherein the second area is located in the first area and the third area And the conductivity of the second region is greater than the conductivity of the first region and the third region; a gate insulating layer covering the channel layer; a first gate and a second gate, Is disposed on the gate insulating layer, and respectively located on the first region and the third region; a dielectric layer is disposed on the gate insulating layer; and a connecting electrode is disposed on the dielectric Above the electrical layer, and electrically connected to the first gate and a second gate, and the vertical projection of the connecting electrode on the channel layer is at least partially with the first area, the second area and the third area overlapping. In the pixel structure described in item 1 of the scope of patent application, the first area, the second area and the third area are arranged along the same direction. For the pixel structure described in item 1 of the scope of patent application, the first area and the second area are arranged along a first direction, and the second area and the third area are arranged along a second direction, And the first direction is different from the second direction. The pixel structure described in item 1 of the scope of patent application further includes: a scan line extending along a direction and connected to the first gate, wherein the The arrangement direction of the first zone, the second zone and the third zone is parallel to the direction. The pixel structure described in item 1 of the scope of patent application further includes: a scan line extending along a direction and connected to the first gate electrode; and a pixel electrode disposed on the dielectric layer, and Connected to the channel layer to form an interface with the channel layer, wherein the arrangement direction of the first region, the second region, the third region, and the interface is different from the direction, and the second gate is at The vertical projection of the channel layer is located between the interface and the vertical projection of the first gate on the channel layer. The pixel structure described in item 1 of the scope of patent application further includes: a scan line extending along a direction and connected to the second gate electrode; and a pixel electrode disposed on the dielectric layer, and Connected to the channel layer to form an interface with the channel layer, wherein the arrangement direction of the first region, the second region, the third region, and the interface is different from the direction, and the second gate is at The vertical projection of the channel layer is located between the interface and the vertical projection of the first gate on the channel layer. For the pixel structure described in item 1 of the scope of patent application, the channel layer further has a fourth area and a fifth area, the fourth area is located between the third area and the fifth area, and the The conductivity of the fourth region is greater than that of the fifth region, and the pixel structure further includes: A third gate is disposed on the gate insulating layer and located on the fifth region, wherein the connecting electrode is more electrically connected to the third gate, and the connecting electrode is perpendicular to the channel layer The projection system at least partially overlaps the third zone, the fourth zone, and the fifth zone. For example, the pixel structure described in any one of items 1 to 7 of the scope of patent application further includes: a source/drain electrode disposed on the dielectric layer and connected to the channel layer, wherein the The source/drain electrode and the connection electrode comprise the same material; and a flat layer is arranged on the dielectric layer and covers the source/drain electrode and the connection electrode. The pixel structure according to any one of items 1 to 7 of the scope of the patent application further includes: a flat layer disposed on the dielectric layer, wherein the connecting electrode is located on the flat layer; And a pixel electrode arranged on the flat layer and connected to the channel layer, wherein the pixel electrode and the connecting electrode comprise the same material. For example, the pixel structure described in any one of items 1 to 7 of the scope of the patent application further includes: a plurality of conductive pads disposed on the dielectric layer and respectively connected to the first gate and the second Two gates, where the connecting electrode is located on the dielectric layer and On the conductive pads, the first gate electrode and the second gate electrode are electrically connected through the conductive pads, and the connecting electrode includes a metal material. The pixel structure according to item 1 of the scope of patent application, wherein the connecting electrode includes a connecting portion and a pair of electrode pads, the connecting portion is between the pair of electrode pads, and the width of the connecting portion is smaller than the pair of electrode pads The width. The pixel structure described in claim 1, wherein the vertical projection area of the first gate and the second gate on the substrate is larger than the vertical projection of the first zone and the third zone on the substrate, respectively area.

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