CN115598890B

CN115598890B - Array substrate and display panel

Info

Publication number: CN115598890B
Application number: CN202211249705.8A
Authority: CN
Inventors: 龙时宇
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2022-10-12
Filing date: 2022-10-12
Publication date: 2024-07-05
Anticipated expiration: 2042-10-12
Also published as: CN115598890A

Abstract

The application provides an array substrate and a display panel, comprising: a substrate; a plurality of pixel electrodes disposed on the substrate; the common electrode is arranged on the substrate, is overlapped with the plurality of pixel electrodes in the thickness direction of the array substrate, is overlapped with the plurality of pixel electrodes and is electrically insulated, and forms a part of a storage capacitor together with each pixel electrode; wherein, at least one pixel electrode comprises a pixel electrode concave-convex structure, and the pixel electrode concave-convex structure comprises a pixel electrode concave structure and a pixel electrode convex structure; and/or the common electrode includes a common electrode concave-convex structure overlapping with the at least one pixel electrode, the common electrode concave-convex structure including a common electrode concave structure and a common electrode convex structure. According to the application, the at least one pixel electrode comprises a pixel electrode concave-convex structure, and/or the common electrode comprises a common electrode concave-convex structure overlapped with the at least one pixel electrode, so that the capacitance value of the at least one storage capacitor is increased, and the crosstalk risk is reduced.

Description

Array substrate and display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate and a display panel.

Background

With the rapid development of 5G communication technology, virtual Reality (VR) technology is in a rapid development stage. Currently, the pixel density of the display screen is very high by the virtual reality technology, the pixel area of a single pixel of the display screen is required to be extremely small, however, for the liquid crystal display screen, the crosstalk risk occurs when the pixel area is small.

Therefore, how to improve the crosstalk risk caused by the smaller pixel area of the liquid crystal display screen is a technical problem to be solved.

Disclosure of Invention

The application aims to provide an array substrate and a display panel, which are used for increasing the capacitance value of a storage capacitor of the array substrate and reducing the crosstalk risk during display of the display panel.

In order to achieve the above purpose, the technical scheme is as follows:

an array substrate, the array substrate comprising:

a substrate;

A plurality of pixel electrodes disposed on the substrate; and

A common electrode disposed on the substrate, stacked with the plurality of pixel electrodes in the thickness direction of the array substrate, overlapped with the plurality of pixel electrodes and electrically insulated from the plurality of pixel electrodes, and forming a portion of a storage capacitor together with each of the pixel electrodes;

Wherein at least one pixel electrode comprises a pixel electrode concave-convex structure, and the pixel electrode concave-convex structure comprises a pixel electrode concave structure and a pixel electrode convex structure; and/or the number of the groups of groups,

The common electrode includes a common electrode concave-convex structure overlapping at least one of the pixel electrodes, the common electrode concave-convex structure including a common electrode concave structure and a common electrode convex structure.

In some embodiments, the array substrate further includes a plurality of pixel electrodes, each of the pixel electrodes including a pixel electrode concave-convex structure disposed adjacent to the pixel electrode convex structure;

The common electrode comprises a common electrode concave-convex structure overlapped with at least one pixel electrode, the common electrode concave structure is arranged adjacent to the common electrode convex structure, the common electrode concave structure is overlapped with the pixel electrode concave structure, and the common electrode convex structure is overlapped with the pixel electrode convex structure.

In some embodiments of the array substrate, the array substrate further includes:

The first planarization layer is arranged on the substrate, a plurality of pixel electrodes and the common electrode are positioned on one side, far away from the substrate, of the first planarization layer, a planarization layer concave-convex structure is arranged on the surface, far away from the substrate, of the first planarization layer, the planarization layer concave-convex structure comprises a planarization layer concave structure and a planarization layer convex structure, the planarization layer concave structure is overlapped with the pixel electrode concave structure, and the planarization layer convex structure is overlapped with the pixel electrode convex structure.

In the array substrate of some embodiments, the common electrode is located between the first planarization layer and the plurality of pixel electrodes in a thickness direction of the array substrate, and the planarization layer convex structure is in contact with the common electrode convex structure; or alternatively, the first and second heat exchangers may be,

In the thickness direction of the array substrate, a plurality of pixel electrodes are positioned between the first planarization layer and the common electrode, and the planarization layer convex structure is in contact with the pixel electrode convex structure.

In some embodiments, the thickness of the first planarization layer at the position of the protruding structure of the planarization layer is greater than the thickness of the first planarization layer at the position of the recessed structure of the planarization layer.

In some embodiments, the material of the first planarization layer includes an organic material, and the thickness of the first planarization layer is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers.

the passivation layer is arranged between the public electrode and the pixel electrodes and is contacted with the public electrode and the pixel electrodes, the passivation layer comprises a passivation layer concave-convex structure, the passivation layer concave-convex structure comprises a passivation layer concave structure and a passivation layer convex structure, the passivation layer concave structure is overlapped with the public electrode concave structure and the pixel electrode concave structure, and the passivation layer convex structure is contacted with the public electrode convex structure and the pixel electrode convex structure.

the second planarization layer is arranged on the substrate and is positioned on one side of the plurality of pixel electrodes and the common electrode away from the substrate.

The driving circuit layer is arranged on the substrate, a plurality of pixel electrodes and the common electrode are arranged on one side, far away from the substrate, of the driving circuit layer, and the driving circuit layer comprises a plurality of thin film transistors, and one pixel electrode is electrically connected with at least one thin film transistor.

A display panel comprising an array substrate of some of the embodiments described above.

The beneficial effects are that: the application provides an array substrate and a display panel, wherein at least one pixel electrode comprises a pixel electrode concave-convex structure, the pixel electrode concave-convex structure comprises a pixel electrode concave structure and a pixel electrode convex structure, and/or a common electrode comprises a common electrode concave-convex structure overlapped with at least one pixel electrode, and the common electrode concave-convex structure comprises a common electrode concave structure and a common electrode convex structure, so that the facing area between at least one pixel electrode and the common electrode is increased, the capacitance value of at least one storage capacitor is increased, and the crosstalk risk existing when the storage capacitance of the display panel is smaller is improved.

Drawings

FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the application;

FIG. 2 is a schematic plan view of the pixel electrode and the first planarization layer shown in FIG. 1;

FIG. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the application;

fig. 4 is a schematic cross-sectional view of a display device according to an embodiment of the application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.

Referring to fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the application, and fig. 2 is a schematic plan view of the pixel electrode and the first planarization layer shown in fig. 1.

In the present embodiment, the display panel 100 is a liquid crystal display panel. The display panel 100 has a display area and a non-display area located at the periphery of the display area. The display panel 100 includes an array substrate 101 and a color film substrate 102, the array substrate 101 is disposed opposite to the color film substrate 102, and a liquid crystal layer (not shown) is disposed between the array substrate 101 and the color film substrate 102.

In the present embodiment, the array substrate 101 includes a substrate 10, a driving circuit layer 20, a first planarization layer 30, a common electrode 40, a passivation layer 50, a plurality of pixel electrodes 60, and a second planarization layer 70.

In the present embodiment, the substrate 10 is a glass substrate. The driving circuit layer 20 is disposed on the substrate 10. The driving circuit layer 20 includes a light shielding layer 201, a buffer layer 202, and a plurality of thin film transistors T.

The light shielding layer 201 plays a role of shielding light, and is located in the display area. The light shielding layer 201 is disposed on the surface of the substrate 10. The material of the light shielding layer 201 includes a metal, but is not limited thereto, and the material of the light shielding layer may also include a black organic material.

The buffer layer 202 covers the light shielding layer 201 and the substrate 10, and is located in the display region and the peripheral region. The material of the buffer layer 202 includes, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride.

The thin film transistors T are disposed on the surface of the buffer layer 202 away from the substrate 10 and are located in the display area. The plurality of thin film transistors T are top gate thin film transistors, but not limited thereto, and the plurality of thin film transistors T may be bottom gate thin film transistors. The thin film transistors T are low temperature polysilicon thin film transistors, metal oxide transistors or amorphous silicon transistors.

Each thin film transistor T includes an active layer 203, a gate insulating layer 204, a gate electrode 205, an interlayer insulating layer 206, and a source-drain electrode 207.

The active layer 203 is disposed on the buffer layer 202 and overlaps the light shielding layer 201. The active layer 203 has one channel region and two heavily doped regions located at opposite sides of the one channel region. The channel region of the active layer 203 overlaps the light shielding layer 201 such that the light shielding layer 201 shields light incident to the channel region of the active layer 203.

It should be noted that, the channel region of the active layer 203 is not subjected to an ion doping treatment, and the heavily doped region of the active layer 203 is subjected to an ion doping treatment, and ions used in the ion doping treatment include, but are not limited to, phosphorus ions.

In addition, when the active layer 203 is a low-temperature polysilicon active layer, the active layer 203 further has two lightly doped regions, and a lightly doped region is disposed between one heavily doped region and the channel region. The ion doping concentration of the heavily doped region of the active layer 203 is greater than the ion doping concentration of the lightly doped region of the active layer 203.

The gate insulating layer 204 covers the active layer 203 and the buffer layer 202, and is located in the display region and the non-display region. The material of the gate insulating layer 204 includes, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride.

The gate electrode 205 is disposed on the gate insulating layer 204 and overlaps the channel region of the active layer 203. The material of the gate electrode 205 includes, but is not limited to, molybdenum, aluminum, titanium, copper, or silver.

The interlayer insulating layer 206 covers the gate electrode 205 and the gate insulating layer 204, and is located in the display region and the non-display region. The material of the interlayer insulating layer 206 includes, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride.

The source/drain electrode 207 is disposed on the interlayer insulating layer 206 and is located in the display region. The source-drain electrode 207 includes a source electrode 2071 and a drain electrode 2072, the source electrode 2071 being in contact with one heavily doped region of the active layer 203 through a first contact hole penetrating the interlayer insulating layer 206 and the gate insulating layer 204, and the drain electrode 2072 being in contact with the other heavily doped region of the active layer 203 through a second contact hole penetrating the interlayer insulating layer 206 and the gate insulating layer 204.

The driving circuit layer 20 further includes a transfer electrode 2073 in the non-display region, the transfer electrode 2073 being disposed in the same layer as the source and drain electrodes 207, the transfer electrode 2073 being of the same material as the source and drain electrodes 207. The transfer electrode 2073 and the source/drain electrode 207 are formed by patterning the same metal layer.

In this embodiment, the first planarization layer 30 is disposed on the substrate 10 and located in the display area and the non-display area. The first planarization layer 30 covers the source-drain electrode 207, the transfer electrode 2073, and the interlayer insulating layer 206 of the driving circuit layer 20.

The material of the first planarization layer 30 includes an organic material including, but not limited to, polyimide, polyacrylate, or silicone. Specifically, the material of the first planarization layer 30 includes an organic photoresist.

The thickness of the first planarization layer 30 is greater than or equal to 0.5 microns and less than or equal to 3 microns. For example, the thickness of the first planarizing layer 30 is 1 micron, 1.5 microns, 1.8 microns, 2.0 microns, 2.4 microns, 2.8 microns, or 3 microns.

The first planarization layer 30 has a planarization layer concave-convex structure 303 on a surface thereof away from the substrate 10, and the planarization layer concave-convex structure 303 includes a planarization layer concave structure 302 and a planarization layer convex structure 301, wherein the planarization layer concave structure 302 is disposed adjacent to the planarization layer convex structure 301.

The shape of the cross section of the planarization layer convex structure 301 in the direction parallel to the thickness direction of the display panel 100 is rectangular, trapezoidal, semicircular, semi-elliptical, or other shape. The shape of the cross section of the planarization layer concave structure 302 in a direction parallel to the thickness direction of the display panel 100 is rectangular, inverted trapezoidal, or other shape.

Specifically, in the present embodiment, the shape of the cross section of the planarizing-layer convex structure 301 in the direction parallel to the thickness direction of the display panel 100 is rectangular. The planarizing-layer recessed structure 302 has a rectangular shape in cross section parallel to the thickness direction of the display panel 100.

It is understood that in other embodiments, the cross-section of the planarization layer convex structure 301 in the direction parallel to the thickness direction of the display panel 100 may also be trapezoidal, and the cross-section of the planarization layer concave structure 302 in the direction parallel to the thickness direction of the display panel 100 may be inverted trapezoidal, so as to reduce the risk of breakage of a thin film layer formed on the planarization layer convex structure 301.

The thickness of the first planarization layer 30 at the location of the planarization layer convex structure 301 is greater than the thickness of the first planarization layer 30 at the location of the planarization layer concave structure 302.

Specifically, the thickness of the first planarization layer 30 at the location of the planarization layer convex structure 301 is greater than or equal to 1.5 micrometers and less than or equal to 3 micrometers, for example, the thickness of the first planarization layer 30 at the location of the planarization layer convex structure 301 is 1.8 micrometers, 2 micrometers, 2.2 micrometers, 2.4 micrometers, 2.6 micrometers, or 3 micrometers. The thickness of the first planarization layer 30 at the location of the planarization layer concave structure 302 is greater than 0 microns and less than or equal to 2 microns, for example, the thickness of the first planarization layer 30 at the location of the planarization layer concave structure 302 is 0.5 microns, 0.8 microns, 1.0 microns, 1.2 microns, 1.5 microns, 1.8 microns, or 2 microns.

When the material for preparing the first planarization layer 30 is an organic photoresist, the first planarization layer 30 is exposed by using a halftone mask, and after the exposed first planarization layer 30 is subjected to a development process, a portion of the first planarization layer 30 is thinned to form a planarization concave structure 302, and an un-thinned portion of the first planarization layer 30 is a planarization convex structure 301.

The recess depth H1 of the planarizing-layer recessed structure 302 is greater than 0 micrometers and less than or equal to 1 micrometer to further reduce the risk of film breakage subsequently formed in the planarizing-layer recessed structure 302. For example, the recess depth H1 of the planarizing-layer recess structure 302 is 0.1 micron, 0.3 micron, 0.5 micron, 0.7 micron, 0.9 micron, or 1 micron.

In the present embodiment, the common electrode 40 is loaded with a common voltage when the display panel 100 displays. The common electrode 40 is located in a display region and a non-display region. In the thickness direction of the array substrate 101, the common electrode 40 is located at a side of the first planarization layer 30 away from the substrate 10, and the common electrode 40 is in contact with a surface of the first planarization layer 30 away from the substrate 10.

In addition, the common electrode 40 is electrically connected to the transmission electrode 2073 through a third contact hole located in the non-display region and penetrating the first planarization layer 30 to transmit a common voltage signal to the common electrode 40 through the transmission electrode 2073. Further, the common electrode 40 is provided with an opening corresponding to the drain electrode 2072, the opening penetrating the common electrode 40 in the thickness direction of the common electrode 40.

The common electrode 40 is a block transparent electrode. The material of the common electrode 40 includes a transparent conductive material including indium tin oxide or indium zinc oxide.

The common electrode 40 includes a common electrode concave-convex structure 403, and the common electrode concave-convex structure 403 includes a common electrode concave structure 402 and a common electrode convex structure 401, and the common electrode concave structure 402 is disposed adjacent to the common electrode convex structure 401. The common electrode convex structure 401 is in contact with the planarization layer convex structure 301 and covers the planarization layer convex structure 301. The common electrode recess structure 402 overlaps the planarization layer recess structure 302.

After the common electrode 40 is formed on the surface of the first planarization layer 30 away from the substrate 10, a common electrode convex structure 401 is formed on the planarization layer convex structure 301, and a planarization layer concave structure 302 is formed in the planarization layer concave structure 302, and the thickness of the common electrode 40 at the position where the common electrode concave structure 402 and the common electrode convex structure 401 are located is the same or tends to be the same.

In the present embodiment, a plurality of pixel electrodes 60 are loaded with data voltages when the display panel 100 displays, and each pixel electrode 60 is electrically connected to at least one thin film transistor T.

In the present embodiment, the material of the plurality of pixel electrodes 60 includes a transparent conductive material including, but not limited to, indium tin oxide or indium zinc oxide. Each pixel electrode 60 includes a pixel electrode main body portion 604 and slits 605 distributed in the pixel electrode main body portion 604, the pixel electrode main body portion 604 being a transparent conductive portion, the slits 605 penetrating the pixel electrode 60 in the thickness direction of the pixel electrode 60.

It will be appreciated that in other embodiments, each pixel electrode 60 may also be a monolithic and non-slotted transparent conductive portion.

In the present embodiment, in the thickness direction of the array substrate 101, the plurality of pixel electrodes 60 are located on one side of the first planarization layer 30 away from the substrate 10, and the plurality of pixel electrodes 60 are located on the same layer and are electrically insulated from each other.

The common electrode 40 and the plurality of pixel electrodes 60 are stacked in a thickness direction of the array substrate 101, the passivation layer 50 is disposed between the common electrode 40 and the plurality of pixel electrodes 60, and the passivation layer 50 is in contact with both the common electrode 40 and the plurality of pixel electrodes 60 to electrically insulate between the common electrode 40 and the plurality of pixel electrodes 60. The common electrode 40 overlaps with the plurality of pixel electrodes 60, and each pixel electrode 60, a portion of the common electrode 40 overlapping with each pixel electrode 60, and the passivation layer 50 together constitute a storage capacitor.

Each pixel electrode 60 is connected to a drain electrode of one thin film transistor T through a fourth contact hole penetrating the passivation layer 50 and the first planarization layer 30, and a source electrode of one thin film transistor T is connected to a data line. When the data voltage transmitted by the data line changes, the changed data voltage charges the storage capacitor through the leakage current, and the smaller the capacitance value of the storage capacitor is, the larger the voltage changed by charging the storage capacitor is due to the leakage current, so that the risk of crosstalk is larger.

It should be noted that, the horizontal component of the electric field formed by the common voltage loaded by the common electrode 40 and the data voltage loaded by the pixel electrode 60 acts on the liquid crystal in the liquid crystal layer, and the liquid crystal deflects under the action of the horizontal component of the electric field, so as to control the light transmittance of the display panel 100, and further enable the display panel to realize display.

Specifically, in the present embodiment, the common electrode 40 is located between the first planarization layer 30 and the plurality of pixel electrodes 60, and the common electrode concave-convex structure 403 of the common electrode 40 overlaps with at least one pixel electrode 60.

The common electrode concave-convex structure 403 of the common electrode 40 of the array substrate 101 of the display panel 100 of this embodiment overlaps with at least one pixel electrode 60, so that the facing area between the common electrode 40 and at least one pixel electrode 60 is increased under the condition that the area of a single pixel of the display panel is unchanged, and further the capacitance value of the storage capacitor formed by the common electrode 40 and at least one pixel electrode 60 is increased, so as to improve the crosstalk risk existing in the smaller capacitance value of the storage capacitor.

In this embodiment, at least one pixel electrode 60 includes a pixel electrode concave-convex structure 603, the pixel electrode concave-convex structure 603 includes a pixel electrode concave structure 602 and a pixel electrode convex structure 601, the pixel electrode concave structure 602 is disposed adjacent to the pixel electrode convex structure 601, and the thicknesses of the pixel electrode 60 at the positions where the pixel electrode concave structure 602 and the pixel electrode convex structure 601 are located are the same or tend to be the same.

The common electrode concave structure 402 overlaps the pixel electrode concave structure 602, the common electrode convex structure 401 overlaps the pixel electrode convex structure 601, the planarizing layer concave structure 302 overlaps the pixel electrode concave structure 602, and the planarizing layer convex structure 301 overlaps the pixel electrode convex structure 601.

In the case that the area of a single pixel of the display panel is unchanged, the pixel electrode 60 includes the pixel electrode concave-convex structure 603, the common electrode concave structure 402 is overlapped with the pixel electrode concave structure 602, and the common electrode convex structure 401 is overlapped with the pixel electrode convex structure 601, so that the facing area between the common electrode 40 and the at least one pixel electrode 60 is further increased, the capacitance value of the storage capacitor formed by the common electrode 40 and the at least one pixel electrode 60 is further increased, and the crosstalk risk existing when the capacitance value of the storage capacitor is smaller is further improved.

It will be appreciated that in other embodiments, the plurality of pixel electrodes 60 may be located between the first planarization layer 30 and the common electrode 40, the plurality of pixel electrodes 60 may be in contact with the surface of the first planarization layer 30 away from the substrate 10, the planarization layer convex structure 301 may be in contact with the pixel electrode convex structure 601, the planarization layer concave structure 302 may overlap the pixel electrode concave structure 602, the common electrode convex structure 401 may overlap the pixel electrode convex structure 601, and the common electrode concave structure 402 may overlap the pixel electrode concave structure 602.

In this embodiment, as shown in fig. 1 and 2, the pixel electrode convex structure 601 is located at a part of the pixel electrode main body 604, and the pixel electrode convex structure 601 does not overlap the slit 605, so as to avoid that the pixel electrode convex structure 601 overlaps the slit 605 to affect the horizontal component of the electric field formed between the pixel electrode 60 and the common electrode 40, and further affect the transmittance of the display panel to light. Meanwhile, the pixel electrode concave structure 602 overlaps with another portion of the pixel electrode main body 604 in addition to the slit 605, and the other portion of the pixel electrode main body 604 is a portion of the pixel electrode main body 604 other than the pixel electrode convex structure 601.

In the present embodiment, the passivation layer 50 includes the passivation layer concave-convex structure 503, the passivation layer concave-convex structure 503 includes the passivation layer concave structure 502 and the passivation layer convex structure 501, the passivation layer concave structure 502 is overlapped with the common electrode concave structure 402 and the pixel electrode concave structure 602, and the passivation layer convex structure 501 is in contact with both the common electrode convex structure 401 and the pixel electrode convex structure 601.

The passivation layer 50 is an inorganic insulating layer. The passivation layer 50 has a thickness greater than or equal to 800 angstroms and less than or equal to 1500 angstroms.

After the passivation layer 50 is formed on the common electrode 40 and the first planarization layer 30, a passivation layer convex structure 501 is formed on the common electrode convex structure 401, a passivation layer concave structure 502 is formed in the common electrode concave structure 402 and the planarization layer concave structure 302, and the thicknesses of the passivation layer 50 at the positions where the passivation layer concave structure 502 and the passivation layer convex structure 501 are located are the same or tend to be the same.

In the present embodiment, the second planarization layer 70 functions to planarize the array substrate 101. The second planarization layer 70 is disposed on the substrate 10 and is located at a side of the plurality of pixel electrodes 60 and the common electrode 40 away from the substrate 10.

Specifically, the second planarization layer 70 covers the plurality of pixel electrodes 60 and the passivation layer 50, and a surface of the second planarization layer 70 remote from the substrate 10 is a flat surface.

The second planarization layer 70 is an organic layer. The material of the second planarization layer 70 is the same as that of the first planarization layer 30. Specifically, the second planarization layer 70 is made of an organic photoresist.

The thickness of the second planarizing layer 70 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers. The thickness of the second planarization layer 70 at the position of the planarization layer convex structure 301 is smaller than the thickness of the second planarization layer 70 at the position of the planarization layer concave structure 302.

Fig. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the application. The display panel shown in fig. 3 is substantially similar to the display panel shown in fig. 1, except that the surface of the first planarization layer 30 away from the substrate 10 is flat, and the common electrode 40 is disposed on the surface of the flat first planarization layer 30 away from the substrate 10, and the common electrode 40 is also flat or tends to be flat; the passivation layer 50 includes a passivation layer concave-convex structure 503 overlapping with the at least one pixel electrode 60, the passivation layer concave-convex structure 503 including a passivation layer concave structure 502 and a passivation layer convex structure 501, the passivation layer convex structure 501 being in contact with a portion of the pixel electrode main body portion 604 of the at least one pixel electrode 60, the passivation layer concave structure 502 overlapping with the slit of the at least one pixel electrode 60 and another portion of the pixel electrode main body portion 604 of the at least one pixel electrode 60, the other portion of the pixel electrode main body portion 604 being a portion of the pixel electrode 60 not in contact with the passivation layer convex structure 501.

In addition, in the present embodiment, at least one pixel electrode 60 includes a pixel electrode concave-convex structure 603, the pixel electrode concave-convex structure 603 includes a pixel electrode concave structure 602 and a pixel electrode convex structure 601, the pixel electrode concave structure 602 is disposed adjacent to the pixel electrode convex structure 601, the pixel electrode convex structure 601 is in contact with the passivation layer convex structure 501 and is a part of the pixel electrode main body portion 604, and the pixel electrode concave structure 602 overlaps with the passivation layer concave structure 502.

In this embodiment, the thickness of the passivation layer 50 at the location of the passivation layer convex structure 501 is greater than the thickness of the passivation layer 50 at the location of the passivation layer concave structure 502.

Specifically, the thickness of the passivation layer 50 at the location of the passivation layer protruding structure 501 is greater than or equal to 800 angstroms and less than or equal to 1500 angstroms, for example, the thickness of the passivation layer 50 at the location of the passivation layer protruding structure 501 is 800 angstroms, 1000 angstroms, 1200 angstroms, 1300 angstroms, or 1500 angstroms.

The passivation layer 50 has a thickness greater than or equal to 200 angstroms and less than or equal to 1200 angstroms at the location of the passivation layer recessed structure 502, for example, the passivation layer 50 has a thickness of 200 angstroms, 400 angstroms, 600 angstroms, 800 angstroms, 1000 angstroms, or 1200 angstroms at the location of the passivation layer recessed structure 502.

It should be noted that, in this embodiment, the passivation layer 50 is partially thinned by the photolithography process and the etching process to form the passivation layer concave structure 502, the portion of the passivation layer 50 that is not thinned is the passivation layer convex structure 501, the portion of the pixel electrode 60 formed on the passivation layer convex structure 501 corresponds to the pixel electrode convex structure 601, and the portion of the pixel electrode 60 formed in the passivation layer concave structure 502 corresponds to the pixel electrode concave structure 602.

The pixel electrode of the display panel of the embodiment comprises a pixel electrode concave-convex structure, the pixel electrode concave-convex structure increases the area of the pixel electrode, and further increases the opposite area between the pixel electrode and the common electrode, so that the capacitance value of the storage capacitor is increased, and the risk of crosstalk during display of the display panel is reduced.

It will be appreciated that in other embodiments, the pixel electrode 60 may be disposed on a surface of the planar first planarization layer 30 away from the substrate 10, and the pixel electrode 60 may be planar or tend to be planar; the passivation layer 50 covers the pixel electrode 60 and the first planarization layer 30, the passivation layer 50 includes a passivation layer concave-convex structure 503 overlapping with at least one pixel electrode 60, and the passivation layer concave-convex structure 503 includes a passivation layer concave structure 502 and a passivation layer convex structure 501; the common electrode 40 is disposed on the surface of the passivation layer 50 away from the substrate 10, and at this time, the common electrode concave-convex structure 403 includes a common electrode concave structure 402 and a common electrode convex structure 401, the common electrode convex structure 401 is in contact with the passivation layer convex structure 501, and the common electrode concave structure 402 overlaps with the passivation layer concave structure 502.

Fig. 4 is a schematic cross-sectional view of a display device according to an embodiment of the application. The display device 300 is applied to a virtual reality display screen. The display device 300 is a liquid crystal display device, and the display device 300 includes the display panel 100 and the backlight module 200 according to any of the above embodiments, where the display panel 100 is located at the light emitting side of the backlight module 200.

The above description of the embodiments is only for helping to understand the technical solution of the present application and its core ideas; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. An array substrate, characterized in that the array substrate comprises:

a substrate;

The first planarization layer is arranged on the substrate, the surface of the first planarization layer far away from the substrate is provided with a planarization layer concave-convex structure, and the planarization layer concave-convex structure comprises a planarization layer concave structure and a planarization layer convex structure;

The pixel electrodes are arranged on the substrate and are positioned on one side of the first planarization layer away from the substrate, the pixel electrodes comprise pixel electrode main body parts and slits distributed in the pixel electrode main body parts, at least one pixel electrode comprises pixel electrode concave-convex structures, the pixel electrode concave-convex structures comprise pixel electrode concave structures and pixel electrode convex structures which are adjacently arranged, the pixel electrode convex structures are positioned at part of the pixel electrode main body parts, the pixel electrode convex structures are not overlapped with the slits, the pixel electrode concave structures are overlapped with the slits and are also overlapped with the other part of the pixel electrode main body parts, the other part of the pixel electrode main body parts are the parts of the pixel electrode main body parts except the pixel electrode convex structures, the planarization layer concave structures are overlapped with the pixel electrode concave structures, and the planarization layer convex structures are overlapped with the pixel electrode convex structures; and

The common electrode is arranged on the substrate and is positioned on one side, far away from the substrate, of the first planarization layer, is arranged in a stacked mode with the pixel electrodes in the thickness direction of the array substrate, is overlapped with the pixel electrodes and is electrically insulated, and forms a storage capacitor part together with each pixel electrode, the common electrode comprises a common electrode concave-convex structure overlapped with at least one pixel electrode, the common electrode concave-convex structure is adjacently arranged and comprises a common electrode concave structure and a common electrode convex structure, the common electrode concave structure is overlapped with the pixel electrode concave structure, and the common electrode convex structure is overlapped with the pixel electrode convex structure.

2. The array substrate according to claim 1, wherein the common electrode is located between the first planarization layer and the plurality of pixel electrodes in a thickness direction of the array substrate, and the planarization layer convex structure is in contact with the common electrode convex structure; or alternatively, the first and second heat exchangers may be,

3. The array substrate of claim 1, wherein a thickness of the first planarization layer at a position of the planarization layer convex structure is greater than a thickness of the first planarization layer at a position of the planarization layer concave structure.

4. The array substrate of claim 1, wherein the material of the first planarization layer comprises an organic material, and wherein the thickness of the first planarization layer is greater than or equal to 0.5 microns and less than or equal to 3 microns.

5. The array substrate of claim 1, further comprising:

6. The array substrate of claim 1, further comprising:

7. The array substrate of claim 1, further comprising:

8. A display panel, characterized in that it comprises an array substrate according to any one of claims 1-7.