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TW202011514A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW202011514A
TW202011514A TW107145695A TW107145695A TW202011514A TW 202011514 A TW202011514 A TW 202011514A TW 107145695 A TW107145695 A TW 107145695A TW 107145695 A TW107145695 A TW 107145695A TW 202011514 A TW202011514 A TW 202011514A
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semiconductor
semiconductor elements
semiconductor element
semiconductor device
elements
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TW107145695A
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TWI711116B (zh
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譚寶豪
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日商東芝記憶體股份有限公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Die Bonding (AREA)

Abstract

實施形態提供一種具備不良情況更少之新穎構成之半導體裝置及其製造方法。 實施形態之半導體裝置包含：基板，其具有第一面；第一半導體元件，其設置於第一面上；複數個半導體元件，其等以局部覆蓋第一半導體元件之方式設置於第一面；接著層，設置於複數個半導體元件與第一面之間、及複數個半導體元件與第一半導體元件之間，且具有自第一面之正交方向觀察時之周緣部朝向複數個半導體元件之外側方向鼓出之膨脹部；及覆蓋膜，其被覆第一半導體元件及複數個半導體元件。

Description

半導體裝置及其製造方法
本實施形態係關於一種半導體裝置及其製造方法。
先前，已知作為半導體裝置之半導體記憶體，其一體地包含複數個記憶體元件、以及控制資料自該記憶體元件之讀出及資料向記憶體元件之寫入之控制器。
實施形態提供一種具備不良情況更少之新穎構成之半導體裝置及其製造方法。
實施形態之半導體裝置包含：基板，其具有第一面；第一半導體元件，其設置於第一面上；複數個半導體元件，其等以局部覆蓋第一半導體元件之方式設置於第一面；接著層，其設置於複數個半導體元件與第一面之間、及複數個半導體元件與第一半導體元件之間，且具有自第一面之正交方向觀察時之周緣部朝向複數個半導體元件之外側方向鼓出之膨脹部；及覆蓋膜，其被覆第一半導體元件及複數個半導體元件。
[相關申請案] 本申請案享有以日本專利申請2018-170553號(申請日：2019年9月12日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。
以下，揭示導體記憶體之例示性實施形態。以下所示之實施形態之構成及方法(技術特徵)、以及藉由該構成及方法所產生之作用及結果(效果)為一例。又，以下例示之複數個實施形態中包含同樣之構成。因此，各實施形態可基於同樣之構成獲得同樣之作用及效果。再者，以下對該同樣之構成要素標註共通之符號，並省略重複說明。
又，於各圖中，出於方便而記載表示方向之箭頭。方向X、方向Y、及方向Z相互正交。方向X及方向Y為沿基板10之背面10a及正面10b之方向，方向Z為基板10之厚度方向。又，以下，出於方便而將基板10之正面10b所朝向之方向即圖1之上方簡稱為上方，將基板10之背面10a所朝向之方向即圖1之下方簡稱為下方。又，方向X為各圖中之右方向。
[第1實施形態] 圖1係半導體記憶體1A之沿方向Z之剖視圖，圖2係半導體記憶體1A之沿方向Z之相反方向觀察之俯視圖。
如圖1所示，半導體記憶體1A包含基板10、控制器20、記憶體元件30、及覆蓋層40。
基板10為電路基板，例如為印刷電路基板。基板10具有扁平板狀之形狀，且具有相互平行之背面10a及正面10b。背面10a及正面10b均與方向Z交叉，並且與方向Z大致正交。
控制器20控制資料自記憶體元件30之讀出及資料向記憶體元件30之寫入。控制器20亦可執行該讀出及寫入以外之控制。又，控制器20具有扁平之長方體狀之形狀，且具有相互平行之背面20a及正面20b。背面20a及正面20b均與方向Z交叉，並且與方向Z大致正交。
控制器20安裝於基板10之正面10b上。控制器20例如可經由晶粒接合膜51(DAF51)而接著於正面10b上。DAF51介置於正面10b與背面20a之間，將該正面10b與背面20a接著。DAF51亦可稱為接著層。DAF51設置於在控制器20之製造步驟中一體地包含複數個控制器20之區域之晶圓(未圖示)之背面。藉由以切晶將晶圓切斷而分為複數個控制器20，從而使DAF51設置於各控制器20之背面20a。又，控制器20經由接合線21而與基板10之例如配線圖案等導體部(未圖示)電性連接。
記憶體元件30為非揮發性之記憶體，例如為NAND(Not AND，反及)型閃速存儲器。記憶體元件30具有扁平之長方體狀之形狀，且具有相互平行之背面30a及正面30b。背面30a及正面30b均與方向Z交叉，並且於本實施形態中與方向Z大致正交。
兩個記憶體元件30安裝於基板10之正面10b上。兩個記憶體元件30隔開間隙排列於方向X上。兩個記憶體元件30分別經由不同之DAF52接著於正面10b上。DAF52介置於正面10b與背面30a之間，將該正面10b與背面30a接著。又，DAF52亦介置於控制器20之正面20b與背面30a之間，將該正面20b與背面30a接著。DAF52設置於在記憶體元件30之製造步驟中一體地包含複數個記憶體元件30之區域之晶圓(未圖示)之背面。藉由以切晶將晶圓切斷而分為複數個記憶體元件30，從而使DAF52設置於各記憶體元件30之背面30a。又，記憶體元件30分別經由接合線31而與基板10之例如配線圖案等導體部(未圖示)電性連接。
記憶體元件30及DAF52局部覆蓋控制器20。換言之，記憶體元件30及DAF52於方向Z上與控制器20局部重疊。即，記憶體元件30及DAF52覆蓋控制器20之正面20b及基板10之正面10b。如圖1、2所示，沿方向X排列之兩排記憶體元件30之中間位置、亦即兩個記憶體元件30之間之間隙重疊於控制器20之中央部上。
DAF52包含第一部位52a及第二部位52b。第一部位52a係覆蓋控制器20之部位、亦即位於控制器20上之部位。又，第二部位52b係偏離控制器20而覆蓋正面10b之部位、亦即位於正面10b上之部位。如圖1、2所示，於沿方向Z觀察之俯視時，第二部位52b大於第一部位52a。因此，記憶體元件30雖然局部載置於控制器20上，但不易於控制器20上傾斜。
又，如圖1所示，DAF52之周緣部52c分別朝向周圍沿基板10之正面10b向外側鼓出。藉此，於兩個DAF52之邊界部分，作為該等周緣部52c之一部分之邊52c1及邊52c1相互無間隙地相接，覆蓋控制器20。
覆蓋層40設置於基板10之正面10b上，覆蓋該基板10。覆蓋層40及基板10包入控制器20及兩個記憶體元件30。覆蓋層40係藉由絕緣性之合成樹脂材料製造。該合成樹脂材料例如為混合有二氧化矽等無機物之環氧樹脂。覆蓋層40亦可稱為密封樹脂。
圖3A～圖3D表示半導體記憶體1A之製造步驟。首先，如圖3A所示，於基板10之正面10b上安裝控制器20。將控制器20經由DAF51接著於正面10b上。又，實施打線接合，使控制器20經由接合線21與基板10之導體部(未圖示)電性連接。
其次，如圖3B所示，以覆蓋基板10之正面10b及控制器20之正面20b之方式，分別經由不同之DAF52接著兩個記憶體元件30。DAF52載置於正面10b及正面20b上。兩個DAF52隔開間隙g配置於方向X上。
其次，如圖3C所示，將兩個記憶體元件30之正面30b朝向基板10之正面10b、即方向Z之相反方向按壓。藉由該步驟，將兩個DAF52分別以方向Z上之高度變低之方式壓縮，並將兩個DAF52之周緣部52c分別朝向周圍沿基板10之正面10b向外側擠出而使其等鼓出。藉此，於圖3B中，於方向X上相互隔開間隙g對面之兩個DAF52之邊52c1、52c1相互靠近，如圖3C所示般相接。藉此，填滿間隙g，控制器20整體被DAF52覆蓋。於圖3C之狀態下，使DAF51、52固化。
其次，如圖3D所示，於基板10之正面10b上載置覆蓋層40，覆蓋層40覆蓋基板10之正面10b及露出於該正面10b上之兩個記憶體元件30。藉此，藉由基板10及覆蓋層40包入控制器20及兩個記憶體元件30。
如以上說明，於本實施形態中，複數個記憶體元件30係以分別局部覆蓋控制器20之方式，經由DAF52(接著層)接著於基板10之正面10b(第一面)上及控制器20之正面20b上。假設當於控制器20上以覆蓋其整體之方式經由DAF52載置記憶體元件30時，記憶體元件30之背面30a相對於控制器20之正面10b不具有足夠之寬廣度，因此擔心產生記憶體元件30之傾斜，其導致正面10b與DAF52之間產生間隙(空隙)等接著不良，成為良率降低之原因。針對該方面，根據本實施形態，複數個記憶體元件30分別局部覆蓋控制器20，與此相應地，於各記憶體元件30，DAF52可存在於正面10b之更大之區域上。換言之，DAF52中偏離控制器20而位於正面10b上之第二部位52b大於DAF52中位於控制器20上之第一部位52a。因此，記憶體元件30及DAF52雖然載置於控制器20上，但不易傾斜。即，根據本實施形態，例如，獲得可藉由DAF52將正面10b與記憶體元件30精度更加良好地或更加確實地接著之效果。
又，根據本實施形態，複數個記憶體元件30分別經由不同之DAF52接著於正面10b上。假設要藉由一個相對較大之接著層來接著複數個記憶體元件30，那麼會有製造耗費工時且成本增大之顧慮。針對該方面，根據本實施形態，複數個記憶體元件30係分別經由不同之DAF52接著於正面10b上，因此例如與使用一個相對較大之接著層之情形相比，可減少製造之工時且抑制成本。又，DAF52於藉由切晶將晶圓切斷而分為複數個記憶體元件30前，可於複數個記憶體元件30一次性地設置DAF52。即，藉由以切晶將安裝有DAF52之晶圓切斷，可獲得複數個帶DAF52之記憶體元件30。因此，根據本實施形態，例如可進一步減少製造之工時且進一步抑制成本。
又，於本實施形態中，兩個DAF52於控制器20上相互連接。根據此種構成，例如可藉由相同材質之複數個DAF52以無間隙或間隙較小之狀態覆蓋於控制器20上，從而可進一步減少伴隨溫度變化產生之半導體記憶體1A之應變。
又，於本實施形態中，DAF52之周緣部52c朝向外側鼓出，各周緣部52c之邊52c1於控制器20上相互連接。根據此種構成，例如藉由將記憶體元件30朝向基板10之正面10b按壓使其向外側鼓出，可相對容易地獲得不同之DAF52之周緣部52c於控制器20上相互連接之構造、亦即不同之DAF52相互連接之構造。
[第1實施形態之變化例] 圖4係本變化例之半導體記憶體1A1之沿方向Z之相反方向觀察之俯視圖。如圖4所示，本變化例包含四個記憶體元件30。
於本變化例中，於基板10之正面10b上配置有四個記憶體元件30。記憶體元件30分別與上述第1變化例同樣地安裝於正面10b上。
四個記憶體元件30係以呈對角狀且如磁磚般相互隔開間隙排列於方向X及方向Y上，且各記憶體元件30之一個角部30c位於控制器20上之方式配置。即，各記憶體元件30之角部30c與控制器20於方向Z上重疊。於圖4之俯視時，四個記憶體元件30之重心(矩心)與控制器20之中心大致重疊。
而且，於本變化例中，半導體記憶體1A1亦係藉由與圖3A～圖3D同樣之製程製造。因此，四個DAF52之周緣部52c沿基板10之正面10b向外側鼓出，鄰接之周緣部52c相互連接。於控制器20上，於方向X或方向Y上鄰接之兩個DAF52之周緣部52c之邊52c1相互連接，並且四個DAF52之周緣部52c之角52c2相互連接。
如此，於本變化例中，四個DAF52於控制器20上相互連接。因此，根據本變化例，例如亦可藉由相同材質之複數個DAF52而以無間隙或間隙較小之狀態覆蓋於控制器20上，因而不易產生伴隨溫度變化產生之半導體記憶體1A1之應變。
[第2實施形態] 圖5係本實施形態之半導體記憶體1B之沿方向Z之剖視圖。半導體記憶體1B具有與第1實施形態之半導體記憶體1A大致相同之構成，且可藉由同樣之製造步驟製造。但於本實施形態中，不實施圖3C之步驟。因此，DAF52之周緣部52c不向外側鼓出，複數個DAF52之周緣部52c隔開間隙g相互分開。根據此種構成，例如由於未實施圖3C之步驟，與此相應地步驟減少，可使製造之所需時間更短，從而容易提昇半導體記憶體1B之製造之產能。
[第3實施形態] 圖6係本實施形態之半導體記憶體1C之沿方向Z之剖視圖。於本實施形態中，於基板10與記憶體元件30之間介置有虛設基板60。虛設基板60具有扁平之長方體狀之形狀，且具有相互平行之背面60a及正面60b。背面60a及正面60b均與方向Z交叉，並且於本實施形態中與方向Z大致正交。虛設基板60不具有導體部，藉由自未處理之(帶DAF53之)晶圓切斷而製造。虛設基板60亦可稱為介置構件、支持構件、或平衡件。再者，虛設基板60及接著層之製造方法並不限定於此。
虛設基板60例如可經由DAF53接著於正面10b上。DAF53介置於正面10b與背面60a之間，將該正面10b與背面60a接著。又，DAF53亦介置於控制器20之正面20b與背面60a之間，將該正面20b與背面60a接著。DAF53亦可稱為接著層。DAF53設置於一體地包含複數個虛設基板60之區域之未處理之矽晶圓(未圖示)之背面。藉由以切晶將晶圓切斷而分為複數個虛設基板60，從而使DAF53設置於各虛設基板60之背面60a。DAF53為第一接著層之一例。
虛設基板60及DAF53覆蓋控制器20。換言之，虛設基板60及DAF53於方向Z上與控制器20重疊。即，虛設基板60及DAF53覆蓋控制器20之正面20b及基板10之正面10b。如圖6所示，虛設基板60之中央部重疊於控制器20之中央部上。又，虛設基板60及DAF53以跨越控制器20之方式覆蓋控制器20。
DAF53包含第一部位53a及第二部位53b。第一部位53a係位於在方向X即沿正面10b之方向上跨越並覆蓋控制器20之部位、亦即位於控制器20上之部位。又，第二部位53b係偏離控制器20而覆蓋正面10b之部位、亦即位於正面10b上之部位。於沿方向Z觀察之俯視時，第二部位53b大於第一部位53a，並且虛設基板60及DAF53跨越控制器20。因此，虛設基板60雖然載置於控制器20上，但不易傾斜。
兩個記憶體元件30安裝於虛設基板60之正面60b上。於本實施形態中，兩個記憶體元件30亦隔開間隙而排列於方向X上。兩個記憶體元件30分別經由不同之DAF52而接著於正面60b上。DAF52介置於正面60b與背面30a之間，將該正面60b與背面30a接著。又，記憶體元件30分別經由接合線31而與基板10之例如配線圖案等導體部(未圖示)電性連接。又，根據圖6明顯可知，虛設基板60具有可安裝於沿正面60b之方向上隔開間隙排列之複數個記憶體元件30之大小。DAF52為第二接著層之一例。正面60b為第二面之一例。
於以上之本實施形態中，半導體記憶體1C包含虛設基板60(介置構件)。虛設基板60經由DAF53(第一接著層)接著於基板10之正面10b(第一面)上及控制器20之正面20b上，兩個記憶體元件30經由DAF52(第二接著層)接著於虛設基板60之正面60b(第二面)上。於此種構成中，DAF53可存在於較正面10b更大之區域上。換言之，DAF53中偏離控制器20而位於正面10b上之第二部位53b大於DAF53中位於控制器20上之第一部位53a。因此，虛設基板60及DAF53雖然載置於控制器20上，但不易傾斜。即，根據本實施形態，獲得例如可將正面10b與DAF52之間精度更加良好地或更加確實地接著之效果。即，根據本實施形態，獲得例如可將正面10b與記憶體元件30精度更加良好地或更加確實地接著之效果。
以上，例示了本發明之實施形態，但上述實施形態為一例，並非意圖限定發明之範圍。上述實施形態可以其他形態實施，且可於不脫離發明之主旨之範圍內進行各種省略、置換、組合、變更。該等實施形態包含於發明之範圍及主旨中，並且包含於申請專利範圍所記載之發明及與其均等之範圍內。又，亦可替換部分各實施形態之構成及形狀而實施。又，可適當變更各構成及形狀等規格(構造、種類、方向、形式、大小、長度、寬度、厚度、高度、數量、配置、位置、材質等)而實施。例如記憶體元件之數量及配置並不限定於上述實施形態，可進行各種設定。又，複數個記憶體元件亦可積層於厚度方向上。
1A:半導體記憶體 1A1:半導體記憶體 1B:半導體記憶體 1C:半導體記憶體 10:基板 10a:背面 10b:正面 20:控制器 20a:背面 20b:正面 21:接合線 30:記憶體元件 30a:背面 30b:正面 30c:角部 31:接合線 40:覆蓋層 51:DAF(接著層) 52:DAF(接著層、第二接著層) 52a:第一部位 52b:第二部位 52c:周緣部 52c1:邊 52c2:角 53:DAF(接著層、第一接著層) 53a:第一部位 53b:第二部位 60:虛設基板(介置構件) 60a:背面 60b:正面 g:間隙 X:方向 Y:方向 Z:方向
圖1係第1實施形態之半導體記憶體之例示且模式性之剖視圖。 圖2係第1實施形態之半導體記憶體之例示且模式性之俯視圖。 圖3A～3D係表示實施形態之半導體記憶體之製造方法的例示且模式性之剖視圖。 圖4係第1實施形態之變化例之半導體記憶體之例示且模式性之俯視圖。 圖5係第2實施形態之半導體記憶體之例示且模式性之剖視圖。 圖6係第3實施形態之半導體記憶體之例示且模式性之剖視圖。
1A:半導體記憶體
10:基板
10a:背面
10b:正面
20:控制器
20a:背面
20b:正面
21:接合線
30:記憶體元件
30a:背面
30b:正面
31:接合線
40:覆蓋層
51:DAF(接著層)
52:DAF(接著層、第二接著層)
52a:第一部位
52b:第二部位
52c:周緣部
52c1:邊
X:方向
Y:方向
Z:方向

Claims (11)

  1. 一種半導體裝置，其包含： 基板，其具有第一面； 第一半導體元件，其設置於第一面上； 複數個半導體元件，其等以局部覆蓋上述第一半導體元件之方式設置於上述第一面； 接著層，其設置於上述複數個半導體元件與上述第一面之間、及上述複數個半導體元件與上述第一半導體元件之間，且具有自上述第一面之正交方向觀察時之周緣部朝向上述複數個半導體元件之外側方向鼓出之膨脹部；及 覆蓋膜，其被覆上述第一半導體元件及上述複數個半導體元件。
  2. 一種半導體裝置，其包含： 基板，其具有第一面； 第一半導體元件，其設置於第一面上； 第二接著層，其設置於上述第一半導體元件之上； 介置構件，其設置於上述第二接著層之上； 複數個半導體元件，其等設置於和上述介置構件之與接觸上述第二接著層之面為相反側之面； 接著層，其設置於上述複數個半導體元件與上述介置構件之間，且具有自上述第一面之正交方向觀察時周緣部朝向上述複數個半導體元件之外側方向鼓出之膨脹部；及 覆蓋膜，其被覆上述複數個半導體元件及上述複數個半導體元件。
  3. 如請求項1或2之半導體裝置，其中上述複數個半導體元件係分別介隔不同之接著層而設置。
  4. 如請求項3之半導體裝置，其中上述不同之接著層之上述膨脹部於自上述第一面之正交方向觀察時之上述第一半導體元件上相互無間隙地物理接觸。
  5. 如請求項3之半導體裝置，其中上述不同之接著層之上述膨脹部於自上述第一面之正交方向觀察時之上述第一半導體元件上相互分開。
  6. 如請求項4之半導體裝置，其中上述第一半導體元件為控制器，且 上述複數個半導體元件為記憶體晶片。
  7. 如請求項4之半導體裝置，其中上述複數個半導體元件之數量為4個。
  8. 一種半導體裝置之製造方法，其包含如下步驟： 於基板之第一面上設置第一半導體元件； 以自上述第一面之正交方向觀察時分別局部覆蓋上述第一半導體元件之方式，介隔不同之接著層將複數個半導體元件設置於上述第一面上； 將複數個半導體元件朝向上述第一面按壓，使自上述第一面之正交方向觀察時之上述不同之接著劑之周緣部向外側鼓出形成膨脹部；及 形成被覆上述複數個半導體元件之覆蓋膜。
  9. 一種半導體裝置之製造方法，其包含如下步驟： 於基板之第一面上設置第一半導體元件； 於上述第一半導體元件之上設置第二接著層； 於上述第二接著層之上設置介置構件； 於上述介置構件之與接觸上述第二接著層之面為相反側之面，以自上述第一面之正交方向觀察時分別局部覆蓋上述第一半導體元件之方式，介隔不同之接著層而設置上述複數個半導體元件； 將複數個半導體元件朝向上述第一面按壓，自上述第一面之正交方向觀察時，使上述不同之接著劑之周緣部向外側鼓出形成膨脹部；及 形成被覆上述複數個半導體元件之覆蓋膜。
  10. 如請求項8或9之半導體裝置之製造方法，其中以使上述膨脹部於自上述第一面之正交方向觀察時之上述第一半導體元件上相互無間隙地物理接觸之方式進行按壓。
  11. 如請求項10之半導體裝置之製造方法，其中於形成有半導體器件之晶圓貼附接著層，並藉由切晶將該晶圓連同接著層分斷，藉此形成上述複數個半導體元件。
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Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW459361B (en) * 2000-07-17 2001-10-11 Siliconware Precision Industries Co Ltd Three-dimensional multiple stacked-die packaging structure
JP3913481B2 (ja) * 2001-01-24 2007-05-09 シャープ株式会社 半導体装置および半導体装置の製造方法
SG104291A1 (en) * 2001-12-08 2004-06-21 Micron Technology Inc Die package
TWI237354B (en) * 2002-01-31 2005-08-01 Advanced Semiconductor Eng Stacked package structure
JP2003273317A (ja) * 2002-03-19 2003-09-26 Nec Electronics Corp 半導体装置及びその製造方法
TWI249796B (en) * 2004-11-08 2006-02-21 Siliconware Precision Industries Co Ltd Semiconductor device having flip chip package
KR100593703B1 (ko) * 2004-12-10 2006-06-30 삼성전자주식회사 돌출부 와이어 본딩 구조 보강용 더미 칩을 포함하는반도체 칩 적층 패키지
TWM385089U (en) * 2007-01-30 2010-07-21 Powertech Technology Inc Multi-chip stack device with no need of spacer disposition
US8399973B2 (en) * 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
TWI382506B (zh) * 2009-09-24 2013-01-11 Powertech Technology Inc 中央銲墊型晶片之主動面朝上堆疊方法與構造
JP2011155144A (ja) * 2010-01-27 2011-08-11 Toshiba Corp 半導体装置
JP2012129464A (ja) 2010-12-17 2012-07-05 Toshiba Corp 半導体装置およびその製造方法
JP2012216644A (ja) 2011-03-31 2012-11-08 Toshiba Corp 半導体装置及びその製造方法
US8823165B2 (en) * 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
WO2013012435A1 (en) 2011-07-18 2013-01-24 Hewlett-Packard Development Company, L.P. Security parameter zeroization
US8436457B2 (en) * 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8653646B2 (en) * 2011-10-03 2014-02-18 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
KR101906408B1 (ko) * 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP2013098240A (ja) 2011-10-28 2013-05-20 Toshiba Corp 記憶装置、半導体装置及び半導体装置の製造方法
KR101896665B1 (ko) * 2012-01-11 2018-09-07 삼성전자주식회사 반도체 패키지
JP5918664B2 (ja) 2012-09-10 2016-05-18 株式会社東芝 積層型半導体装置の製造方法
KR20140109134A (ko) * 2013-03-05 2014-09-15 삼성전자주식회사 멀티-채널을 갖는 반도체 패키지 및 관련된 전자 장치
US9087846B2 (en) * 2013-03-13 2015-07-21 Apple Inc. Systems and methods for high-speed, low-profile memory packages and pinout designs
KR102108087B1 (ko) * 2013-07-11 2020-05-08 삼성전자주식회사 반도체 패키지
JP6074357B2 (ja) * 2013-12-24 2017-02-01 日東電工株式会社 接着フィルム、ダイシング・ダイボンドフィルム、半導体装置の製造方法及び半導体装置
JP2016063015A (ja) * 2014-09-17 2016-04-25 株式会社東芝 半導体装置
JP6427473B2 (ja) 2015-09-08 2018-11-21 富士フイルム株式会社 有機半導体膜形成用組成物、有機半導体膜およびその製造方法、並びに有機半導体素子
JP6373811B2 (ja) 2015-09-08 2018-08-15 東芝メモリ株式会社 半導体装置の製造方法および製造装置
KR102592640B1 (ko) * 2016-11-04 2023-10-23 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US10340250B2 (en) * 2017-08-15 2019-07-02 Kingpak Technology Inc. Stack type sensor package structure

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