TW202001863A - Gate driving apparatus - Google Patents

Abstract

A gate driving apparatus includes a plurality of shift register circuits. In the shift register circuit, an output stage circuit receives a control signal and provides a gate low or high voltage in accordance with the control signal to charge the output to generate a gate drive signal. A compensation circuit includes first and second transistors and first and second capacitors. A first voltage regulator according to a mode selection signal to provide the low or high gate voltage to adjust the control signal. A second voltage regulator according to a switching signal and a reverse clock signal to provide a pre-drive signal or a start pulse signal to adjust the control signal. A third voltage regulator according to the mode selection signal and the control signal to provide the low or high gate voltage to adjust the control signal. A fourth voltage regulator adjusts the control signal according to the reverse clock signal.

Description

Gate drive

The invention relates to a gate driving device, and in particular to a gate driving device of a display device.

In recent years, many products have integrated the gate driver circuit (Gate driver) in the display driver circuit on the glass, which is the gate-driver-on-array (GOA) circuit. The gate drive circuit on the array has many advantages. It can reduce the width of the frame of the display panel to achieve the effect of a narrow frame, thereby effectively reducing the design area of the internal circuit of the display.

In the display device, since the display screen presented by the display panel is easily affected by the turn-on voltage of the driving transistor in the pixel circuit, the quality of the display screen is reduced. Therefore, the gate driving circuit needs to make the pixel switches of the same column be turned on or off at the same time in the compensation stage to perform compensation operation on the driving transistor. Next, the gate drive circuit needs to turn on the pixel switches row by row during the data writing stage to write the drawing voltage (or pixel data) to the corresponding pixel circuit.

In other words, how to effectively generate a consistent gate drive signal when the gate drive device is operating in the compensation stage, and to sequentially generate the gate drive signals during the data writing stage to improve gate drive The performance of the device will be an important issue for those skilled in the art.

The invention provides a gate drive device, which can enable each gate drive signal at the same time in the compensation phase, and enable each gate drive signal in sequence during the write phase, thereby enhancing the gate drive device efficacy.

The gate driving device of the present invention has multiple shift temporary storage circuits. A plurality of shift register circuits are coupled in series with each other to generate a plurality of gate drive signals, wherein the shift register circuit of the Nth stage includes an output stage circuit, a compensation circuit, and first to fourth voltage regulators. The output stage circuit has a first control terminal and a second control terminal to receive the first control signal and the second control signal, respectively, according to the first control signal and the second control signal to provide the gate low voltage or the gate high voltage to the output terminal Charge to generate the Nth gate drive signal. The compensation circuit is coupled between the first control terminal and the output stage circuit. The compensation circuit includes first and second transistors and first and second capacitors. The first terminal of the first transistor receives the clock signal, and the control terminal of the first transistor is coupled to the first control terminal. The first terminal of the second transistor is coupled to the second terminal of the first transistor, the second terminal of the second transistor is coupled to the first node, and the control terminal of the second transistor receives the switching signal. The first capacitor is coupled between the first control terminal and the first node. The second capacitor is coupled between the first node and the output terminal. The first voltage regulator is coupled to the first control terminal, and provides a gate low voltage or a gate high voltage according to the first mode selection signal and the second mode selection signal to adjust the first control signal. The second voltage regulator is coupled to the first control terminal, and provides a previous-stage gate driving signal or a starting pulse signal according to the switching signal and the reverse clock signal to adjust the first control signal. The third voltage regulator is coupled between the first control terminal and the second control terminal, and provides the gate low voltage or the gate high voltage according to the second mode selection signal and the first control signal to adjust the second control signal. The fourth voltage regulator is coupled to the second control terminal and adjusts the second control signal according to the reverse clock signal.

Based on the above, the shift temporary storage circuit of the gate driving device of the present invention can synchronize the output of the gate driving signal generated by the output stage circuit with the gate driving signals of the front and rear stages during the compensation stage. In the writing stage, the gate driving signal generated by the output stage circuit and the front and rear stage gate driving signals are output in order, thereby improving the performance of the gate driving device.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

The term "coupling (or connection)" used in the entire specification of this case (including the scope of patent application) may refer to any direct or indirect connection means. For example, if it is described that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to another device or a certain device. Connection means indirectly connected to the second device. In addition, wherever possible, elements/components/steps using the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numbers or use the same terminology in different embodiments may refer to related descriptions with each other.

Please refer to FIG. 1, which is a schematic diagram of a gate driving device according to an embodiment of the present invention. Wherein, the gate driving device includes a plurality of shift temporary storage circuits coupled in series, and generates a plurality of gate driving signals respectively. Taking the shift register circuit 100 of the Nth stage as an example, the shift register circuit 100 includes an output stage circuit 110, a compensation circuit 120, and a plurality of voltage regulators 130-160. The output stage circuit 110 has a control terminal CT1 and a control terminal CT2. The control terminal CT1 and the control terminal CT2 can receive the control signal CS1 and the control signal CS2, respectively. The output stage circuit 110 provides the gate low voltage VGL or the gate high voltage VGH to charge the output terminal OUT according to the control signal CS1 and the control signal CS2, thereby generating the gate drive signal G[N] of the Nth stage.

In this embodiment, the output stage circuit 110 includes transistors M1, M2. The first terminal of the transistor M1 receives the gate low voltage VGL, the second terminal of the transistor M1 is coupled to the output terminal OUT, and the control terminal of the transistor M1 is coupled to the control terminal CT1. The first terminal of the transistor M2 is coupled to the output terminal OUT, the second terminal of the transistor M2 receives the gate high voltage VGH, and the control terminal of the transistor M2 is coupled to the control terminal CT2.

The compensation circuit 120 is coupled between the control terminal CT1 and the output stage circuit 110. In this embodiment, the compensation circuit 120 includes transistors M3 and M4, capacitors C1 and C2. The first end of the transistor M3 receives the clock signal CLK, and the control end of the transistor M3 is coupled to the control end CT1. The first end of the transistor M4 is coupled to the second end of the transistor M3, the second end of the transistor M4 is coupled to the node P1, and the control end of the transistor M4 receives the switching signal CHA. In addition, the capacitor C1 is coupled between the control terminal CT1 and the node P1. The capacitor C2 is coupled between the node P1 and the output terminal OUT.

On the other hand, the voltage regulator 130 is coupled to the control terminal CT1. The voltage regulator 130 can decide to provide the gate low voltage VGL or the gate high voltage VGH to the control terminal CT1 according to the mode selection signal SS1 and the mode selection signal SS2, so that the voltage regulator 130 can pass the gate low voltage VGL or the gate High voltage VGH to adjust the control signal CS1.

In this embodiment, the voltage regulator 130 includes transistors M5, M6, and M7. The first terminal of the transistor M5 receives the gate low voltage VGL, the second terminal of the transistor M5 is coupled to the control terminal CT1, and the control terminal of the transistor M5 receives the mode selection signal SS1. The transistor M6 and the transistor M7 are connected in series with each other. The transistor M6 receives the gate high voltage VGH and is controlled by the mode selection signal SS2 and is connected to the control terminal CT1 through the transistor M7. The transistor M7 is coupled to the control terminal CT1 and is controlled by the mode selection signal SS2. It is worth mentioning that the transistor M7 in FIG. 1 can be omitted. The illustration in FIG. 1 is only an illustrative example, and is not intended to limit the scope of the present invention.

The voltage regulator 140 is coupled to the control terminal CT1. The voltage regulator 140 can decide to provide the previous-stage gate drive signal G[N-1] or the start pulse signal ST to the control terminal CT1 according to the switching signal CHA and the reverse clock signal XCLK, so that the voltage regulator 140 can The control signal CS1 is adjusted by the previous-stage gate drive signal G[N-1] or the start pulse signal ST.

In this embodiment, the voltage regulator 140 includes a transistor M8 and a transistor M9. The transistor M8 and the transistor M9 are connected in series with each other, wherein the transistor M8 receives the previous-stage gate drive signal G[N-1] or the start pulse signal ST and is controlled by the reverse clock signal XCLK. The transistor M9 is coupled to the control terminal CT1 and is controlled by the switching signal CHA.

In particular, in this embodiment, when the shift register circuit 100 operates in the compensation stage, the voltage regulator 140 can turn off the transistor M9 according to the switching signal CHA with a high voltage level. In this way, during the compensation phase, the shift register circuit 100 can effectively isolate the influence between the previous-stage gate drive signal G[N-1] or the start pulse signal ST and the control signal CS1, thereby reducing the synchronization The influence of the gate drive signal G[N] output by the output stage circuit 110 on the previous-stage gate drive signal G[N-1] or the start pulse signal ST.

On the other hand, the voltage regulator 150 is coupled between the control terminal CT1 and the control terminal CT2. The voltage regulator 150 can decide to provide the gate low voltage VGL or the gate high voltage VGH to the control terminal CT2 according to the mode selection signal SS2 and the control signal CS1, so that the voltage regulator 150 can pass the gate low voltage VGL or the gate high Voltage VGH to adjust the control signal CS2.

In this embodiment, the voltage regulator 150 includes transistors M10-M13. The first terminal of the transistor M10 receives the gate low voltage VGL, the second terminal of the transistor M10 is coupled to the control terminal CT2, and the control terminal of the transistor M10 receives the mode selection signal SS2. The first terminal of the transistor M11 is coupled to the control terminal CT2, the second terminal of the transistor M11 receives the gate high voltage VGH, and the control terminal of the transistor M11 receives the control signal CS1. The first terminal of the transistor M12 is coupled to the control terminal CT1, and the control terminal of the transistor M12 is coupled to the control terminal CT2. The first terminal of the transistor M13 is coupled to the second terminal of the transistor M12, the second terminal of the transistor M13 receives the gate high voltage VGH, and the control terminal of the transistor M13 is coupled to the control terminal CT2.

The voltage regulator 160 is coupled to the control terminal CT2. The voltage regulator 160 can adjust the control signal CS2 according to the reverse clock signal XCLK. In this embodiment, the voltage regulator 160 includes a transistor M14 and a transistor M15. The first end of the transistor M14 and the control end jointly receive the reverse clock signal XCLK. The first terminal of the transistor M15 is coupled to the second terminal of the transistor M14. The second terminal of the transistor M15 is coupled to the control terminal CT2. The control terminal of the transistor M15 receives the reverse clock signal XCLK.

It is worth mentioning that the transistor M14 and the transistor M15 of this embodiment can form a diode according to the connection mode of the diode configuration (Diode Connection). Wherein, the cathode of the diode (ie the first end of the transistor M14) receives the reverse clock signal XCLK, and the anode of the diode (ie the second end of the transistor M15) is coupled to the control端CT2. Incidentally, the transistors M1 to M15 of this embodiment are P-type transistors as an example, but the embodiments of the present invention are not limited thereto. In some embodiments, one of transistors M14 or M15 may be omitted. For example, the transistor M14 can be omitted, and the first end and the control end of the transistor M15 receive the reverse clock signal XCLK, and the second end is coupled to the control end CT2.

For details of the operation of the shift register circuit 100, please refer to FIG. 2 and FIGS. 3A to 3F at the same time. FIG. 2 is a waveform diagram of the gate driving device according to an embodiment of the present invention, and FIGS. 3A to 3F are according to the present invention. An equivalent circuit diagram of the shift register circuit of the embodiment.

Referring to FIG. 2, in this embodiment, one pixel period TFR of the shift register circuit 100 can be divided into a compensation stage TC, a writing stage TR, and a voltage holding stage TVH, and a compensation stage TC, a writing stage TR and TVH does not overlap each other in the voltage holding phase. Wherein, the writing phase TR is enabled after the compensation phase TC, and the voltage holding phase TVH is enabled after the writing phase TR.

Please refer to FIG. 2 and FIG. 3A at the same time. Specifically, when the shift register circuit 100 operates in the first sub-stage TC_1 of the compensation stage TC, a clock generator (not shown) externally connected to the shift register circuit 100 The clock signal CLK with a high voltage level and the reverse clock signal XCLK with a low voltage level can be provided to the shift register circuit 100. In addition, the shift register circuit 100 can set the mode selection signal SS1 to a low voltage level state, and set the mode selection signal SS2 and the switching signal CHA to be both high voltage level states.

In detail, the voltage regulator 130 can transmit the gate low voltage VGL to the control terminal CT1 according to the mode selection signal SS1, thereby pulling down the voltage level of the control signal CS1 and simultaneously turning on the transistor M3. Moreover, the transistor M4 and the transistor M9 can be turned off according to the switching signal CHA. In this case, the voltage regulator 140 cannot transmit the previous-stage gate driving signal G[N-1] or the start pulse signal ST to the control terminal CT1. In this way, this embodiment can effectively isolate the influence between the previous-stage gate drive signal G[N-1] or the start pulse signal ST and the control signal CS1.

On the other hand, in the first sub-stage TC_1, the voltage regulator 160 may be turned on according to the reverse clock signal XCLK, and charge the control signal CS2. Then, the voltage regulator 150 can transmit the gate high voltage VGH to the control terminal CT2 according to the pulled-down control signal CS1, and then pull the control signal CS2 to the voltage level of the gate high voltage VGH.

In other words, in the first sub-stage TC_1, the output stage circuit 110 can provide the gate low voltage VGL according to the pulled-down control signal CS1 to charge the output terminal OUT, and the output stage circuit 110 can pass through the output terminal OUT Accordingly, the gate driving signal G[N] having the voltage level of the gate low voltage VGL is generated correspondingly.

Next, please refer to FIGS. 2 and 3B at the same time. Specifically, when the shift register circuit 100 operates in the second sub-stage TC_2 of the compensation stage TC, the shift register circuit 100 can set the mode selection signal SS1, mode selection Both the signal SS2 and the switching signal CHA are in a high voltage level state. In addition, an external clock generator (not shown) can provide the clock signal CLK and the reverse clock signal XCLK that periodically change state to the shift register circuit 100.

In detail, the voltage regulator 130 can be turned off according to the mode selection signal SS1 and the mode selection signal SS2, and the transistor M4 and the transistor M9 can be continuously turned off according to the switching signal CHA. In addition, the transistor M3 can be continuously turned on according to the pulled-down control signal CS1. It is worth mentioning that in the second sub-stage TC_2, the compensation circuit 120 can be based on the control terminal CT1 and the node P1 being in a floating state, and by the coupling effect of the capacitor C1 and the capacitor C2, the voltage of the control signal CS1 The level is adjusted to the sum of the voltage value of the gate low voltage VGL and a voltage value V1. In addition, the voltage level on the node P1 is also adjusted synchronously to the voltage difference between the voltage value of the gate low voltage VGL and an offset value ΔV after coupling effect. The voltage value V1 may be expressed as a voltage difference between the on-voltage |VTH5| of the transistor M5 and the offset value ΔV after the coupling effect. That is, the voltage level of the control signal CS1 at this time is VGL+V1=VGL+|VTH5|-ΔV, and the voltage level of the node P1 at this time is VGL-ΔV.

On the other hand, the voltage regulator 160 is periodically turned off according to the reverse clock signal XCLK. Moreover, the voltage regulator 150 can provide the gate high voltage VGH to the control terminal CT2 according to the pulled-down control signal CS1, so that the voltage level of the control signal CS2 can be maintained at the voltage value of the gate high voltage VGH.

In other words, in the second sub-stage TC_2, the output stage circuit 110 can provide the gate low voltage VGL according to the pulled-down control signal CS1 to charge the output terminal OUT, and the output stage circuit 110 can pass through the output terminal OUT Accordingly, the gate driving signal G[N] having the voltage level of the gate low voltage VGL is generated correspondingly.

Next, please refer to FIGS. 2 and 3C at the same time. Specifically, when the shift register circuit 100 operates in the third sub-stage TC_3 of the compensation stage TC, the shift register circuit 100 can set the mode selection signal SS1 and the switching signal CHA is continuously maintained in the high voltage level state, and the mode selection signal SS2 is set to the low voltage level state. In addition, an external clock generator (not shown) can provide a clock signal CLK with a high voltage level and a reverse clock signal XCLK with a low voltage level.

In detail, the voltage regulator 130 can provide the gate high voltage VGH to the control terminal CT1 according to the mode selection signal SS2, so that the voltage level of the control signal CS1 can be pulled up to the voltage value of the gate high voltage VGH. At the same time, the transistor M3 and the transistor M4 in the compensation circuit 120 can be disconnected respectively according to the control signal CS1 and the switching signal CHA being pulled down, and the voltage regulator 140 can be continuously disconnected according to the switching signal CHA open.

On the other hand, the voltage regulator 160 can be turned on according to the reverse clock signal XCLK to charge the control signal CS2. Then, the voltage regulator 150 can provide the gate low voltage VGL to the control terminal CT2 according to the mode selection signal SS2, so that the voltage level of the control signal CS2 is adjusted to the voltage value of the gate low voltage VGL and a voltage value V2 sum. Wherein, the voltage value V2 can be expressed as the on-voltage |VTH10| of the transistor M10. That is, the voltage level of the control signal CS2 at this time is VGL+ V2=VGL+|VTH10|.

In other words, in the third sub-stage TC_3, the output stage circuit 110 can provide the gate high voltage VGH according to the pulled-down control signal CS2 to charge the output terminal OUT, and the output stage circuit 110 can pass through the output terminal OUT Accordingly, the gate driving signal G[N] having the voltage level of the gate high voltage VGH is correspondingly generated.

According to the above descriptions of FIGS. 3A to 3C, it can be clearly seen that in the compensation stage TC, the shift register circuit 100 can open the front gate by setting the switching signal CHA to a high voltage level state. The drive signal G[N-1] is transmitted to the path of the control terminal CT1, so that the gate drive signal G[N] will not be affected by the previous gate drive signal G[N-1], and the gate drive The signal G[N] can be output in synchronization with the subsequent gate driving signal G[N+1], thereby improving the performance of the display gate driving device.

Please refer to FIGS. 2 and 3D at the same time. Specifically, when the shift register circuit 100 operates in the first sub-stage TR_1 of the writing stage TR, the shift register circuit 100 can set the mode selection signal SS1 and the mode selection signal SS2 is in a high voltage level state, and the switching signal CHA is set to a low voltage level state. In addition, an external clock generator (not shown) can provide a clock signal CLK with a high voltage level and a reverse clock signal XCLK with a low voltage level to the shift register circuit 100.

In detail, the voltage regulator 130 can be turned off according to the mode selection signal SS1 and the mode selection signal SS2. In addition, the transistor M3 and the transistor M4 in the voltage regulator 120 can be turned on according to the pulled-down control signal CS1 and the switching signal CHA, respectively. Unlike the compensation stage TC, in the writing stage TR, the voltage regulator 140 can be turned on according to the switching signal CHA and the reverse clock signal XCLK.

In this case, the voltage regulator 140 can transmit the previous-stage gate drive signal G[N-1] or the start pulse signal ST to the control terminal CT1, so that the voltage level of the control signal CS1 can be pulled down to the gate The sum of the voltage value of the very low voltage VGL and a voltage value V3. Wherein, the voltage value V3 can be expressed as the on-voltage |VTH8| of the transistor M8. That is, the voltage level of the control signal CS1 at this time is VGL+V3=VGL+|VTH8|. It should be noted that since the transistor M3 and the transistor M4 are both on at this time, the node P1 can pass through the conduction path formed by the transistor M3 and the transistor M4 and synchronize according to the pulled-up clock signal CLK Is pulled up to the voltage level of the gate high voltage VGH.

On the other hand, in the first sub-stage TR_1, the voltage regulator 160 can be continuously turned on according to the pulled-down reverse clock signal XCLK, and continuously charge the control signal CS2. Then, the voltage regulator 150 can transmit the gate high voltage VGH to the control terminal CT2 according to the pulled-down control signal CS1, so that the voltage level of the control signal CS2 can be pulled up to the voltage value of the gate high voltage VGH.

In other words, in the first sub-stage TR_1, the output stage circuit 110 can correspondingly generate the gate driving signal G[N] according to the pulled-down control signal CS1. The voltage level of the gate drive signal G[N] at this time is the sum of the voltage value of the gate low voltage VGL and a voltage value V4. Wherein, the voltage value V4 can be expressed as the on-voltage |VTH8| of the transistor M8 and the on-voltage |VTH1| of the transistor M1. That is, the voltage level of the gate drive signal G[N] at this time is VGL+V4=VGL+|VTH8|+|VTH1|.

Please refer to FIGS. 2 and 3E at the same time. Specifically, when the shift register circuit 100 operates in the second sub-stage TR_2 of the writing stage TR, the shift register circuit 100 can set the mode selection signal SS1 and the mode selection signal SS2 continues to maintain a high voltage level state, and sets the switching signal CHA to a low voltage level state. In addition, an external clock generator (not shown) can provide a clock signal CLK with a low voltage level and a reverse clock signal XCLK with a high voltage level to the shift register circuit 100.

In detail, the voltage regulator 130 can be continuously disconnected according to the mode selection signal SS1 and the mode selection signal SS2, and the voltage regulator 140 can be disconnected again according to the inverted clock signal XCLK being pulled high. Then, the transistor M3 and the transistor M4 of the compensation circuit 120 can be turned on according to the pulled-down control signal CS1 and the switching signal CHA, respectively.

It is worth mentioning that in the second sub-stage TR_2, the compensation circuit 120 can pull the voltage level of the node P1 synchronously to the voltage value of the gate low voltage VGL and a value according to the pulled down clock signal CLK The sum of the voltage value V5. Wherein, the voltage value V5 can be expressed as the on-voltage |VTH3| of the transistor M3. That is, the voltage level of the node P1 at this time is VGL+|VTH3|. Then, the compensation circuit 120 can adjust the voltage level of the gate low voltage VGL and a voltage synchronously through the coupling effect of the capacitor C1 according to the voltage level of the node P1 being pulled down The sum of the values V6. The voltage value V6 may be expressed as a voltage difference between the on-voltage |VTH8| of the transistor M8 and the offset value ΔV after the coupling effect. That is, the voltage level of the control signal CS1 at this time is VGL+V6=VGL+|VTH8|-△V.

On the other hand, the voltage regulator 160 can be turned off again according to the pulled up reverse clock signal XCLK. Next, the voltage regulator 150 can provide the gate high voltage VGH to the control terminal CT2 according to the pulled-down control signal CS1, so that the voltage level of the control signal CS2 is maintained at the voltage value of the gate high voltage VGH.

In other words, in the second sub-stage TR_2, the output stage circuit 110 can provide the gate low voltage VGL according to the pulled-down control signal CS1 to charge the output terminal OUT, and the output stage circuit 110 can pass through the output terminal OUT Accordingly, the gate driving signal G[N] having the voltage level of the gate low voltage VGL is generated correspondingly.

Please refer to FIG. 2 and FIG. 3F at the same time. Specifically, when the shift register circuit 100 operates in the voltage holding stage TVH, the shift register circuit 100 can set the mode selection signal SS1 and the mode selection signal SS2 to continue to the high voltage level. Bit state, and set the switching signal to continue to the low voltage level state. In addition, an external clock generator (not shown) can provide the clock signal CLK and the reverse clock signal XCLK that are periodically switched to the shift register circuit 100.

In detail, the voltage regulator 130 can remain off according to the mode selection signal SS1 and the mode selection signal SS2. At the same time, the voltage regulator 140 can be periodically turned on according to the reverse clock signal XCLK, and periodically charge the control signal CS1 to pull the control signal CS1 high. Then, the transistor M3 of the voltage regulator 120 can be turned off again according to the pulled-up control signal CS1.

On the other hand, the voltage regulator 160 can be periodically turned on according to the reverse clock signal XCLK, and periodically charge the control signal CS2 to lower the voltage level of the control signal CS2.

In other words, in the voltage holding stage TVH, the output stage circuit 110 can provide the gate low voltage VGH according to the pulled-down control signal CS2 to charge the output terminal OUT, and make the output stage circuit 110 correspond through the output terminal OUT Generates a gate drive signal G[N] with a voltage level of the gate high voltage VGH.

It should be noted that the above-mentioned high voltage level may be the voltage value of the gate high voltage VGH, and the low voltage level may be the voltage value of the gate low voltage VGL.

According to the above descriptions of FIG. 3D to FIG. 3F, it can be clearly seen that in the writing stage TR, the shift register circuit 100 can make the control signal CS1 be pulled down synchronously through the coupling effect of the capacitor C1, thereby enabling The gate driving signal G[N] and the subsequent-stage gate driving signal G[N+1] can be output in sequence, thereby improving the performance of the gate driving device.

In summary, the shift temporary storage circuit of the gate driving device of the present invention can output the gate driving signal generated by the output stage circuit and the gate driving signals of the front and rear stages in synchronization during the compensation stage. In the writing stage, the gate driving signal generated by the output stage circuit and the front and rear stage gate driving signals are output in order, thereby improving the performance of the gate driving device.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100‧‧‧ Shift temporary storage circuit 110‧‧‧ Output stage circuit 120‧‧‧ Compensation circuit 130～160‧‧‧Voltage regulator CT1～CT2‧Control terminal CS1～CS2‧‧‧‧Control signal CHA‧‧ ‧Switching signal C1, C2 ‧‧‧Capacitance G[N-1]～G[N+1]‧‧‧Gate drive signal M1～M15 ‧‧‧Transistor OUT‧‧‧Output terminal P1‧‧‧VGL ‧‧‧Gate low voltage VGH‧‧‧Gate high voltage SS1～SS2 ‧‧‧ Mode selection signal ST‧‧‧Start pulse signal TFR‧‧‧Pixel period TC‧‧‧Compensation stage TR‧‧‧ Write phase TVH‧‧‧voltage hold phase TC_1～TC_3, TR_1～TR_2‧‧‧subphase V1～V6‧‧‧voltage value XCLK‧‧‧reverse clock signal CLK‧‧‧clock signal

FIG. 1 is a schematic diagram of a gate driving device according to an embodiment of the invention. 2 is a waveform diagram of a gate driving device according to an embodiment of the invention. 3A to 3F are equivalent circuit diagrams of a shift register circuit according to an embodiment of the invention.

100‧‧‧shift temporary storage circuit

110‧‧‧ output stage circuit

120‧‧‧Compensation circuit

130~160‧‧‧Voltage regulator

CT1~CT2‧‧‧Control terminal

CS1~CS2‧‧‧Control signal

CHA‧‧‧switch signal

C1, C2‧‧‧Capacitance

G[N-1], G[N]‧‧‧ gate drive signal

M1~M15‧‧‧Transistor

OUT‧‧‧Output

VGL‧‧‧gate low voltage

VGH‧‧‧gate high voltage

SS1~SS2‧‧‧Mode selection signal

ST‧‧‧Start pulse signal

XCLK‧‧‧Reverse clock signal

CLK‧‧‧clock signal

Claims (17)

A gate drive device includes: a plurality of shift register circuits, which are coupled in series to each other, and generate a plurality of gate drive signals, wherein the shift register circuit of the Nth stage includes: a The output stage circuit has a first control terminal and a second control terminal to receive a first control signal and a second control signal respectively, and to provide a gate low voltage according to the first control signal and the second control signal Or a gate high voltage charges an output terminal to generate an Nth gate drive signal; a compensation circuit coupled between the first control terminal and the output stage circuit, wherein the compensation circuit includes: a first A transistor, the first end of which receives a clock signal, the control end of the first transistor is coupled to the first control end; a second transistor, the first end of which is coupled to the first end of the first transistor Two ends, the second end of the second transistor is coupled to a first node, the control end of the second transistor receives a switching signal; a first capacitor is coupled to the first control end and the first Between nodes; and a second capacitor, coupled between the first node and the output terminal; a first voltage regulator, coupled to the first control terminal, according to a first mode selection signal and a first Two mode selection signals to provide the gate low voltage or the gate high voltage to adjust the first control signal; a second voltage regulator, coupled to the first control terminal, based on the switching signal and a reverse time Pulse signal to provide a previous gate drive signal or a starting pulse signal to adjust the first control signal; a third voltage regulator, coupled between the first control terminal and the second control terminal, according to The second mode selection signal and the first control signal to provide the gate low voltage or the gate high voltage to adjust the second control signal; and a fourth voltage regulator, coupled to the second control terminal, The second control signal is adjusted according to the reverse clock signal. The gate drive device as described in item 1 of the patent application, wherein in a compensation stage, the second voltage regulator is cut off according to the switching signal, and the first voltage regulator is provided according to the first mode selection signal The gate low voltage pulls down the first control signal. The gate drive device as described in item 2 of the patent application scope, wherein in the compensation stage, the fourth voltage regulator is turned on according to the reverse clock signal, and the third voltage regulator is based on the first control signal The high voltage of the gate is provided to pull up the second control signal. The gate drive device as described in item 3 of the patent application range, wherein in the compensation stage, the output stage circuit provides the gate low voltage according to the first control signal to charge the output terminal, and generates the Nth Level gate drive signal. The gate drive device as described in item 2 of the patent application scope, wherein the first voltage regulator is turned off according to the first mode selection signal and the second mode selection signal in a first sub-stage of a writing stage On, the second voltage regulator is turned on according to the switching signal and the inverted clock signal pulled down to transmit the previous-stage gate drive signal or the starting pulse signal to pull down the first control signal. The gate drive device as claimed in item 5 of the patent application range, wherein in the first sub-stage of the writing stage, the fourth voltage regulator is turned on according to the reverse clock signal, and the third voltage regulator The device provides the gate high voltage according to the first control signal to pull up the second control signal. The gate drive device as described in item 5 of the patent application range, wherein in a second sub-stage of the writing stage, the second voltage regulator is cut off according to the reverse clock signal being pulled up, The first control signal is pulled down by an offset value according to the clock signal being pulled down. The gate drive device as described in item 7 of the patent application scope, wherein the output stage circuit provides the gate low voltage according to the first control signal to charge the output terminal, and generates the Nth gate drive signal . The gate drive device according to item 2 of the patent application scope, wherein in a voltage holding stage, the second voltage regulator is periodically turned on according to the reverse clock signal, and periodically responds to the first control signal During charging, the first voltage regulator remains cut off, the fourth voltage regulator is periodically turned on according to the reverse clock signal, and periodically charges the second control signal. The gate drive device as claimed in item 9 of the patent application range, wherein in the voltage holding stage, the output stage circuit provides the gate high voltage according to the second control signal to generate the Nth gate drive signal. The gate driving device as described in item 1 of the patent application range, wherein the output stage circuit includes: a third transistor whose first end receives the low voltage of the gate, and the second end of the third transistor is coupled To the output end, the control end of the third transistor receives the first control signal; and a fourth transistor, the first end of which is coupled to the output end, and the second end of the fourth transistor receives the gate Very high voltage, the control terminal of the fourth transistor receives the second control signal. The gate drive device as described in item 1 of the patent application range, wherein the first voltage regulator includes: a third transistor whose first end receives the low voltage of the gate and the second end of the third transistor Coupled to the first control terminal, the control terminal of the third transistor receives the first mode selection signal; and at least a fourth transistor, coupled between the first control terminal and the gate high voltage, The control terminal of the at least one fourth transistor receives the second mode selection signal. The gate drive device as described in item 1 of the patent application, wherein the second voltage regulator includes: a third transistor whose first end receives the previous-stage gate drive signal or the starting pulse signal, The control terminal of the third transistor receives the reverse clock signal; and a fourth transistor, the first terminal of which is coupled to the second terminal of the second transistor, and the second terminal of the fourth transistor Connected to the first control terminal, the control terminal of the fourth transistor receives the switching signal. The gate drive device according to item 1 of the patent application scope, wherein the third voltage regulator includes: a third transistor whose first terminal receives the low voltage of the gate electrode and a second terminal of the third transistor Coupled to the second control terminal, the control terminal of the third transistor receives the second mode selection signal; a fourth transistor, the first terminal of which is coupled to the second control terminal, the fourth transistor The second terminal receives the gate high voltage, the control terminal of the fourth transistor receives the first control signal; a fifth transistor, the first terminal of which is coupled to the first control terminal, the fifth transistor The control terminal is coupled to the second control terminal; and a sixth transistor having a first terminal coupled to the second terminal of the fifth transistor, the second terminal of the sixth transistor receiving the gate high voltage The control terminal of the sixth transistor is coupled to the second control terminal. The gate drive device as described in item 1 of the patent application scope, wherein the fourth voltage regulator includes: a diode whose cathode receives the reverse clock signal and whose anode is coupled to the second control terminal. The gate drive device according to item 15 of the patent application scope, wherein the diode includes: a third transistor whose first end and control end receive the reverse clock signal; and a fourth transistor, The first terminal is coupled to the second terminal of the third transistor, the second terminal of the fourth transistor is coupled to the second control terminal, and the control terminal of the fourth transistor receives the reverse clock signal . The gate drive device as described in item 1 of the patent application scope, wherein the gate drive signals are simultaneously enabled during a compensation phase, and the gate drive signals are sequentially enabled during a write phase, In a voltage holding phase, the gate drive signals are kept at the disabled voltage value, wherein the compensation phase, the writing phase, and the voltage holding phase occur in sequence.

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