TW202001849A - Gate driving apparatus - Google Patents

Abstract

A gate driving apparatus includes a plurality of shift register circuits. The shift register circuits are coupled in series, and a Nth stage shift register circuit includes an output stage circuit and a plurality of voltage adjuster. The output stage circuit generates a Nth stage gate driving signal at an output end according to a first control signal, a second control signal, and a third control signal. A first voltage adjuster adjusts the first control signal according to a first and second mode selection signals. A second voltage adjuster adjusts the second control signal according to a prior stage gate driving signal, a rear stage gate driving signal, an inverted clock signal or the third control signal. A third voltage adjuster adjusts the third control signal according to the first mode selection signal, the second control signal and a clock signal.

Description

Gate drive

The invention relates to a gate driving device, and in particular to a gate driving device for driving a display panel.

In an active light-emitting diode pixel circuit that emits light synchronously, all pixels need to be turned on at the same time in the compensation stage, so that the variation of the on-voltage of the thin film transistor in the pixel can be compensated at the same time. In the next data access stage, you need to turn on the pixel circuits row by row to write data to the pixel circuits row by row.

In the conventional technical field, pixel circuits that emit light synchronously often face various problems. First, a special signal needs to be set in the pixel circuit that emits light synchronously to indicate the progress of the compensation stage and the data access stage; second, when applied to a high-resolution display panel, a sufficiently long data writing time is required; Third, when the thin-film transistors manufactured by the low-temperature polysilicon process are used in the gate drive circuit, when the thin-film transistors are disconnected, they still have a relatively high electron mobility and are likely to cause leakage at the circuit nodes .

The invention provides a gate driving device, which can be applied to a high-resolution display panel.

The gate driving device of the present invention includes a plurality of shift temporary storage circuits. The shift register circuits are coupled in series with each other and generate a plurality of gate drive signals, wherein the shift register circuit of the Nth stage includes an output stage circuit, a first voltage regulator, a second voltage regulator, and a third voltage Adjuster. The output stage circuit has a first control terminal, a second control terminal, and a third control terminal to receive the first control signal, the second control signal, and the third control signal, respectively. The output stage circuit generates the N-th gate driving signal at the output terminal according to the first control signal, the second control signal, and the third control signal. The first voltage regulator is coupled to the first control terminal, and selects the gate high voltage or the gate low voltage according to the first mode selection signal and the second mode selection signal to adjust the first control signal. The second voltage regulator is coupled to the second control terminal, provides a clock signal according to the previous gate drive signal to adjust the second control signal, and provides the gate high according to the rear gate drive signal or the third control signal The voltage adjusts the second control signal, and adjusts the second control signal according to the reverse clock signal. The third voltage regulator is coupled to the third control terminal, and adjusts the third control signal according to the first mode selection signal, the second control signal, and the clock signal.

Based on the above, the gate driving device of the present invention adjusts the control signal on the control terminal through a plurality of voltage regulators, and controls the output stage circuit by the control signal to generate the gate driving signal. In this way, the gate driver can generate a plurality of gate driving signals having a uniform waveform in the compensation stage, and generate a plurality of gate driving signals that are sequentially enabled in the subsequent writing stage.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

Please refer to FIG. 1, which is a schematic diagram of a gate driving device according to an embodiment of the invention. The gate drive device includes a plurality of shift temporary storage circuits, wherein the gate drive device is constructed by the shift temporary storage circuits coupled to each other in series. Taking the Nth stage shift register circuit 100 as an example, the Nth stage shift register circuit 100 includes an output stage circuit 110, a first voltage regulator 120, a second voltage regulator 130, and a third voltage regulator 140 . The output stage circuit 110 has a first control terminal CE1, a second control terminal CE2, and a third control terminal CE3. The first control terminal CE1, the second control terminal CE2 and the third control terminal CE3 respectively receive the first control signal S _[N] , the second control signal Q _[N] and the third control signal P _[N] . The output stage circuit 110 according to the first control signal S _[N], the second control signal Q _[N] and a third control signal P _[N] to produce the N-th stage output terminal OE at the gate driving signal G _[N].

In this embodiment, the output stage circuit 110 includes transistors T4, T5, T11, and T13. The first terminal of the transistor T4 receives the gate low voltage V _GL , the second terminal of the transistor T4 is coupled to the output terminal OE, and the control terminal of the transistor T4 receives the second control signal Q _[N] . The first terminal of the transistor T5 receives the gate low voltage V _GL , the second terminal of the transistor T5 is coupled to the output terminal OE, and the control terminal of the transistor T5 receives the first control signal S _[N] . Transistors T13 and T11 are coupled in series with each other, wherein the first end of transistor T13 and the first end of transistor T11 are coupled to each other, the first end of transistor T11 receives the gate high voltage V _GH , the first end of transistor T13 The two terminals are coupled to the output terminal OE, and the control terminals of the transistors T13 and T11 jointly receive the third control signal P _[N] . In other embodiments of the present invention, the transistors T11 and T13 can be changed to a single transistor or two or more transistors connected in series to each other. The illustration in FIG. 1 is only an illustrative example, not to limit the invention Category. Through multiple transistors connected in series, the leakage phenomenon in the circuit node can be reduced.

The voltage regulator 120 is coupled to the first control terminal CE1. The voltage regulator 120 selects the gate low voltage V _GL or the gate high voltage V _GH according to the mode selection signal SS and the mode selection signal SR to adjust the first control signal S _[N] . In this embodiment, the voltage regulator 120 includes transistors T6 and T12 and a capacitor C2. The first terminal of the transistor T6 receives the gate low voltage V _GL , the second terminal of the transistor T6 is coupled to the first control terminal CE1, and generates a first control signal S _[N] , the control terminal of the transistor T6 receives the mode Select signal SS. The first end of the transistor T12 is coupled to the second end of the transistor T6, the second end of the transistor T12 receives the gate high voltage V _GH , and the control end of the transistor T12 receives the mode selection signal SR. The capacitor C2 is coupled between the output terminal OE and the first control terminal CE1.

The voltage regulator 130 is coupled to the second control terminal CE2. The voltage regulator 130 provides a clock signal CK to adjust the second control signal Q _[N] according to the previous second control signal Q _{[N-1 ]} . The voltage regulator 130 adjusts the second control signal Q _[N] according to the subsequent gate drive signal G _[N+2] or the third control signal P _[N] to provide the gate high voltage V _GH , and according to the reverse The clock signal XCK adjusts the second control signal Q _[N] .

In this embodiment, the voltage regulator 130 includes transistors T1, T2, T3, T10 and a capacitor C1. Transistor T1 is coupled into a diode configuration. The control end and the first end form a cathode of the diode and receive the clock signal CK. The second end of the transistor T1 forms the anode of the diode and is coupled Connect to the first end of transistor T2. The second terminal of the transistor T2 is coupled to the second control terminal CE2, and the control terminal of the transistor T2 receives the second control signal Q _{[N-1] of the} previous stage. One end of the capacitor C1 receives the reverse clock signal XCK, and the other end thereof is coupled to the second control terminal CE2. The first terminal of the transistor T3 is coupled to the second control terminal CE2, the second terminal of the transistor T3 receives the gate high voltage V _GH , and the control terminal of the transistor T3 receives the subsequent gate drive signal G _[N+2] . In addition, the first terminal of the transistor T10 is coupled to the second control terminal CE2, the second terminal of the transistor T10 receives the gate high voltage V _GH , and the control terminal of the transistor T10 receives the third control signal P _[N] .

The voltage regulator 140 is coupled to the third control terminal CE3. The voltage regulator 140 adjusts the third control signal P _[N] according to the mode selection signal SS, the second control signal Q _[N] and the clock signal CK.

In this embodiment, the voltage regulator 140 includes transistors T7, T8, and T9. The transistor T8 is coupled between the third control terminal CE3 and the gate high voltage V _GH . The control terminal of the transistor T8 receives the second control signal Q _[N] . The transistor T9 is coupled between the third control terminal CE3 and the gate high voltage V _GH . The control terminal of the transistor T9 receives the mode selection signal SS. The transistor T7 is coupled in a diode configuration, the control section and the first end are coupled together to form a cathode to receive the clock signal CK, and the anode formed at the second end thereof is coupled to the third control end CE3.

For details of the operation of the gate driving device according to the embodiment of the present invention, please refer to FIG. 2 and FIGS. 3A to 3G at the same time, wherein FIG. 2 illustrates the operation waveform diagram of the gate driving device according to the embodiment of the present invention, and FIG. 3A to FIG. 3G shows an equivalent circuit diagram of the gate driving device according to an embodiment of the invention.

Please refer to FIG. 2 and FIG. 3A first. In the initial time interval TA0, the mode selection signals SS and SR are the high voltage level (equal to the gate high voltage V _GH ) and the low voltage level (equal to the gate low voltage V _GL ), while the clock signal CK and the reverse The clock signal XCK is a low voltage level (equal to the gate low voltage V _GL ) and a high voltage level (equal to the gate high voltage V _GH ).

At this time, the transistor T12 is turned on, and makes the voltage value of the first control signal S _[N] equal to the gate high voltage V _GH . The transistor T7 is turned on, so that the third control signal P _[N] is the gate low voltage V _GL . Corresponding to the third control signal P _[N] of the gate low voltage V _GL , the transistors T10, T11, T13 are turned on and cause the second control signal Q _[N] and the Nth gate drive signal G _[N] The voltage values are the gate high voltage V _GH .

On the other hand, in the time interval TA0, the transistors T2 to T6 and T8 to T9 are turned off.

2 and 3B, in the time interval TA1, the gate driving device enters the compensation stage. In the compensation phase, the mode selection signals SS and SR are respectively transitioned to the gate low voltage V _GL and the gate high voltage V _GH . In the voltage regulator 120, the transistor T6 is turned on (the transistor T12 is turned off), and the first control signal S _[N] is pulled low. Corresponding to this, the transistor T5 in the output stage circuit 110 is turned on and pulls down the Nth gate drive signal G _[N] to the gate low voltage V _GL , and this pull-down action passes through the coupling effect of the capacitor C2, The voltage value of the first control signal S _[N] is further pulled down to be equal to V _GL -DV. Among them, DV is an offset value, and its magnitude is related to the coupling rate provided by the capacitor C2.

It is worth mentioning that, in the gate driving device, based on the mode selection signal SS equal to the gate low voltage V _GL , all the shift register circuits can simultaneously generate the gate driving signal equal to the gate low voltage V _GL , so In the time interval TA1, the gate drive signal G _[N-1] , the gate drive signal G _[N], and the gate drive signal G _{[N+2] of the} rear stage are all equal to the gate low voltage V _GL .

On the other hand, based on the mode selection signal SS being the gate low voltage V _GL , the transistor T9 in the voltage regulator 140 is turned on, and the third control signal P[N] is pulled up to the logic high level V _GH And the transistor T10 in the voltage regulator 140 and the transistors T11 and T13 in the output stage circuit 110 are turned off. However, based on the subsequent gate drive signal G _[N+2] being equal to the gate low voltage V _GL , the transistor T3 in the voltage regulator 140 is turned on, and the second control signal Q _{[N] is} maintained at the gate high voltage V _GH .

2 and FIG. 3C, in the time interval TA2, the compensation phase of the gate drive device ends, and it is ready to enter the write phase. In the time interval TA2, the mode selection signals SS and SR are respectively transitioned to the gate high voltage V _GH and the gate low voltage V _GL , the transistor T12 in the voltage regulator 120 is turned on (the transistor T6 is turned off), The first control signal S _[N] is pulled up to the gate high voltage V _GH . Based on the mode selection signal SS being the gate high voltage V _GH , the transistor T9 in the voltage regulator 140 is turned off. Under the condition that the clock signal CK is at a low voltage level, the transistor T7 in the voltage regulator 140 is turned on, and the third control signal P _[N] is pulled up to the gate high voltage V _GH . At the same time, the transistor T10 in the voltage regulator 130 is turned on, and the second control signal Q _{[N] is} maintained at the gate high voltage V _GH (at this time, the transistor T3 is in the off state).

Then, in the time interval TA3, the gate driving device is ready to enter the data writing stage. In the time interval TA3, the voltage values of the previous-stage second control signal Q _[N-1] and the previous-stage gate drive signal G _[N-1] fall to be equal to V _GL +|V _{TH_T1} | and V _GL +| V _{TH_T1} |+|V _{TH_T4} |. Wherein V _{TH_T1} and V _{TH_T4} are the turn-on voltages of the transistors T1 and T4 in the previous-stage shift temporary storage circuit, respectively.

2 and 3D below, in the time interval TA4, the gate driving device enters the first sub-stage of the data writing stage. In the time interval TA4, the previous-stage second control signal Q _[N-1] further drops to be equal to V _GL +|V _{TH_T1} |-DV1, and the transistor T2 in the voltage regulator 130 is turned on. DV1 is an offset value. And when the clock signal CK is equal to the gate low voltage V _GL , the transistor T1 is turned on at the same time, and the second control signal Q _{[N] is} pulled down to V _GL +|V _{TH_T1} |. On the other hand, based on the condition that the second control signal Q _[N] is pulled low, the transistor T8 in the voltage regulator 140 is turned on correspondingly, and the third control signal P _[N] is pulled high to It is equal to V _GH -DV2, where the offset value DV2 is caused by the transistor T8 not being fully turned on. Moreover, corresponding to the third control signal P _[N] being pulled high and the second control signal Q _{[N] being} pulled low, the transistor T4 in the output stage circuit 110 is turned on, and the transistors T11 and T13 are turned off. The gate drive signal G _{[N] of} the Nth stage is correspondingly pulled down to be equal to V _GL +|V _{TH_T1} |+|V _{TH_T4} |.

2 and 3E, in the time interval TA5, the gate driving device enters the second sub-stage of the data writing stage. In the time interval TA5, the reverse clock signal XCK transitions from the gate high voltage V _GH to the gate low voltage V _GL , and through the coupling effect of the capacitor C1 in the voltage regulator 130, the second control signal Q _{[ N]} pulls down an offset value DV1 and makes the voltage value of the second control signal Q _[N] equal to V _GL +|V _{TH_T1} |-DV1. The magnitude of the offset value DV1 is related to the coupling rate of the capacitor C1. With the second control signal Q _[N] further pulled down, the transistor T4 in the output stage circuit 110 can be fully turned on, and the gate drive circuit G _{[N] of} the Nth stage can be completely pulled down to be equal to the gate Very low voltage V _GL . On the other hand, the transistor T8 can be fully turned on, and the third control signal P _[N] is pulled up to the gate high voltage V _GH .

It is worth mentioning that in the waveform diagram of FIG. 2, the second control signal Q _[N-1] in the previous stage is equivalent to the signal that the second control signal Q _{[N] is} advanced by a period of half a clock signal CK. The first-stage gate drive signal G _{[N-1] is} equivalent to the gate drive signal G _[N] a signal earlier by a period of half a clock signal CK, and the later-stage gate drive signal G _{[N+2] is} equivalent to the gate The drive signal G _{[N] is} delayed by one cycle of the clock signal CK.

2 and 3F, in the time interval TA6, the gate drive device enters the voltage holding stage. In the time interval TA6, the late gate drive signal G _[N+2] is pulled down (to V _GL +|V _{TH_T1} |+|V _{TH_T4} |), and the transistor T3 in the voltage regulator 130 is turned off Turn on. The transistor T3 transmits the gate high voltage V _GH to pull up the second control signal Q _[N] , and causes the transistor T4 in the output stage circuit 110 to be turned off. At the same time, the transistor T8 in the voltage regulator 140 is turned off, and the transistor T7 is turned on according to the clock signal CK. Through the transistor T7 being turned on, the third control signal P _{[N] is} pulled down to V _GL +|V _{TH_T7} |, where V _{TH_T7} is the turn-on voltage of the transistor T7.

Based on the third control signal P _[N] being pulled low, the transistors T11, T13 in the output stage circuit 110 are turned on, and the Nth-stage gate drive signal G _[N] is pulled up to the gate high voltage _VGH .

2 and 3G below, in the time interval TA7, the subsequent gate drive signal G _[N+2] is pulled down to the gate low voltage V _GL and the transistor T3 in the voltage regulator 130 is turned on. And the clock signal CK transitions to the gate high voltage V _GH , and the transistor T7 in the voltage regulator 140 is turned off.

After the time interval TA7, the subsequent gate drive signal G _[N+2] is pulled up to the gate high voltage V _GH , and the transistor T3 in the voltage regulator 130 is turned off.

It is worth mentioning that after the time interval TA7, the transistor T7 in the voltage regulator 140 can be periodically turned on through the clock signal CK that periodically transitions to the gate low voltage V _GL , and the third control The signal P[N] is maintained at the gate low voltage V _GL . The gate drive signal G _{[N] of} the Nth stage can be continuously charged and keep equal to the gate high voltage V _GH , which is the disabled voltage value.

In summary, the present invention generates gate drive signals by controlling multiple control signals through multiple voltage regulators. The gate driver provided by the present invention can provide a plurality of gate driving signals that are commonly enabled in the compensation stage, and generate gate driving signals that are sequentially enabled in the writing stage to provide a long enough time to perform data writing action. It can be effectively matched with the display panel of synchronous active organic light-emitting diode, and applied to the display panel with high resolution. In addition, in the embodiment of the present invention, the voltage regulator is constructed through a plurality of transistors connected in series, which can reduce the leakage phenomenon of internal nodes and save power consumption.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100‧‧‧shift temporary storage circuit CE1, CE2‧‧‧ control terminal 110‧‧‧ output stage circuit 120~140‧‧‧ voltage regulator S[N], Q[N], P[N]‧‧‧ Control signal OE‧‧‧Output terminals T1~T13‧‧‧Transistor VGL‧‧‧Gate low voltage VGH‧‧‧Gate high voltage SS, SR‧‧‧ Mode selection signal C1, C2‧‧‧Capacitance XCK‧ ‧‧Reverse clock signal CK‧‧‧Clock signal G[N]‧‧‧Nth stage gate drive signal Q[N-1]‧‧‧Previous stage second control signal G[N-1]‧ ‧‧Front gate drive signal G[N+2]‧‧‧Post-stage gate drive signal TA0~TA7‧‧‧‧Interval

FIG. 1 is a schematic diagram of a gate driving device according to an embodiment of the invention. FIG. 2 illustrates an operation waveform diagram of the gate driving device according to an embodiment of the invention. 3A to 3G illustrate equivalent circuit diagrams of the gate driving device according to an embodiment of the invention.

100‧‧‧shift temporary storage circuit

CE1, CE2, CE3 ‧‧‧ control end

110‧‧‧ output stage circuit

120~140‧‧‧Voltage regulator

S _[N] , Q _[N] , P _[N] ‧‧‧ control signal

OE‧‧‧Output

T1~T13‧‧‧Transistor

V _GL ‧‧‧ gate low voltage

V _GH ‧‧‧ gate high voltage

SS, SR‧‧‧ Mode selection signal

C1, C2‧‧‧Capacitance

XCK‧‧‧Reverse clock signal

CK‧‧‧clock signal

G _[N] ‧‧‧ Nth gate drive signal

Q _[N-1] ‧‧‧Previous second control signal

G _[N+2] ‧‧‧Gate drive signal

Claims (16)

A gate driving device includes: a plurality of shift temporary storage circuits, the shift temporary storage circuits are coupled in series with each other, and respectively generate a plurality of gate drive signals, wherein the shift temporary storage circuit of the Nth stage includes: An output stage circuit has a first control end, a second control end, and a third control end to receive a first control signal, a second control signal, and a third control signal, respectively. The output stage circuit is based on the The first control signal, the second control signal, and the third control signal generate an N-th gate drive signal at an output terminal; a first voltage regulator, coupled to the first control terminal, is based on a first A mode selection signal and a second mode selection signal to select a gate low voltage or a gate high voltage to adjust the first control signal; a second voltage regulator, coupled to the second control terminal, according to a front The second control signal of the second stage is used to provide a clock signal to adjust the second control signal, to provide the high gate voltage to adjust the second control signal according to a subsequent gate drive signal or the third control signal, and to adjust the second control signal according to a Adjust the second control signal by reverse clock signal; and a third voltage regulator, coupled to the third control terminal, adjust according to the first mode selection signal, the second control signal and the clock signal The third control signal. The gate driving device as described in item 1 of the patent application scope, wherein the first voltage regulator provides the gate low voltage to pull down the first control signal according to the first mode selection signal in a compensation stage, the The second voltage regulator provides the gate high voltage according to the subsequent gate drive signal to pull up the second control signal, and the third voltage regulator provides the gate high voltage according to the first mode selection signal Raise the third control signal. The gate driving device as described in item 2 of the patent application scope, wherein in the compensation stage, the output stage circuit transmits the low gate voltage to the output terminal according to the first control signal to generate the Nth gate Drive signal. The gate driving device as described in item 3 of the patent application scope, wherein in a first sub-stage of a writing stage, the first voltage regulator provides the gate high voltage according to the second mode selection signal to pull When the first control signal is high, the second voltage regulator provides the clock signal to pull down the second control signal according to the previous gate drive signal, and the third voltage regulator pulls down according to the clock signal The third control signal. The gate drive device as described in item 4 of the patent application scope, wherein the output stage circuit is based on the first control signal, the second control signal and the third control signal in the first sub-stage of a writing stage To lower the voltage value of the N-th gate drive signal. The gate driving device as described in item 5 of the patent application range, wherein in a second sub-stage of the writing stage, the second voltage regulator pulls the second control signal down according to the reverse clock signal Offset value. The gate drive device as described in item 6 of the patent application range, wherein in the first sub-stage of the writing stage, the voltage value of the reverse clock signal is equal to the high voltage of the gate, in the writing stage In the second sub-stage, the voltage value of the reverse clock signal is equal to the gate low voltage. The gate drive device as claimed in item 6 of the patent application range, wherein in the second sub-stage of the writing stage, the output stage circuit makes the voltage value of the N-th gate drive signal according to the second control signal Pulled down to equal the gate low voltage. The gate driving device as described in item 6 of the patent application scope, wherein in a voltage holding stage, the first voltage regulator provides the gate high voltage according to the second mode selection signal to pull up the first control signal , The second voltage regulator provides the gate high voltage to pull up the second control signal according to the subsequent gate drive signal and the third control signal, and the third voltage regulator pulls according to the clock signal Lower the third control signal. The gate drive device as claimed in item 9 of the patent application range, wherein in the voltage holding stage, the output stage circuit provides the gate high voltage according to the third control signal to maintain the Nth gate drive signal Voltage value. The gate drive device as described in item 10 of the patent application range, wherein the compensation stage, the first sub-stage of the writing stage, the second sub-stage of the writing stage, and the voltage holding stage occur in sequence. The gate drive device as described in item 1 of the patent application scope, wherein the first voltage regulator includes: a first transistor whose first terminal receives the low voltage of the gate electrode and a second terminal of the first transistor Coupled to the first control terminal and generating the first control signal, the control terminal of the first transistor receives the first mode selection signal; a second transistor, the first terminal of which is coupled to the first circuit The second terminal of the crystal, the second terminal of the second transistor receives the gate high voltage, the control terminal of the second transistor receives the second mode selection signal; and a capacitor coupled to the output terminal and the Between the first control terminal. The gate drive device as described in item 1 of the patent application scope, wherein the second voltage regulator comprises: a diode whose cathode receives the clock signal; a first transistor coupled to the diode Between the anode and the second control terminal, the control terminal receives the pre-stage second control signal; a second transistor, the first terminal of which receives the gate high voltage, and the second terminal of the second transistor is coupled To the second control terminal, the control terminal of the second transistor receives the latter-stage gate drive signal; a capacitor, one end of which receives the reverse clock signal, and the other end of which is coupled to the second control terminal; and A third transistor has a first terminal coupled to the second control terminal, a second terminal of the third transistor receives the gate high voltage, and a control terminal of the third transistor receives the third control signal. The gate drive device as described in item 1 of the patent application scope, wherein the third voltage regulator includes: a first transistor coupled between the third control terminal and the gate high voltage, the first power The control terminal of the crystal receives the second control signal; a second transistor coupled between the third control terminal and the gate high voltage, the control terminal of the second transistor receives the first mode selection signal; and A diode whose anode is coupled to the third control terminal and whose cathode receives the clock signal. The gate drive device according to item 1 of the patent application scope, wherein the output stage circuit includes: a first transistor whose first end receives the low voltage of the gate, and a second end of the first transistor is coupled To the output end, the control end of the first transistor receives the second control signal; a second transistor, the first end of which receives the gate low voltage, and the second end of the second transistor is coupled to the At the output end, the control end of the second transistor receives the first control signal; and at least one third transistor, the first end of which receives the gate high voltage, and the second end of the at least one third transistor is coupled To the output terminal, the control terminal of the at least one third transistor receives the third control signal. The gate drive device as described in item 1 of the patent application scope, wherein the gate drive signals are simultaneously enabled during a compensation phase, and the gate drive signals are sequentially enabled during a write phase, In a voltage holding phase, the gate drive signals are kept at the disabled voltage value.

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