TW202001839A - Gate driving apparatus - Google Patents

Abstract

A gate driving apparatus includes a plurality of shift register circuits. A Nth stage shift register circuit includes an output stage circuit, a first voltage adjuster, a second voltage adjuster, a third voltage adjuster and a fourth voltage adjuster. The output stage circuit provides a clock signal or a first mode selection signal to generate a Nth stage gate driving signal according to a first control signal and a second control signal. The first voltage adjuster adjusts the first control according to a second mode selection signal. The second voltage adjuster adjusts the first control signal according to a switching signal and an inverted clock signal. The third voltage adjuster adjusts the second control signal according to the first control signal. The fourth voltage adjuster adjusts the second control signal according to the inverted clock signal.

Description

Gate drive

The invention relates to a gate driving device, and in particular to a gate driving device for driving a display panel.

In an active light-emitting diode pixel circuit that emits light synchronously, all pixels need to be turned on at the same time in the compensation stage, so that the variation of the on-voltage of the thin film transistor in the pixel can be compensated at the same time. In the next data access stage, you need to turn on the pixel circuits row by row to write data to the pixel circuits row by row.

In the conventional technical field, pixel circuits that emit light synchronously often face various problems. First, a special signal needs to be set in the pixel circuit that emits light synchronously to indicate the progress of the compensation stage and the data access stage; second, when applied to a high-resolution display panel, a sufficiently long data writing time is required; Third, when the thin-film transistors manufactured by the low-temperature polysilicon process are used in the gate drive circuit, when the thin-film transistors are disconnected, they can still have a relatively high electron mobility and easily cause leakage at the circuit nodes phenomenon.

The invention provides a gate driving device, which can be applied to a high-resolution display panel.

The gate driving device of the present invention includes a plurality of shift temporary storage circuits. The shift register circuits are coupled in series with each other and generate a plurality of gate drive signals, wherein the shift register circuit of the Nth stage includes an output stage circuit, a first voltage regulator, a second voltage regulator, and a third voltage The regulator and the fourth voltage regulator. The output stage circuit has a first control terminal and a second control terminal to receive the first control signal and the second control signal, respectively. The output stage circuit charges the output terminal according to the first control signal and the second control signal to provide a clock signal or a first mode selection signal to generate an N-th gate drive signal. The first voltage regulator is coupled to the first control terminal and provides the gate high voltage according to the second mode selection signal to adjust the first control signal. The second voltage regulator is coupled to the first control terminal, and provides a previous-stage gate driving signal or a starting pulse signal according to the switching signal and the reverse clock signal to adjust the first control signal. The third voltage regulator is coupled to the second control terminal and provides the gate high voltage according to the first control signal to adjust the second control signal. The fourth voltage regulator is coupled to the first control terminal and adjusts the second control signal according to the reverse clock signal.

Based on the above, the gate driving device of the present invention adjusts the control signal on the control terminal through a plurality of voltage regulators, and controls the output stage circuit by the control signal to generate the gate driving signal. In this way, the gate driver can generate a plurality of gate driving signals having a uniform waveform in the compensation stage, and generate a plurality of gate driving signals that are sequentially enabled in the subsequent writing stage.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

Referring first to FIG. 1, FIG. 1 is a schematic diagram of a gate driving device according to an embodiment of the present invention. Wherein, the gate driving device includes a plurality of shift temporary storage circuits coupled in series, and generates a plurality of gate driving signals respectively. Taking the shift register circuit 100 of the Nth stage as an example, the shift register circuit 100 includes an output stage circuit 110 and a plurality of voltage regulators 120-150. The output stage circuit 110 has a first control terminal CE1 and a second control terminal CE2. The first control terminal CE1 and the second control terminal CE2 receive the first control signal Q _[N] and the second control signal P _{[N], respectively} . The output stage circuit 110 provides the clock signal CK or the mode selection signal SS2 according to the first control signal Q _[N] and the second control signal P _[N] to charge the output terminal OE, and thereby generates the Nth gate drive signal G _[N] .

In this embodiment, the output stage circuit 110 includes transistors T5, T10, capacitors C1 and C2. The first terminal of the transistor T5 receives the clock signal CK, the second terminal of the transistor T5 is coupled to the output terminal OE, and the control terminal of the transistor T5 is coupled to the first control terminal CE1. The first terminal of the transistor T10 is coupled to the output terminal OE, the second terminal of the transistor T10 receives the mode selection signal SS2, and the control terminal of the transistor T10 is coupled to the second control terminal CE2. In addition, the capacitor C1 is connected in series between the control terminal of the transistor T5 and the output terminal OE, and the capacitor C2 is connected in series between the control terminal of the transistor T10 and the output terminal OE.

The voltage regulator 120 is coupled to the first control terminal CE1. The voltage regulator 120 provides the gate high voltage V _GH according to the mode selection signal SS1 to adjust the first control signal Q _[N] , wherein, when the mode selection signal SS1 is at the low voltage level, the voltage regulator 120 can provide the gate The high voltage V _GH pulls up the voltage value of the first control signal Q _[N] . In this embodiment, the mode selection signals SS1 and SS2 are used to indicate that the shift register circuit 100 is operating in the compensation stage or the writing stage.

In this embodiment, the voltage regulator 120 includes transistors T3 and T4, which are serially connected in series between the first control terminal CE1 and the gate high voltage V _GH . The control terminals of the transistors T3 and T4 jointly receive the mode selection signal SS1.

In other embodiments of the present invention, the voltage regulator 120 may include only a single transistor. In fact, the voltage regulator 120 can be provided with one or more transistors connected in series, the number of which is not fixed. The circuit structure of multiple transistors connected in series can reduce the leakage phenomenon between the nodes.

The voltage regulator 130 is coupled to the first control terminal CE1. The voltage regulator 130 provides the first-stage gate driving signal G _[N-1] or the start pulse signal ST to adjust the first control signal Q _[N] according to the switching signal CHA and the reverse clock signal XCK. When both the reverse clock signal XCK and the switching signal CHA are at a low voltage level, the voltage regulator 130 can adjust the first according to the previous gate drive signal G _[N-1] or the start pulse signal ST The voltage value of the control signal Q _[N] .

Incidentally, when the shift register circuit 100 is the first-stage shift register circuit, the voltage regulator 130 can provide the starting pulse signal ST for adjustment according to the switching signal CHA and the reverse clock signal XCK The voltage value of the first control signal Q _[N] , on the other hand, when the shift register circuit 100 is not the shift register circuit of the first stage, the voltage regulator 130 can be based on the switching signal CHA and the reverse time The pulse signal XCK provides the previous-stage gate drive signal G _[N-1] to adjust the voltage value of the first control signal Q _[N] .

In this embodiment, the voltage regulator 130 includes transistors T1 and T2. The transistors T1 and T2 are connected in series with each other, wherein the transistor T1 receives the previous-stage gate drive signal G _[N-1] or the start pulse signal ST and is controlled by the reverse clock signal XCK. The transistor T2 is coupled to the first control terminal CE1 and is controlled by the switching signal CHA. It is worth mentioning that the arrangement order of the transistors T1 and T2 in FIG. 1 can be exchanged. The illustration in FIG. 1 is only an illustrative example, and does not limit the scope of the present invention.

The voltage regulator 140 is coupled to the second control terminal CE2. The voltage regulator 140 provides the gate high voltage V _GH according to the first control signal Q _[N] to adjust the second control signal P _[N] . When the first control signal Q _[N] is at a low voltage level, the voltage regulator 140 provides the gate high voltage V _GH to raise the voltage value of the second control signal P _[N] .

In this embodiment, the voltage regulator 140 includes transistors T8 and T9. Transistors T8 and T9 are connected in series between the second control terminal CE2 and the gate high voltage V _GH . It is worth mentioning that the number of transistors included in the voltage regulator 140 may also be one or more than two. The illustration in FIG. 1 is only an illustrative example, and is not intended to limit the scope of the present invention.

The voltage regulator 150 is coupled to the first control terminal CE1. The voltage regulator 150 adjusts the second control signal P _[N] according to the reverse clock signal XCK. The voltage regulator 150 includes transistors T6 and T7. The control terminals of the transistors T6 and T7 are commonly coupled to the first end of the transistor T6 and form a coupling configuration of a diode configuration. In this embodiment, the cathode of the diode constructed by the transistors T6 and T7 receives the reverse clock signal XCK, and the anode thereof is coupled to the second control terminal CE2.

In other embodiments of the present invention, the number of transistors included in the voltage regulator 150 may be one or more than two. The drawing in FIG. 1 is only an illustrative example, and is not intended to limit the scope of the present invention.

For details of the operation of the shift register circuit 100, please refer to FIG. 2 and FIGS. 3A to 3F at the same time, where FIG. 2 illustrates the operation waveform diagram of the gate driving device according to an embodiment of the present invention, and FIGS. 3A to 3F illustrate the present An equivalent circuit diagram of the shift register circuit of the embodiment of the invention.

2 and 3A, in the initial time interval TA0, when the reverse clock signal XCK is at a low voltage level (equal to the gate low voltage V _GL ), the transistors T6 and T7 reverse conduction, and make The voltage value of the two control signals P _[N] is equal to V _GL +|V _{TH_T6} |, where V _{TH_T6} is the turn-on voltage of the transistor T6. Then, the reverse clock signal XCK transitions to the high voltage level (equal to the gate high voltage V _GH ), the transistors T1 and T2 are cut off, and the state is switched to the low voltage level based on the mode selection signal SS1, and the voltage adjustment circuit The transistors T3 and T4 in 120 are turned on, and the voltage adjustment circuit 120 provides the gate high voltage V _GH to pull up the first control signal Q _[N] . At this time, the transistor T10 in the output stage circuit 110 is turned on according to the second control signal P _[N] , and the transistor T5 in the output stage circuit 110 is turned off according to the first control signal Q _[N] , and the output stage circuit 110 corresponds to the N-th gate drive signal G _[N] generated as a high voltage level. At the same time, the later-stage gate drive signal G _[N+1] generated by the later-stage shift register is also at a high voltage level (equal to the gate high voltage V _GH ).

Incidentally, in the initial time interval TA0, the transistors T8 and T9 in the voltage regulator 140 are turned off according to the first control signal Q _[N] equal to the high voltage level (equal to the gate high voltage V _GH ) .

Then please refer to FIG. 2 and FIG. 3B. In the time interval TA1, the gate drive device enters the compensation phase. At the same time, the switching signal CHA transitions to a high voltage level (equal to the gate high voltage V _GH ), and the mode selection signal SS2 transitions to a low voltage level (equal to the gate low voltage V _GL ). Based on the mode selection signal SS2 transitioning to a low voltage level, the output stage circuit 110 provides the mode selection signal SS2 according to the second control signal P _[N] to charge the output terminal OE, and causes the Nth gate drive signal G The voltage value of _[N] is pulled down to be equal to the gate low voltage V _GL .

Corresponding to the pull-down action of the N-th gate drive signal G _[N] , the voltage value of the second control signal P _[N] is pulled down to be equal to V _GL +|V _{TH_T6} | _-DV through the coupling effect of the capacitor C2 . The size of DV is determined according to the ratio of the capacitance value of the capacitor C2 and the equivalent capacitance value on the second control terminal CE2.

It is worth noting that at this time, the transistors T1 and T2 in the voltage regulator 130 associated with the previous-stage gate drive signal G _[N-1] or the start pulse signal ST are all disconnected. Therefore, All the shift register circuits in the gate driving device can simultaneously generate a gate driving signal equal to the gate low voltage V _GL , that is, the voltage value of the subsequent gate driving signal G _[N+1] Equal to the gate low voltage V _GL .

Then please refer to FIG. 2 and FIG. 3C. In the time interval TA2, the gate drive device ends the compensation phase and is ready to enter the write phase. In the time interval TA2, the mode selection signal SS2 transitions to a high voltage level (equal to the gate high voltage V _GH ). A voltage value according to the mode circuit 110 through the output stage is turned on to maintain the transistor T10, the first N-level gate driving signal G _[N] of the selection signal SS2 is pulled to a high gate voltage V _GH. Moreover, through the coupling effect of the capacitor C2, the voltage value of the second control signal P _[N] is pulled up to be equal to V _GL +|V _{TH_T6} |, and based on the transistors T3 and T4 in the voltage regulator 120 being continuously turned on In this case, the voltage value of the first control signal Q _[N] remains equal to the gate high voltage V _GH .

On the other hand, the mode selection signal SS2 received based on all the shift register circuits is the same, therefore, in the time interval TA2, the voltage value of the gate driving signal G _[N+1] in the N+1 stage depends on the mode The selection signal SS2 is pulled up to the gate high voltage V _GH synchronously. In this way, the gate driving device can enable all the gate driving signals to be enabled (pulled down) at the same time, and can perform the compensation action of the thin film transistors of all pixel circuits.

Then please refer to FIG. 2 and FIG. 3D. In the time interval TA3, the gate driving device enters the first sub-phase of the writing phase. In the time interval TA3, the mode selection signal SS1 transitions to a high voltage level (equal to the gate high voltage V _GH ), and the switching signal CHA transitions to a low voltage level (equal to the gate low voltage V _GL ). At the same time, the voltage regulator 130 is turned on according to the switching signal CHA and the reverse clock signal XCK, and receives the start pulse signal ST as a low voltage level (equal to the gate low voltage V _GL ). Through the turned-on transistors T1 and T2, the voltage value of the first control signal Q _[N] is pulled down according to the initial pulse signal ST. At this time, the voltage value of the first control signal Q _[N] is equal to V _GL +|V _{TH_T1} |, where V _{TH_T1} is the on-voltage of the transistor T1.

As the voltage value of the first control signal Q _[N] is pulled down, the transistors T8, T9 in the voltage regulator 140 are turned on. As a result, the voltage value of the second control signal P _[N] is pulled up according to the gate high voltage V _GH . In this embodiment, the second control signal P _[N] can be pulled up to a voltage V _GM slightly lower than the gate high voltage V _GH during the time interval TA3. Among them, V _GH > V _GM > V _GL +|V _{TH_T6} |. At the same time, the transistor T5 remains turned on, the transistor T10 remains turned off, and the voltage value of the N-th gate drive signal G _[N] remains equal to the gate high voltage V _GH .

It is worth mentioning that the voltage regulator 130 can receive the start pulse signal ST, or can also receive the previous-stage gate drive signal G _[N-1] . The voltage regulator 130 may determine to receive the start pulse signal ST or the previous-stage gate drive signal G _[N-1] according to the position of the shift register circuit to which it belongs. To briefly explain, when the voltage regulator 130 belongs to the shift register circuit of the first stage, the voltage regulator 130 can receive the start pulse signal ST, and when the voltage regulator 130 does not belong to the shift register of the first stage During the circuit, the voltage regulator 130 can receive the previous-stage gate driving signal G _[N-1] .

Then please refer to FIG. 2 and FIG. 3E. In the time interval TA4, the gate driving device enters the second sub-phase of the writing phase. In the time interval TA4, the voltage value of the start pulse signal ST is pulled up to the gate high voltage V _GH . The reverse clock signal XCK and the switching signal CHA then transition to a high voltage level, and turn off the transistors T1 and T2 in the voltage regulator 130. On the other hand, the clock signal CK transitions from the gate high voltage V _GH to the gate low voltage V _GL . By maintaining the turned-on transistor T5, the voltage value of the N-th gate drive signal G _[N] is pulled down to the gate low voltage V _GL .

Please note that the voltage value of the first control signal Q _[N] can be further reduced by the coupling effect generated by the capacitor C1 based on the action of pulling down the voltage value of the gate drive signal G _[N] of the Nth stage _Pull down to V _GL +|V _{TH_T1} | _-DV . Under the condition that the voltage value of the first control signal Q _[N] can be further lowered, the transistors T8 and T9 in the voltage regulator 140 can be turned on and make the voltage of the second control signal P _[N] The value is pulled up to the gate high voltage V _GH .

Then please refer to FIG. 2 and FIG. 3F. In the time interval TA5, the gate drive device enters the voltage holding phase. In the time interval TA5, the gate drive signal G _{[N] of} the Nth stage is transmitted to the shift register circuit of the subsequent stage, becomes the gate drive signal of the preceding stage of the shift register circuit of the subsequent stage, and drives the subsequent stage The gate drive signal G _[N+1] of the N+1th stage generated by the shift temporary storage circuit is pulled down to the gate low voltage V _GL . In addition, transistor T1 according to a periodic clock signal CK of periodic transient conduction periodically charging the first control signal Q _[N], to maintain the first control signal Q _[N] is equal to the value of the gate voltage Low voltage V _GL . The transistor T5 is turned off according to the first control signal Q _[N] being pulled down. On the other hand, the voltage regulator 150 periodically charges the second control signal P _[N] according to the periodically inverted reverse clock signal XCK. In order to drive the voltage value of the second control signal P _[N] to fall and maintain at V _GL +|V _{TH_T6} |, and the transistor T10 is turned on. The gate drive signal G _{[N] of} the _N- th stage transitions according to the mode selection signal SS2 and is maintained at the gate high voltage V _GH .

From the above description, it is not difficult to know that through the step-by-step transmission of the pulled-down gate drive signal, during the writing phase, the gate drive device can generate the gate drive signals that are sequentially enabled (pulled down), and Write data to multiple pixel rows sequentially.

In summary, the present invention provides a shift temporary storage circuit, and forms a gate drive signal through a shift temporary storage circuit connected in series. The gate drive signal provided by the present invention can provide a plurality of gate drive signals that are commonly enabled in the compensation phase, and generate the gate drive signals that are sequentially enabled in the write phase to provide sufficient time to perform data writing Into action. It can be effectively matched with the display panel of synchronous active organic light-emitting diode, and applied to the display panel with high resolution. In addition, in the embodiment of the present invention, the voltage regulator is constructed through a plurality of transistors connected in series, which can reduce the leakage phenomenon of internal nodes and save power consumption.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100‧‧‧shift temporary storage circuit 110‧‧‧ output stage circuit 120~150‧‧‧ voltage regulators CE1, CE2‧‧‧ control terminals Q[N], P[N]‧‧‧ control signal OE‧‧ ‧Output terminal SS1, SS2‧‧‧ Mode selection signal CK‧‧‧Clock signal CHA‧‧‧Switch signal XCK‧‧‧Reverse clock signal G[N]‧‧‧Nth gate drive signal T1~ T10‧‧‧Transistor C1, C2‧‧‧Capacitor VGH‧‧‧Gate high voltage VGL‧‧‧Gate low voltage G[N-1]‧‧‧Previous gate drive signal ST‧‧‧Start Pulse signal G _[N+1] ‧‧‧Gate drive signal TA0~TA5 ‧‧‧

FIG. 1 is a schematic diagram of a gate driving device according to an embodiment of the invention. FIG. 2 illustrates an operation waveform diagram of the gate driving device according to an embodiment of the invention. 3A to 3F illustrate equivalent circuit diagrams of the shift register circuit of the embodiment of the present invention.

100‧‧‧shift temporary storage circuit

110‧‧‧ output stage circuit

120~150‧‧‧Voltage regulator

CE1, CE2‧‧‧Control

Q _[N] , P _[N] ‧‧‧ control signal

OE‧‧‧Output

SS1, SS2‧‧‧Mode selection signal

CK‧‧‧clock signal

CHA‧‧‧switch signal

XCK‧‧‧Reverse clock signal

G _[N] ‧‧‧ Nth gate drive signal

T1~T10‧‧‧Transistor

C1, C2‧‧‧Capacitance

V _GH ‧‧‧ gate high voltage

G _[N-1] ‧‧‧Previous gate drive signal

ST‧‧‧Start pulse signal

Claims (17)

A gate drive device includes: a plurality of shift register circuits, which are coupled in series to each other, and generate a plurality of gate drive signals, wherein the shift register circuit of the Nth stage includes: a The output stage circuit has a first control terminal and a second control terminal to respectively receive a first control signal and a second control signal, and according to the first control signal and the second control signal to provide a clock signal or a The first mode selection signal is sent to an output terminal to generate an N-th gate drive signal; a first voltage regulator, coupled to the first control terminal, provides a gate high voltage according to a second mode selection signal To adjust the first control signal; a second voltage regulator, coupled to the first control terminal, according to a switching signal and a reverse clock signal to provide a front-stage gate drive signal or a starting pulse signal To adjust the first control signal; a third voltage regulator, coupled to the second control terminal, provides the gate high voltage according to the first control signal to adjust the second control signal; and a fourth voltage The regulator is coupled to the first control terminal and adjusts the second control signal according to the reverse clock signal. The gate drive device as claimed in item 1 of the patent application, wherein in a compensation stage, the second voltage regulator is turned off according to the switching signal, and the first voltage regulator is turned on according to the second mode selection signal And provide the gate high voltage to pull up the first control signal. The gate drive device as claimed in item 2 of the patent application scope, wherein in the compensation stage, the third voltage regulator is cut off according to the first control signal, the fourth voltage regulator is cut off and pulled low The second control signal. The gate drive device as described in item 3 of the patent application range, wherein in the compensation stage, the output stage circuit provides the first mode selection signal to the output terminal according to the second control signal and generates the Nth stage Gate drive signal. The gate drive device according to item 2 of the patent application scope, wherein in a first sub-stage of a writing stage, the first voltage regulator is turned off according to the second mode selection signal, and the second voltage regulation The device is turned on according to the switching signal and the inverted clock signal pulled down to transmit the previous-stage gate driving signal or the starting pulse signal to pull down the first control signal. The gate drive device as claimed in item 5 of the patent application range, wherein in the first sub-stage of the writing stage, the third voltage regulator is turned on according to the first control signal and provides the gate high voltage To raise the second control signal, the fourth voltage regulator is turned on. The gate drive device as described in item 5 of the patent application range, wherein in a second sub-stage of the writing stage, the second voltage regulator is cut off according to the reverse clock signal being pulled up, the The first control signal is pulled down by an offset value according to the clock signal being pulled down. The gate drive device as described in item 7 of the patent application range, wherein the output stage circuit provides the clock signal to the output terminal according to the first control signal and generates the Nth gate drive signal. The gate drive device according to item 2 of the patent application scope, wherein in a voltage holding stage, the second voltage regulator is periodically turned on according to the clock signal, and periodically charges the first control signal, The first voltage regulator and the third voltage regulator remain off. The fourth voltage regulator is periodically turned on according to the reverse clock signal, and periodically charges the second control signal. The gate drive device as claimed in item 9 of the patent application range, wherein in the voltage holding phase, the output stage circuit provides the first mode selection signal according to the second control signal to generate the Nth gate drive signal . The gate drive device according to item 1 of the patent application scope, wherein the output stage circuit includes: a first transistor whose first end receives the clock signal, and a second end of the first transistor is coupled to The output terminal, the control terminal of the first transistor receives the first control signal; a first capacitor, coupled between the control terminal of the first transistor and the output terminal; a second transistor, the first The terminal is coupled to the output terminal, the second terminal of the second transistor receives the first mode selection signal, the control terminal of the second transistor receives the second control signal; and a second capacitor coupled to the Between the control terminal of the second transistor and the output terminal. The gate driving device as described in item 1 of the patent application scope, wherein the first voltage regulator includes: at least one transistor coupled between the first control terminal and the gate high voltage, the at least one transistor The control terminal of receives the second mode selection signal. The gate drive device as described in item 1 of the patent application, wherein the second voltage regulator includes: a first transistor whose first end receives the previous-stage gate drive signal or the starting pulse signal, The control terminal of the first transistor receives the reverse clock signal; and a second transistor, the first terminal of which is coupled to the second terminal of the first transistor, and the second terminal of the second transistor Connected to the first control terminal, the control terminal of the second transistor receives the switching signal. The gate drive device as described in item 1 of the patent application scope, wherein the third voltage regulator includes: at least one transistor, coupled between the second control terminal and the gate high voltage, the at least one transistor The control end of receives the first control signal. The gate drive device as described in item 1 of the patent application scope, wherein the fourth voltage regulator includes: a diode whose cathode receives the reverse clock signal, and whose anode is coupled to the second control terminal. The gate drive device as described in item 15 of the patent application scope, wherein the diode includes: a first transistor whose first terminal and control terminal receive the reverse clock signal; and a second transistor, The first terminal is coupled to the second terminal of the first transistor, the control terminal of the second transistor receives the reverse clock signal, and the second terminal of the second transistor is coupled to the second control terminal. The gate drive device as described in item 1 of the patent application scope, wherein the gate drive signals are simultaneously enabled during a compensation phase, and the gate drive signals are sequentially enabled during a write phase, In a voltage holding phase, the gate drive signals are kept at the disabled voltage value, wherein the compensation phase, the writing phase, and the voltage holding phase occur in sequence.

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