TW201914382A - Circuit board and manufacturing method thereof - Google Patents
Circuit board and manufacturing method thereof Download PDFInfo
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- TW201914382A TW201914382A TW106140405A TW106140405A TW201914382A TW 201914382 A TW201914382 A TW 201914382A TW 106140405 A TW106140405 A TW 106140405A TW 106140405 A TW106140405 A TW 106140405A TW 201914382 A TW201914382 A TW 201914382A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09672—Superposed layout, i.e. in different planes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
本發明涉及電路板製作領域,尤其涉及一種多層電路板及其製作方法。The invention relates to the field of circuit board manufacturing, in particular to a multilayer circuit board and a manufacturing method thereof.
印刷電路板因具有裝配密度高等優點而得到了廣泛的應用。關於電路板的應用請參見文獻Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880,IEEE Trans. on Components, Packaging, and Manufacturing Technology, 1992, 15(4): 1418-1425。Printed circuit boards have been widely used for their advantages such as high assembly density. For the application of circuit boards, please refer to the literature Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880, IEEE Trans on Components, Packaging, and Manufacturing Technology, 1992, 15 (4): 1418-1425.
在電路板的製作過程中,通常會對焊墊進行表面處理,在焊墊表面先後鍍上一層鍍鎳層及一層鍍金層。焊墊、鍍鎳層、鍍金層均設置在絕緣層上,鍍鎳層包覆焊墊,鍍金層包覆鍍鎳層。實際情況中,鍍金層、鍍鎳層與絕緣層的交界處均存在微小的空隙。潮濕的空氣很容易從空隙中進入與所述鍍鎳層發生金屬腐蝕。鍍鎳層腐蝕到一定程度,鍍金層將從電路板上剝離脫落。During the manufacturing process of the circuit board, the pads are usually surface-treated, and the surface of the pads is plated with a layer of nickel and a layer of gold. The solder pad, nickel plating layer, and gold plating layer are all disposed on the insulating layer, the nickel plating layer covers the solder pad, and the gold plating layer covers the nickel plating layer. In actual conditions, there are tiny voids at the junctions of the gold-plated layer, the nickel-plated layer, and the insulating layer. Humid air easily enters from the gap and metal corrosion occurs with the nickel plating layer. The nickel plating layer is corroded to a certain extent, and the gold plating layer will be peeled off from the circuit board.
有鑒於此,有必要提供一種電路板及其製作方法解決上述技術問題。In view of this, it is necessary to provide a circuit board and a manufacturing method thereof to solve the above technical problems.
一種電路板的製作方法,包括步驟:A method for manufacturing a circuit board includes the steps:
提供一第一銅箔層及一絕緣層,所述第一銅箔層固定設置在所述絕緣層上;Providing a first copper foil layer and an insulating layer, and the first copper foil layer is fixedly disposed on the insulating layer;
在所述第一銅箔層表面製作形成一具有線路圖案的第一導電層,所述第一導電層包括多個第一導電墊;Forming a first conductive layer with a circuit pattern on the surface of the first copper foil layer, the first conductive layer including a plurality of first conductive pads;
蝕刻所述第一銅箔層得到第二導電層,使所述第二導電層的線路圖案與所述第一導電層的線路圖案相正對應,所述第二導電層包括多個第二導電墊,所述第二導電墊的厚度小於所述第一導電墊的厚度,所述第一導電墊與所述第二導電墊共同構成所述電路板的焊墊,每個第一導電墊設置在相對應的所述第二導電墊上,所述第二導電墊相對所述第一導電墊具有突出部分,所述突出部分環繞所述第一導電墊;Etching the first copper foil layer to obtain a second conductive layer, so that the circuit pattern of the second conductive layer corresponds directly to the circuit pattern of the first conductive layer, and the second conductive layer includes a plurality of second conductive layers. Pad, the thickness of the second conductive pad is smaller than the thickness of the first conductive pad, the first conductive pad and the second conductive pad together form a solder pad of the circuit board, and each first conductive pad is provided On the corresponding second conductive pad, the second conductive pad has a protruding portion opposite to the first conductive pad, and the protruding portion surrounds the first conductive pad;
在所述焊墊的上表面及側面鍍上一層鍍鎳金層。A nickel-plated gold layer is plated on the upper surface and the side of the solder pad.
一種電路板包括一絕緣層、一焊墊、一鍍鎳金層。所述焊墊、所述鍍鎳金層均設置在所述絕緣層上。所述鍍鎳金層包覆所述焊墊。所述焊墊包括第一導電墊及第二導電墊。所述第二導電墊設置在所述絕緣層上。所述第一導電墊設置在所述第二導電墊上。所述第二導電墊的厚度小於所述第一導電墊的厚度。所述第二導電墊相對所述第一導電墊具有突出部分。所述突出部分環繞所述第一導電墊。A circuit board includes an insulating layer, a solder pad, and a nickel-plated gold layer. The solder pad and the nickel-plated gold layer are both disposed on the insulating layer. The nickel-plated gold layer covers the solder pad. The solder pad includes a first conductive pad and a second conductive pad. The second conductive pad is disposed on the insulating layer. The first conductive pad is disposed on the second conductive pad. A thickness of the second conductive pad is smaller than a thickness of the first conductive pad. The second conductive pad has a protruding portion opposite to the first conductive pad. The protruding portion surrounds the first conductive pad.
與先前技術相比,本發明提供的電路板及其製作方法包括所述焊墊,所述焊墊包括所述第二導電墊及所述第一導電墊。所述第二導電墊設置在所述絕緣層上,所述第一導電墊設置在所述第二導電墊上,所述第二導電墊的厚度小於所述第一導電墊的厚度,所述第二導電墊相對所述第一導電墊具有突出部分,所述突出部分環繞所述第一導電墊,所述突出部分靠近所述鍍金層延伸設置,取代所述鍍鎳層優先與所述鍍金層、鍍鎳層與所述絕緣層之間進入的空氣及水分發生反應,延緩了所述鍍鎳層與空氣及水分的反應時間,一定程度上阻止了所述鍍金層將從所述電路板上剝離脫落。Compared with the prior art, the circuit board and the manufacturing method thereof provided by the present invention include the solder pad, and the solder pad includes the second conductive pad and the first conductive pad. The second conductive pad is disposed on the insulating layer, the first conductive pad is disposed on the second conductive pad, and a thickness of the second conductive pad is smaller than a thickness of the first conductive pad. The two conductive pads have a protruding portion opposite to the first conductive pad, the protruding portion surrounds the first conductive pad, and the protruding portion is disposed close to the gold plating layer, replacing the nickel plating layer and the gold plating layer in preference. The air and moisture entering between the nickel-plated layer and the insulating layer react, delaying the reaction time of the nickel-plated layer and air and moisture, and to a certain extent, preventing the gold-plated layer from coming out of the circuit board Peel off.
下面以製作單層電路板為例,來說明本技術方案提供的電路板100的製作方法,所述電路板100的製作方法包括如下步驟:In the following, a single-layer circuit board is taken as an example to describe a method for manufacturing the circuit board 100 provided in this technical solution. The method for manufacturing the circuit board 100 includes the following steps:
第一步,請參閱圖1,提供一個銅箔基板10以及一個第一乾膜20,將所述第一乾膜20貼覆固定在所述銅箔基板10的銅箔表面。In the first step, referring to FIG. 1, a copper foil substrate 10 and a first dry film 20 are provided, and the first dry film 20 is adhered and fixed on the copper foil surface of the copper foil substrate 10.
所述銅箔基板10包括一絕緣層12以及一第一銅箔層14。所述第一銅箔層14貼覆在所述絕緣層12上。銅箔基板10可以為軟性的銅箔基板,也可以為硬性的銅箔基板。所述第一乾膜20貼覆在所述第一銅箔層14上。The copper foil substrate 10 includes an insulating layer 12 and a first copper foil layer 14. The first copper foil layer 14 is covered on the insulating layer 12. The copper foil substrate 10 may be a flexible copper foil substrate or a rigid copper foil substrate. The first dry film 20 is coated on the first copper foil layer 14.
第二步,一併請參閱圖2及圖3,對所述第一乾膜20進行曝光、顯影處理,在所述第一乾膜20上形成第一乾膜圖案22。In the second step, referring to FIG. 2 and FIG. 3 together, the first dry film 20 is exposed and developed to form a first dry film pattern 22 on the first dry film 20.
請參閱圖3,所述第一乾膜圖案22上形成有多個第一開口220。部分所述第一銅箔層14從所述多個第一開口220中暴露。Referring to FIG. 3, a plurality of first openings 220 are formed on the first dry film pattern 22. A portion of the first copper foil layer 14 is exposed from the plurality of first openings 220.
第三步,請參閱圖4,對所述銅箔基板10進行電鍍,在所述第一銅箔層14上形成所述第一導電層30。In the third step, referring to FIG. 4, the copper foil substrate 10 is electroplated to form the first conductive layer 30 on the first copper foil layer 14.
所述第一導電層30填充所述多個第一開口220。本實施方式中,所述第一導電層30的厚度小於所述第一乾膜20的厚度。The first conductive layer 30 fills the first openings 220. In this embodiment, a thickness of the first conductive layer 30 is smaller than a thickness of the first dry film 20.
在其它實施方式中,所述第一導電層30的厚度可以大於或等於所述第一乾膜20的厚度。In other embodiments, the thickness of the first conductive layer 30 may be greater than or equal to the thickness of the first dry film 20.
第四步,請參閱圖5,將所述第一乾膜20從所述第一銅箔層14上去除。所述第一導電層30的厚度大於所述第一銅箔層14的厚度。所述第一導電層30包括多個第一導電墊32。In the fourth step, referring to FIG. 5, the first dry film 20 is removed from the first copper foil layer 14. The thickness of the first conductive layer 30 is greater than the thickness of the first copper foil layer 14. The first conductive layer 30 includes a plurality of first conductive pads 32.
第五步,請參閱圖6,提供一第二乾膜40,將所述第二乾膜40壓合貼覆在所述第一銅箔層14及所述第一導電層30上。所述第二乾膜40為感光性覆蓋膜。Fifth step, referring to FIG. 6, a second dry film 40 is provided, and the second dry film 40 is laminated and laminated on the first copper foil layer 14 and the first conductive layer 30. The second dry film 40 is a photosensitive cover film.
第六步,請一併參閱圖7及圖8,對所述第二乾膜40進行曝光及顯影處理,製作形成第二乾膜圖案42。In the sixth step, referring to FIG. 7 and FIG. 8 together, the second dry film 40 is exposed and developed to form a second dry film pattern 42.
本步驟中,所述第二乾膜圖案42包覆所述第一導電層30,並覆蓋部分所述第一銅箔層14。所述部分第一銅箔層14圍繞在所述第一導電層30。所述第二乾膜圖案42包括多個第二開口420。所述第一銅箔層14從所述多個第二開口420中暴露。In this step, the second dry film pattern 42 covers the first conductive layer 30 and covers a part of the first copper foil layer 14. The part of the first copper foil layer 14 surrounds the first conductive layer 30. The second dry film pattern 42 includes a plurality of second openings 420. The first copper foil layer 14 is exposed from the plurality of second openings 420.
第七步,請參閱圖9,蝕刻所述第一銅箔層14,將所述第一銅箔層14製作成具有線路圖案的第二導電層50,在所述絕緣層12上形成線路層60。Seventh step, referring to FIG. 9, the first copper foil layer 14 is etched, the first copper foil layer 14 is fabricated into a second conductive layer 50 having a circuit pattern, and a circuit layer is formed on the insulating layer 12 60.
所述第二導電層50的線路圖案與所述第一導電層30的線路圖案相對應。The circuit pattern of the second conductive layer 50 corresponds to the circuit pattern of the first conductive layer 30.
第八步,請參閱圖10,剝除所述第二導電層50與所述第一導電層30上的第二乾膜40,使所述第二導電層50與所述第一導電層30暴露出來。 所述第二導電層50包括多個第二導電墊52。所述第二導電層50與所述第一導電層30共同形成線路層60。所述線路層60包括上下堆疊的所述第一導電層30及所述第二導電層50。所述線路層60包括多個焊墊70。所述焊墊70包括第一導電墊32及所述第二導電墊52。所述第二導電墊52設置在所述絕緣層12上。所述第一導電墊32固定在所述第二導電墊52上。所述第二導電墊52的厚度小於所述第一導電墊32的厚度。所述第二導電墊52相對所述第一導電墊32具有突出部分54。所述突出部分54環繞所述第一導電墊32。Eighth step, referring to FIG. 10, peeling off the second dry film 40 on the second conductive layer 50 and the first conductive layer 30 to make the second conductive layer 50 and the first conductive layer 30 Exposed. The second conductive layer 50 includes a plurality of second conductive pads 52. The second conductive layer 50 and the first conductive layer 30 together form a circuit layer 60. The circuit layer 60 includes the first conductive layer 30 and the second conductive layer 50 stacked on top of each other. The circuit layer 60 includes a plurality of bonding pads 70. The bonding pad 70 includes a first conductive pad 32 and a second conductive pad 52. The second conductive pad 52 is disposed on the insulating layer 12. The first conductive pad 32 is fixed on the second conductive pad 52. The thickness of the second conductive pad 52 is smaller than the thickness of the first conductive pad 32. The second conductive pad 52 has a protruding portion 54 opposite to the first conductive pad 32. The protruding portion 54 surrounds the first conductive pad 32.
第九步,請參閱圖11,在所述焊墊70的表面鍍上一層鍍鎳層80,並在所述鍍鎳層80的表面鍍上一層鍍金層90,從而完成所述電路板100的製作。Ninth step, referring to FIG. 11, a nickel plating layer 80 is plated on the surface of the pad 70, and a gold plating layer 90 is plated on the surface of the nickel plating layer 80 to complete the circuit board 100. Production.
所述鍍鎳層80設置在所述絕緣層12上,並包覆所述焊墊70。所述鍍金層90設置在所述絕緣層12上,並包覆所述鍍鎳層80。The nickel plating layer 80 is disposed on the insulation layer 12 and covers the solder pad 70. The gold plating layer 90 is disposed on the insulating layer 12 and covers the nickel plating layer 80.
請參閱圖11,所述電路板100包括所述絕緣層12、所述焊墊70、所述鍍鎳層80及所述鍍金層90。所述焊墊70、所述鍍鎳層80及所述鍍金層90均設置在所述絕緣層12上。所述鍍鎳層80包覆所述焊墊70的上表面及側面。所述鍍金層90包覆所述鍍鎳層80。所述焊墊70包括所述第二導電墊52及所述第一導電墊32。所述第二導電墊52設置在所述絕緣層12上。所述第一導電墊32設置在所述第二導電墊52上。所述第二導電墊52的厚度小於所述第一導電墊32的厚度。所述第二導電墊52相對所述第一導電墊32具有突出部分54。所述突出部分54環繞所述第一導電墊32。Referring to FIG. 11, the circuit board 100 includes the insulating layer 12, the bonding pad 70, the nickel plating layer 80, and the gold plating layer 90. The pads 70, the nickel plating layer 80, and the gold plating layer 90 are all disposed on the insulation layer 12. The nickel plating layer 80 covers the upper surface and the side surfaces of the bonding pad 70. The gold plating layer 90 covers the nickel plating layer 80. The bonding pad 70 includes the second conductive pad 52 and the first conductive pad 32. The second conductive pad 52 is disposed on the insulating layer 12. The first conductive pad 32 is disposed on the second conductive pad 52. The thickness of the second conductive pad 52 is smaller than the thickness of the first conductive pad 32. The second conductive pad 52 has a protruding portion 54 opposite to the first conductive pad 32. The protruding portion 54 surrounds the first conductive pad 32.
所述第一導電墊32的頂部朝靠近所述鍍金層90的方向延伸。所述突出部分54沿垂直於所述絕緣層12方向的截面形狀為三角形、長方形或梯形中的一種。所述突出部分54的截面形狀並不限於此。The top of the first conductive pad 32 extends in a direction close to the gold plating layer 90. A cross-sectional shape of the protruding portion 54 along a direction perpendicular to the insulating layer 12 is one of a triangle, a rectangle, and a trapezoid. The cross-sectional shape of the protruding portion 54 is not limited to this.
其中,所述突出部分54最高點距離所述絕緣層12上表面的垂直高度為h;所述第二導電墊52及所述第一導電墊32的總厚度為T;所述鍍鎳層80與所述鍍金層90的總厚度為H,其中: h+H≦T。Wherein, the vertical height of the highest point of the protruding portion 54 from the upper surface of the insulating layer 12 is h; the total thickness of the second conductive pad 52 and the first conductive pad 32 is T; the nickel plating layer 80 The total thickness of the gold-plated layer 90 is H, where: h + H ≦ T.
所述突出部分54突出於所述第一導電墊32的寬度為d,其中: d≦T/3。The width of the protruding portion 54 protruding from the first conductive pad 32 is d, where: d ≦ T / 3.
本發明提供的電路板及其製作方法包括所述焊墊70,所述焊墊70包括所述第二導電墊52及所述第一導電墊32。所述第二導電墊52設置在所述絕緣層12上,所述第一導電墊32設置在所述第二導電墊52上,所述第二導電墊52的厚度小於所述第一導電墊32的厚度,所述第二導電墊52相對所述第一導電墊32具有突出部分54,所述突出部分54環繞所述第一導電墊32,所述突出部分54靠近所述鍍金層90延伸設置,取代所述鍍鎳層80優先與所述鍍金層90、鍍鎳層80與所述絕緣層12之間進入的空氣及水分發生反應,延緩了所述鍍鎳層80與空氣及水分的反應時間,一定程度上阻止了所述鍍金層90將從所述電路板100上剝離脫落。The circuit board provided by the present invention and a manufacturing method thereof include the solder pad 70, and the solder pad 70 includes the second conductive pad 52 and the first conductive pad 32. The second conductive pad 52 is disposed on the insulating layer 12, the first conductive pad 32 is disposed on the second conductive pad 52, and the thickness of the second conductive pad 52 is smaller than that of the first conductive pad 32, the second conductive pad 52 has a protruding portion 54 opposite to the first conductive pad 32, the protruding portion 54 surrounds the first conductive pad 32, and the protruding portion 54 extends near the gold plating layer 90 It is provided to replace the nickel-plated layer 80 to preferentially react with the air and moisture entering between the gold-plated layer 90, the nickel-plated layer 80 and the insulating layer 12, and delay the reaction between the nickel-plated layer 80 and the air and moisture. The reaction time prevents the gold plating layer 90 from peeling off the circuit board 100 to a certain extent.
可以理解的係,對於本領域具有通常知識者來說,可以根據本發明的技術構思做出其他各種相應的改變與變形,而所有這些改變與變形都應屬於本發明的保護範圍。Understandably, for those having ordinary knowledge in the art, various other corresponding changes and deformations can be made according to the technical concept of the present invention, and all these changes and deformations should belong to the protection scope of the present invention.
100‧‧‧電路板 100‧‧‧Circuit Board
10‧‧‧銅箔基板 10‧‧‧ Copper foil substrate
12‧‧‧絕緣層 12‧‧‧ Insulation
14‧‧‧第一銅箔層 14‧‧‧The first copper foil layer
20‧‧‧第一乾膜 20‧‧‧The first dry film
22‧‧‧第一乾膜圖案 22‧‧‧The first dry film pattern
220‧‧‧第一開口 220‧‧‧ the first opening
30‧‧‧第一導電層 30‧‧‧first conductive layer
32‧‧‧第一導電墊 32‧‧‧The first conductive pad
40‧‧‧第二乾膜 40‧‧‧Second dry film
42‧‧‧第二乾膜圖案 42‧‧‧Second dry film pattern
420‧‧‧第二開口 420‧‧‧Second opening
50‧‧‧第二導電層 50‧‧‧ second conductive layer
52‧‧‧第二導電墊 52‧‧‧Second conductive pad
54‧‧‧突出部分 54‧‧‧ prominence
60‧‧‧線路層 60‧‧‧Line layer
70‧‧‧焊墊 70‧‧‧pad
80‧‧‧鍍鎳層 80‧‧‧ nickel plating
90‧‧‧鍍金層 90‧‧‧ gold plating
圖1係發明較佳實施例提供的銅箔基板及第一乾膜的剖面示意圖。FIG. 1 is a schematic cross-sectional view of a copper foil substrate and a first dry film according to a preferred embodiment of the present invention.
圖2係圖1的第一乾膜曝光形成圖案後的剖面示意圖。FIG. 2 is a schematic cross-sectional view of the first dry film in FIG. 1 after being patterned.
圖3係圖2的第一乾膜顯影後的剖面示意圖。FIG. 3 is a schematic cross-sectional view of the first dry film of FIG. 2 after development.
圖4係圖3的第一乾膜圖案中形成第一導電層後的剖面示意圖。4 is a schematic cross-sectional view of the first dry film pattern after the first conductive layer is formed in FIG. 3.
圖5係圖4的銅箔基板剝除第一乾膜後的剖面示意圖。5 is a schematic cross-sectional view of the copper foil substrate of FIG. 4 after the first dry film is removed.
圖6係圖5的第一銅箔層及第一導電層壓合貼覆第二乾膜後的剖面示意圖。6 is a schematic cross-sectional view of the first copper foil layer and the first conductive laminate of FIG. 5 after the second dry film is laminated.
圖7係圖6的第二乾膜曝光後的剖面示意圖。FIG. 7 is a schematic cross-sectional view of the second dry film of FIG. 6 after exposure.
圖8係圖7的第二乾膜顯影後的剖面示意圖。FIG. 8 is a schematic cross-sectional view of the second dry film of FIG. 7 after development.
圖9係圖8的第一銅箔層蝕刻形成圖案後的剖面示意圖。FIG. 9 is a schematic cross-sectional view of the first copper foil layer in FIG. 8 after being patterned by etching.
圖10係圖9的第二乾膜從第一銅箔層及第一導電層剝除後的剖面示意圖。FIG. 10 is a schematic cross-sectional view of the second dry film of FIG. 9 after being stripped from the first copper foil layer and the first conductive layer.
圖11係圖10的焊墊上形成鍍鎳層及鍍金層後的剖視圖。11 is a cross-sectional view of a nickel-plated layer and a gold-plated layer formed on the pad of FIG. 10.
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CN110809364A (en) * | 2019-11-15 | 2020-02-18 | 广州兴森快捷电路科技有限公司 | PCB manufacturing method and PCB |
CN114554729B (en) * | 2020-11-27 | 2024-07-05 | 鹏鼎控股(深圳)股份有限公司 | Circuit board manufacturing method and circuit board |
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US5800575A (en) * | 1992-04-06 | 1998-09-01 | Zycon Corporation | In situ method of forming a bypass capacitor element internally within a capacitive PCB |
US5764485A (en) * | 1996-04-19 | 1998-06-09 | Lebaschi; Ali | Multi-layer PCB blockade-via pad-connection |
US5912809A (en) * | 1997-01-21 | 1999-06-15 | Dell Usa, L.P. | Printed circuit board (PCB) including channeled capacitive plane structure |
CN103582304B (en) * | 2012-07-30 | 2016-08-03 | 富葵精密组件(深圳)有限公司 | Transparent printed circuit board (PCB) and preparation method thereof |
CN202857129U (en) * | 2012-09-11 | 2013-04-03 | 岳长来 | Structure of metal palladium layer in conducting layer of printed circuit board |
CN102802364B (en) * | 2012-09-11 | 2014-11-05 | 深圳市和美精艺科技有限公司 | Method for arranging metal palladium layer in conducting layer of printed circuit board and layered structure thereof |
CN104427738A (en) * | 2013-08-21 | 2015-03-18 | 富葵精密组件(深圳)有限公司 | Printed circuit board and manufacturing method thereof |
CN106304662B (en) * | 2015-05-27 | 2019-06-11 | 鹏鼎控股(深圳)股份有限公司 | Circuit board and method of making the same |
KR102552614B1 (en) * | 2016-02-26 | 2023-07-06 | 주식회사 기가레인 | Flexible printed circuit board |
CN206260136U (en) * | 2016-12-23 | 2017-06-16 | 中磊电子(苏州)有限公司 | Circuit board |
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