JP2007324232A - BGA type multilayer wiring board and BGA type semiconductor package - Google Patents

Abstract

Provided are a BGA type multilayer wiring board and a BGA type semiconductor package in which breakage of connection vias due to heat generation during operation of a semiconductor chip is effectively prevented.
A chip mounting area including a plurality of wiring patterns alternately stacked via an insulating layer and having a semiconductor chip mounted on one surface thereof, and including the chip mounting area and one more than the chip mounting area. A large chip mounting area 5 is provided, and the other surface is internally connected to the wiring pattern, and is provided with a plurality of BGA pads to which signal lines and power / ground lines are to be connected externally. In the BGA type multilayer wiring board 1, the signal line is not connected to the BGA pad 7 located in the region corresponding to the chip mounting area on the other side, but the power / ground line is connected, and the chip on the other side is connected. A signal line is connected to the BGA pad 6 located in a region corresponding to an area outside the mounting area.
[Selection] Figure 2

Description

  The present invention relates to a BGA type multilayer wiring board and a BGA type semiconductor package used for electronic devices and the like, and more particularly to a BGA type multilayer wiring board and a BGA type semiconductor package in which breakage of connection vias is prevented.

 Multilayer wiring boards are widely used as circuit boards of a type in which semiconductor integrated circuit elements are directly mounted / connected, and as external circuits for connecting semiconductor devices in a state where the semiconductor integrated circuit elements are mounted / connected to a lead frame.

 In recent years, BGA type multilayer wiring boards in which external terminals are formed of solder balls have been used as such multilayer wiring boards. In the BGA type multilayer wiring board, it is important to improve the connection reliability and mounting reliability between the chip and the mother board. In particular, in the case of a flexible substrate, since the degree of freedom of contraction of the substrate is high, it is called a stiffener. Mounting reliability is improved by fixing the substrate with a metal plate or pouring underfill resin into the bump connection portion (see, for example, Patent Document 1).

However, it is difficult to ensure high mounting reliability of the BGA type multilayer wiring board only by improving the mounting method. In particular, for a substrate having a total thickness of 500 μm or less, since the heat capacity of the entire substrate is small, the thermal stress applied to the via increases and the probability of via fracture increases. In addition, the probability that the substrate via breaks in the underfill resin region becomes extremely high due to the difference in thermal expansion between the underfill resin in the bump connection portion and the substrate. The underfill resin region is a region extending about 3 mm from the chip, and the via is often broken due to the thermal effect during the chip operation, thus reducing the mounting reliability.
Japanese Patent No. 318062

  An object of the present invention is to provide a BGA type multilayer wiring board and a BGA type semiconductor package which are made under the circumstances described above and which effectively prevent breakage of connection vias due to heat generation during operation of a semiconductor chip.

  In order to solve the above-described problem, a first aspect of the present invention includes a chip mounting area including a plurality of wiring patterns alternately stacked via insulating layers and mounting a semiconductor chip on one surface thereof, It has a chip mounting area that includes the chip mounting area and is slightly larger than the chip mounting area. On the other side, the wiring pattern is connected internally, and the signal lines and power / ground lines are connected externally. In a BGA type multilayer wiring board provided with a plurality of BGA pads to be provided, a signal line is not connected to a BGA pad located in a region corresponding to the chip mounting area on the other side, and a power / ground line is connected The signal line is connected to the BGA pad located in the area corresponding to the area outside the chip mounting area on the other side. Providing BGA type multilayer wiring board characterized.

  In this BGA type multilayer wiring board, the BGA pad to which the signal line is connected is connected to the wiring pattern through one connection via, and the BGA pad to which the power / ground line is connected is a plurality of connection vias. It can be set as the structure connected with the said wiring pattern via this.

  In this case, the wiring pattern in which the BGA pad to which the signal line is connected is connected through one connection via is connected to the inner wiring pattern in a region corresponding to the chip mounting area. be able to.

  The BGA type multilayer wiring board can have a thickness of 500 μm or less.

  According to a second aspect of the present invention, there is provided a chip mounting area including a plurality of wiring patterns alternately stacked via insulating layers, on which a semiconductor chip is mounted, and a chip mounting area including the chip mounting area. A chip mounting area that is one size larger than that, and on the other side, a plurality of BGA pads that are connected to the wiring pattern inside and to which signal lines and power / ground lines are to be connected outside are provided. In a BGA type semiconductor package comprising a BGA type multilayer wiring board and a semiconductor chip mounted on the chip mounting area of the BGA type multilayer wiring board, the BGA type multilayer wiring board is located in a region corresponding to the chip mounting area on the other surface. The signal line is not connected to the BGA pad to be connected, the power / ground line is connected, and the outside of the chip mounting area on the other side The BGA pads located in the region corresponding to the area, to provide a BGA type semiconductor package, wherein a signal line is connected.

  According to the present invention, the signal line is not connected to the BGA pad located in the region corresponding to the chip mounting area on the other side of the multilayer wiring board, but the power / ground line is connected (power / ground pad), and the other Since the signal line is connected to the BGA pad located in the area corresponding to the area outside the chip mounting area on the surface (signal pad), it is effective to break the connection via due to heat generated during operation of the semiconductor chip. Can be prevented.

  That is, the signal pad connected by one connection via is not arranged in a region where a large force is applied due to a difference in thermal expansion coefficient between the substrate and the underfill resin, but is arranged in an outer region. The via will not break. A power supply / ground pad is placed in the area where a large force is applied due to the difference in thermal expansion coefficient between the plate and the underfill resin, but the power / ground pad is connected by multiple connection vias, so the force is distributed, Breakage of the connection via is prevented.

  The best mode for carrying out the invention will be described below with reference to the drawings.

  FIG. 1 is a top view showing a multilayer wiring board and a semiconductor package having a semiconductor chip mounted thereon according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view thereof. 1 and 2, a semiconductor chip 3 is mounted in the chip mounting area 2 on the upper surface of the multilayer wiring board 1. An underfill resin 4 is filled between the multilayer wiring board 1 and the chip 3. The region 5 filled with the underfill resin 4 is called a chip mounting area. Since the underfill resin 4 covers the connection portion between the multilayer wiring board 1 and the chip 3 and has a shape that slightly expands toward the multilayer wiring board 1 side, the chip mounting area 5 includes the chip mounting area 2 and the chip mounting. This is a region that is slightly larger than the area 2 and that extends outward by about 3 mm.

  As shown in FIG. 2, the semiconductor chip 3 is mounted with solder balls. Thermal stress is applied to the entire multilayer wiring board 1 due to the operation of the semiconductor chip 3, causing thermal expansion and contraction of the multilayer wiring board 1, resulting in a problem that the via breaks. However, in this chip mounting area 5, thermal expansion and contraction occurs. As a result, the rate of via breakage is greater than the outside of the chip mounting area 5.

 In particular, in a thin multilayer wiring board having a substrate thickness of 500 μm or less, since the heat capacity of the entire multilayer wiring board 1 is small, the rate of occurrence of via fracture due to thermal expansion and contraction is high. Therefore, in the present invention, in the thin multilayer wiring board having a substrate thickness of 500 μm or less, the signal line is not connected to the BGA pad immediately below the chip mounting area 5, but the power supply / ground line is connected. A ground pad 7 is disposed. A signal line is connected to the BGA pad below the area outside the chip mounting area 5, that is, the signal pad 6 is arranged.

 3 (a) and 3 (b) are enlarged views of part A and part B in FIG. 2, respectively. 3A shows the signal pad 6 portion, and FIG. 3B shows the power / ground pad 7 portion.

 As shown in FIG. 3A, the signal pad 6 is connected to the wiring pattern 9a through one connection via 8a. As shown in FIG. 3B, the power / ground pad 7 includes a plurality of ( The wiring pattern 9b is connected via four (4) connection vias 8b. Reference numerals 10a and 10b denote solder balls.

 The reason why the signal pad 6 is connected to the wiring pattern 9a through one connection via 8a is that if there are a large number of connection vias, the flow of current and electric field becomes non-uniform and impedance mismatch occurs. It is. Characteristic impedance matching is important for signal lines, and there must be one connection via.

 On the other hand, in the case of the power supply / ground pad 7, even if there are a large number of connection vias 8b, there is no problem in electrical characteristics, and in order to improve connection reliability, the connection is made to the wiring pattern 9b via a large number of connection vias 8b. Is desirable.

 As shown in FIG. 2, the chip mounting area 5 is an area filled with the underfill resin 4. Due to the thermal influence during chip operation, the chip mounting area 5 is formed on the substrate 1 due to a difference in thermal expansion between the underfill resin 4 and the substrate 1. Stress is applied, and the connection via on the pad side immediately below the chip mounting area 5 is easily broken. However, when there are a large number of connection vias, the force applied to the connection vias is dispersed, and the breakage of the connection vias can be avoided.

 In the present invention, the power supply / ground pad 7 connected via a large number of connection vias is disposed immediately below the chip mounting area 5 and the signal pad 6 connected via a single connection via is not disposed. Prevents breakage of connecting vias.

 FIG. 4 is a view of a multilayer wiring board according to an embodiment of the present invention as viewed from below (BGA pad forming side). Under the chip mounting area 5 of the multilayer wiring board 1, only the power / ground pad 7 is arranged, and under the area outside the chip mounting area 5, the signal pad 6 and the power / ground pad 7 are arranged. Yes. That is, not only the signal pad 6 but also the power / ground pad 7 may be disposed under the area outside the chip mounting area 5.

 By disposing the signal pad 6 and the power / ground pad 7 in this way, breakage of the connection via can be prevented and mounting reliability can be greatly improved.

 The production of the multilayer circuit wiring board according to the present invention is not limited to being performed using a single-wafer substrate, but also in a roll-to-roll continuous production method using a tape-like flexible substrate. It is possible to apply.

Examples Hereinafter, examples of the present invention will be described with reference to FIGS. 5 and 6. 5 and 6 are cross-sectional views in the substrate width direction showing a method of manufacturing a semiconductor package made of a multilayer wiring board on which a semiconductor chip is mounted according to this embodiment in the order of steps.

 First, as shown in FIG. 5 (a), a polyimide substrate 13 with a double-sided copper foil prepared by pasting copper foils 12a and 12b on both sides of a polyimide layer 11 in the form of a tape having a width of 105 mm is prepared by copper polishing. The film thickness of the foils 12a and 12b was controlled to about 12 μm. Next, as shown in FIG. 5B, after degreasing the double-sided copper foil-attached polyimide substrate 13, the copper foil 12 a and the polyimide layer 11 are penetrated from the upper surface of the substrate 13 by laser processing, and the polyimide layer 11. A via hole 14 reaching the boundary surface of the copper foil 12b on the lower surface side was formed.

 Next, as shown in FIG.5 (c), after giving a desmear process inside the via hole 14 formed in the said polyimide substrate 13 with a double-sided copper foil, electroless copper plating and electrolytic copper plating are given, and a plating layer Then, conductive vias 15 for electrically connecting the copper foil layers on both sides of the substrate are formed, and then chemical polishing is performed with a mixed solution of sulfuric acid and hydrogen peroxide solution, so that the thickness of the copper foils 12a and 12b is about 10 μm. I made it.

 Then, as shown in FIG.5 (d), resist layer 16a, 16b was formed on both surfaces of the polyimide substrate 13 with a double-sided copper foil. A liquid resist was used as the resist. Next, as shown in FIG. 5E, after aligning the substrate and the photomask, exposure and development were performed to form resist patterns 17a and 17b. Development was carried out by dipping in a resist-dedicated developer.

 Next, the copper foils 12a, 12b on both sides of the polyimide substrate 13 with the double-sided copper foil are sprayed and sprayed onto the copper foils 12a, 12b through the resist patterns 17a, 17b, and the copper foils 12a, 12b exposed at the openings of the resist patterns 17a, 17b. After removing 12b by etching, the resist patterns 17a and 17b were peeled off to form wiring patterns 18a and 18b as shown in FIG.

 Next, as shown in FIG. 6B, a polyimide substrate 13 with a double-sided copper foil having wiring patterns 18a and 18b formed on both sides is used as a core substrate, and polyimide substrates 20a and 20b with a tape-like single-sided copper foil on each side. Was laminated through adhesives 19a and 19b so that the copper foils 21a and 21b were on the outside. The thickness of the adhesive was 30 μm.

 Next, as shown in FIG. 6C, via formation and wiring formation are respectively performed on the single-sided copper foil-coated polyimide substrates 20a and 20b laminated on both sides, and upper and lower two-layer printed wiring boards are formed as multilayer wiring boards. completed.

 In this case, the signal line was not connected to the BGA pad 22 immediately below the chip mounting area, but was connected to the BGA pad 23 directly below the chip mounting area. In addition, the via connection reliability is improved by using a large number of vias 24 as connection vias of the BGA pad 22 directly under the chip mounting area.

 FIG. 6D is a completed view of the semiconductor package after chip mounting. The solder resists 25a and 25b were made to have a resist film thickness of 30 μm by a spinner, and openings were formed in the solder resists 25a and 25b by performing exposure and development processing. Thereafter, solder printing was performed, solder balls 26 were formed on the FC pad portion, solder balls 27 were formed on the BGA pad portion, and a chip 28 was mounted via the solder balls 26 to complete a semiconductor package.

 When the chip mounting area of the semiconductor package manufactured as described above was filled with an underfill resin and operated, no breakage of the connection via due to heat generation of the chip 28 was observed.

 The present invention is not limited to the embodiments described above and shown in the drawings, and various modifications can be made without departing from the spirit of the present invention. The multilayer wiring board of the above embodiment has been described with respect to the case where the wiring pattern has two upper and lower layers. However, it can be widely applied to multilayer wiring boards and semiconductor packages having three or four upper and lower circuit patterns.

It is a top view which shows the semiconductor package using the BGA type | mold multilayer wiring board based on one Embodiment of this invention. It is a side view showing a semiconductor package using a BGA type multilayer wiring board concerning one embodiment of the present invention. It is sectional drawing which expands and shows the A section and B section of FIG. It is a bottom view which shows the BGA type | mold multilayer wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor package which concerns on the Example of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor package which concerns on the Example of this invention.

Explanation of symbols

   DESCRIPTION OF SYMBOLS 1,29 ... Multilayer wiring board, 2 ... Chip mounting area, 3, 28 ... Semiconductor chip, 4 ... Underfill resin, 5 ... Chip mounting area, 6 ... Signal pad, 7 ... Power supply / ground pad, 8a, 8b ... Connection Vias, 9a, 9b ... wiring patterns, 10a, 10b, 26, 27 ... solder balls, 11 ... polyimide layers, 12a, 12b, 21a, 21b ... copper foils, 13 ... polyimide substrates with double-sided copper foils, 14 ... via holes, 15 ... conductive vias, 16a, 16b ... resist layers, 17a, 17b ... resist patterns, 18a, 18b ... wiring patterns, 19a, 19b ... adhesives, 20a, 20b ... polyimide substrates with single-sided copper foil, 22, 23 ... BGA pads, 24 ... multiple vias, 25a, 25b ... solder resist, 30 ... semiconductor package.

Claims (5)

  A chip mounting area having a plurality of wiring patterns alternately stacked via an insulating layer and having a semiconductor chip mounted on one surface thereof, and a chip mounting area including the chip mounting area and slightly larger than the chip mounting area BGA type multilayer wiring board having a plurality of BGA pads to which signal lines and power / ground lines are to be connected on the outside, and connected to the wiring pattern inside on the other side The signal line is not connected to the BGA pad located in the area corresponding to the chip mounting area on the other side, and the power / ground line is connected to the BGA pad corresponding to the area outside the chip mounting area on the other side. A BGA type multilayer wiring board, wherein a signal line is connected to a BGA pad located in a region to be operated.   The BGA pad to which the signal line is connected is connected to one of the wiring patterns via one connection via, and the BGA pad to which the power / ground line is connected is connected to the wiring pattern via a plurality of connection vias. 2. The BGA type multilayer wiring board according to claim 1, wherein the BGA type multilayer wiring board is connected to the other one.   The wiring pattern in which the BGA pad to which the signal line is connected is connected through one connection via is connected to an inner wiring pattern in a region corresponding to the chip mounting area. Item 3. A BGA type multilayer wiring board according to Item 2.   The BGA type multilayer wiring board according to claim 1, which has a thickness of 500 μm or less.   A chip mounting area having a plurality of wiring patterns alternately stacked via an insulating layer and having a semiconductor chip mounted on one surface thereof, and a chip mounting area including the chip mounting area and slightly larger than the chip mounting area A BGA type multilayer wiring board provided with a plurality of BGA pads to which signal lines and power / ground lines are to be connected on the outside, and connected to the wiring pattern inside on the other side, In a BGA type semiconductor package comprising a semiconductor chip mounted on the chip mounting area of the BGA type multilayer wiring board, a signal line is connected to a BGA pad located in a region corresponding to the chip mounting area on the other side. Not connected, power / ground wire connected, area corresponding to the area outside the chip mounting area on the other side The BGA pads located, BGA type semiconductor package, wherein a signal line is connected.

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