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TW201911508A - 電子封裝件 - Google Patents

電子封裝件 Download PDF

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Publication number
TW201911508A
TW201911508A TW106126048A TW106126048A TW201911508A TW 201911508 A TW201911508 A TW 201911508A TW 106126048 A TW106126048 A TW 106126048A TW 106126048 A TW106126048 A TW 106126048A TW 201911508 A TW201911508 A TW 201911508A
Authority
TW
Taiwan
Prior art keywords
layer
electronic component
circuit
active surface
electronic
Prior art date
Application number
TW106126048A
Other languages
English (en)
Inventor
何祈慶
蔡瀛洲
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW106126048A priority Critical patent/TW201911508A/zh
Priority to CN201710753942.0A priority patent/CN109390306A/zh
Priority to US15/869,249 priority patent/US20190043819A1/en
Publication of TW201911508A publication Critical patent/TW201911508A/zh

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Abstract

一種電子封裝件，係包括有電子件、形成於該電子元件上之線路重佈結構、結合至該線路重佈結構上之導電柱以及供該導電柱接置之線路重佈層，以供該電子元件透過該線路重佈結構與導電柱而電性連接該線路重佈層，使符合微小化需求之電子元件能進一步電性連接至外部裝置。

Description

電子封裝件
本發明係有關一種封裝結構，尤指一種符合微小化需求之電子封裝件。
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態。為滿足半導體裝置之高積集度(Integration)、微型化(Miniaturization)以及高電路效能等需求，遂而發展出覆晶(Flip chip)接合封裝技術。
覆晶接合封裝技術係為一種以晶片(或其他半導體結構)的作用面上形成複數金屬凸塊，以藉由該些金屬凸塊使該晶片的作用面得電性連接至外部電子裝置或封裝基板，此種設計可大幅縮減整體封裝件的體積。
如第1A及1B圖所示，於習知覆晶式半導體封裝件1之製程中，係先將一半導體晶片11藉由複數銲錫凸塊13結合至一封裝基板10上，再形成底膠12於該半導體晶片11與該封裝基板10之間，以包覆該些銲錫凸塊13。之後，於該封裝基板10下側植設複數銲球14以接置於電子產品之運算主板(major board)9上。
此外，目前在摩爾定律的驅策下，該半導體晶片11的尺寸係朝微小化發展，且其線路更精細(fine pitch)。
惟，習知半導體封裝件1中，用以電性連接該半導體晶片11與該運算主板9的封裝基板10，其上線路尺寸及用以電性外接的銲球14之尺寸因製程限制無法依據摩爾定律的規劃進行同於晶片尺寸等級的縮小。
再者，習知覆晶式半導體封裝件1中，該半導體晶片11之側面11c係裸露於外界，使該半導體晶片11之結構強度較低，故於取放該半導體封裝件1至適合位置以進行表面貼銲技術(Surface Mount Techno1ogy，簡稱SMT)時，易使該半導體晶片11產生裂損(Crack)，進而降低產品之良率。
另外，習知覆晶式半導體封裝件1中，該封裝基板10係為一般有機基板或核心基板，其受限於製程，而無法製作線寬線距(pitch)小於130微米(um)之線路。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：電子元件，係具有相對之作用面與非作用面；線路重佈結構，係形成於該電子元件之作用面上，且電性連接該電子元件；複數導電柱，係結合並電性連接該線路重佈結構；線路重佈層，係結合並電性連接該複數導電柱，以令該導電柱一端連接該線路重佈結構，且該導 電柱之另一端連接該線路重佈層；包覆層，係結合至該電子元件上；以及封裝層，係結合至該包覆層上。
本發明亦提供一種電子封裝件，係包括：電子元件，係具有相對之作用面、非作用面及鄰接該作用面與非作用面之側面；包覆層，係結合於該電子元件之側面；線路重佈結構，係形成於該電子元件之作用面及該包覆層上，並電性連接該電子元件；複數導電柱，係結合並電性連接該線路重佈結構；線路重佈層，係結合並電性連接該複數導電柱，以令該導電柱一端連接該線路重佈結構，且該導電柱之另一端連接該線路重佈層；以及封裝層，係形成於該線路重佈層上且包覆該包覆層、線路重佈結構與該複數導電柱。
前述之電子封裝件中，該線路重佈層復結合複數導電元件，以外接電子裝置。例如，該線路重佈層用以結合該導電元件之線距係至少為150um。
前述之電子封裝件中，該線路重佈結構係包含有一電性連接該電子元件之線路層，且該線路層結合該些導電柱，其中，該線路層用以結合該導電柱之線距係至少為100um。
前述之電子封裝件中，該電子元件復具有鄰接該作用面與非作用面之側面，且於該電子元件之側面上接觸形成有包覆層。例如，該包覆層係直接接觸該線路重佈結構，以令該線路重佈結構結合於該電子元件之作用面及該包覆層上；或者，該包覆層復形成於該電子元件之非作用面上。 進一步，復包括形成於該線路重佈層上以包覆該包覆層之封裝層，且於一實施例中，該封裝層復形成於該電子元件之非作用面上，又於一實施例中，該封裝層係直接接觸該包覆層，或於一實施例中，該電子元件之非作用面或該包覆層之頂面係外露出該封裝層之上表面。
由上可知，本發明之電子封裝件，主要藉由兩次扇出型(fan out)之線路重佈層(RDL)之設計(即形成於電子元件上之線路重佈結構及供該導電柱接置之線路重佈層)，使具精細(fine pitch)線路而符合微小化需求之電子元件能藉由該線路重佈層接置及電性連接至外部電子裝置。
再者，藉由該包覆層與該封裝層包覆該電子元件之外側，以提升該電子元件之結構強度，故相較於習知技術，於後續進行表面貼銲技術或運送該電子封裝件時，能避免該電子元件產生裂損，因而能提升產品之良率。
1‧‧‧半導體封裝件
10‧‧‧封裝基板
11‧‧‧半導體晶片
12‧‧‧底膠
13‧‧‧銲錫凸塊
14‧‧‧銲球
2‧‧‧電子封裝件
2a‧‧‧整版面基板
20‧‧‧電子元件
20’‧‧‧間隔部
20a‧‧‧作用面
20b‧‧‧非作用面
20c‧‧‧側面
200‧‧‧電極墊
201‧‧‧鈍化層
21‧‧‧線路重佈層
210‧‧‧介電層
211‧‧‧第一線路層
212‧‧‧第二線路層
213‧‧‧導電孔
214‧‧‧保護層
22,32‧‧‧封裝層
23‧‧‧導電元件
24‧‧‧溝道
25,35‧‧‧包覆層
26‧‧‧切割路徑
27‧‧‧線路重佈結構
271‧‧‧線路層
273‧‧‧保護保護層
28‧‧‧導電體
280‧‧‧導電材
281‧‧‧導電柱
30‧‧‧承載板
300‧‧‧離形層
31‧‧‧導電層
8‧‧‧支撐件
80‧‧‧離型層
9‧‧‧運算主板
第1A至1B圖係為習知覆晶式半導體封裝件之製法之剖視示意圖；第2A至2H圖係為本發明之電子封裝件之製法之剖視示意圖；第3A至3C圖係為對應第2H圖之不同實施例之剖視示意圖；以及第4A至4C圖係為本發明之線路重佈層之製程之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明之電子封裝件2之製法之剖視示意圖。
如第2A圖所示，提供一整版面基板2a，該整版面基板2a包含複數電子元件20與位於相鄰兩電子元件20之間的間隔部20’。
於本實施例中，該電子元件20具有作用面20a與相對該作用面20a之非作用面20b，該作用面20a上具有複數電極墊200，並於該作用面20a與該些電極墊200上形成有一鈍化層201，且令該些電極墊200外露出該鈍化層201。
再者，該電子元件20係為主動元件、被動元件或其組 合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。具體地，於本實施例中，該整版面基板2a係為矽晶圓，且該電子元件20係為半導體晶片。
如第2B圖所示，結合一支撐件8於該鈍化層201上。於本實施例中，該鈍化層201與該支撐件8之間係可形成有離型層80，以利於後續剝離該支撐件8製程時避免造成損害，而能提升產品良率。
如第2C圖所示，以例如切割或蝕刻等方式形成溝道24於該間隔部20’上，使各該電子元件20形成有側面20c，且該側面20c係鄰接該作用面20a與非作用面20b。
於本實施例中，係移除該間隔部20’之全部材質，以形成該溝道24，且可選擇性執行研磨該電子元件20之非作用面20b之薄化製程。
如第2D圖所示，形成一包覆層25於該溝道24中與各該電子元件20上，以覆蓋該電子元件20之側面20c與非作用面20b。
於本實施例中，該包覆層25係填滿該溝道24，使該包覆層25環設於該電子元件20之側面20c，且該包覆層25係為絕緣材，如可固化之液態模封材(liquid molding compound)、乾膜材(dry film)、光阻材(photoresist)或防銲層(solder mask)。
如第2E圖所示，移除該支撐件8與該離型層80，以外露該些電極墊200、該鈍化層201及該包覆層25。
如第2F圖所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，以接觸形成一扇出型(fan out)之線路重佈結構27於該鈍化層201與該包覆層25上，且令該線路重佈結構27電性連接該些電極墊200。接著，形成複數導電體28於該線路重佈結構27上。
於本實施例中，該線路重佈結構27係包括一形成於該鈍化層201上且電性連接該些電極墊200之線路層271、及一覆蓋該線路層271且外露部分該線路層271之絕緣保護層273，以供該些導電體28形成於該線路層271之外露表面上而電性連接該線路層271。應可理解地，該線路重佈結構27之層數可依需求設定，例如可形成至少一介電層(圖略)於該鈍化層201與該線路層271上，再形成其它線路層於該介電層上，之後才形成該絕緣保護層273於該介電層與最外側線路層上。因此，可依實際需求設計該線路重佈結構27之態樣，並不限於上述。
再者，該線路層271用以結合該導電體28之線距(pitch)係至少為100um。
又，於本實施例中，該導電體28係例如包含有如銅柱之導電柱281及設於該導電柱281端部上如銲錫之導電材280，或其它適合構造態樣。
另外，該導電柱281之熔點與該導電材280之熔點不同，使該導電柱281之高度於回銲後保持不變，而該導電材280之高度於回銲後會改變。
具體地，一般覆晶式結構所用之銲錫材，如第1A圖所示之習知銲錫凸塊13，因習知銲錫凸塊13之體積及高 度之平均值與公差控制不易，將難以達到細間距的要求。更詳言之，當習知銲錫凸塊13之體積平均值偏小或高度平均值偏低時，不利於封裝之底膠(underfill)填充，易導致爆板；另一方面，當習知銲錫凸塊13之體積平均值偏大或高度平均值偏高時，容易發生造成短路之接點橋接(bridge)現象，故當習知銲錫凸塊13之體積及高度之公差大時，不僅接點容易產生缺陷，導致電性連接品質不良，且習知銲錫凸塊13所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良，導致接點應力(stress)不平衡而容易造成半導體晶片11損壞。
因此，本發明之導電體28藉由銅材或熔點高於銲錫之材質製作該導電柱281，由於該導電柱281不會於回銲製程中改變形狀，可控制該導電體28的高度與體積，故能避免上述習知銲錫凸塊13所產生之缺失，有效達到細間距的要求。
如第2G圖所示，進行切單製程，係沿切割路徑26切割該整版面基板2a，以分離各該電子元件20。
於本實施例中，該切割路徑26係對應該溝道24之路徑，且該切割路徑26之寬度係小於該溝道24之寬度，使該包覆層25保留於該電子元件20之側面20c上。
如第2H圖所示，將該電子元件20以其作用面20a藉由複數導電體28結合至一線路重佈層21上，再形成一封裝層22於該線路重佈層21上以包覆該包覆層25與該些導電體28，使該封裝層22直接接觸該線路重佈結構27之側 面與底面、該導電體28及該線路重佈層21。
於本實施例中，該線路重佈層21係為扇出型(fan out)，且其上下側分別用以結合及電性連接該些導電體28與複數導電元件23，以於後續製程中，藉由該些導電元件23結合至一如電路板(如第1B圖所示之運算主板9)之電子裝置上，其中，該線路重佈層21用以結合該導電元件23之線距係至少為150um。
再者，該些導電元件23係可包含有銲錫凸塊、銅柱、或其它適合構造態樣。
又，於其它實施例中，如第3A圖所示，可藉由移除部分封裝層，使該包覆層25之頂面外露於該封裝層32上表面，例如，該包覆層25之頂面齊平該封裝層32上表面。或者，如第3B圖所示，可藉由移除部分封裝層與包覆層，使該電子元件20之非作用面20b外露於該封裝層32上表面與該包覆層35之頂面，例如，該電子元件20之非作用面20b齊平該包覆層35之頂面及該封裝層32上表面。
另外，如第3C圖所示，亦可先藉由移除部分包覆層，使該電子元件20之非作用面20b外露於該包覆層35之頂面(例如，該電子元件20之非作用面20b齊平該包覆層35之頂面)，再以該封裝層22包覆該電子元件20之非作用面20b與該包覆層35之頂面，使該電子元件20之非作用面20b接觸該封裝層22。
另一方面，該線路重佈層21之製程係如第3A至3C圖所示。首先，於一承載板30之相對兩側上藉由導電層 31電鍍形成第一線路層211，再以壓合方式形成介電層210(或以光阻方式形成鈍化層)於該承載板30上以覆蓋該第一線路層211，之後形成第二線路層212於該介電層210上，並形成複數導電孔213於該介電層210中，使該些導電孔213電性連接該第一線路層211與該第二線路層212。接著，藉由離形層300分離該承載板30兩側上之線路結構，並移除該導電層31。最後，於該介電層210之兩側上分別形成保護層214(或電性絕緣層)，並外露部分該第一線路層211與部分該第二線路層212，以完成該線路重佈層21之製作。
本發明之電子封裝件2係透過兩次扇出型(fan out)之線路重佈層(RDL)製程(即該線路重佈層21與該線路重佈結構27之線路層271)，使微小化晶片(即符合微小化之規格需求之電子元件20)能藉由該線路重佈層21接置及電性連接至電子裝置(如第1B圖所示之運算主板9)。
再者，藉由該包覆層25與該封裝層22包覆該電子元件20之雙層保護設計，以提升該電子元件20之強度，故於後續進行表面貼銲技術或運送該電子封裝件2時，能避免該電子元件20產生裂損，因而提升產品之良率。
本發明復提供一種電子封裝件2，係包括：一線路重佈層21、一電子元件20、一包覆層25,35以及一封裝層22,32。
所述之線路重佈層21係用以結合複數導電元件23。
所述之電子元件20係具有相對之作用面20a與非作用 面20b、及鄰接該作用面20a與該非作用面20b之側面20c。
所述之包覆層25,35係直接接觸地形成於該電子元件20之側面20c上。
該電子元件20之作用面20a及包覆層25,35上係形成有線路重佈結構27，以令該電子元件20得以藉由該線路重佈結構27並透過複數導電體28結合至該線路重佈層21上。
所述之封裝層22,32係形成於該線路重佈層21上以包覆該包覆層25,35與該些導電體28。
於一實施例中，該線路重佈層21藉由該些導電元件23外接一電子裝置，且該線路重佈層21用以結合該導電元件23之線距係至少為150um。
於一實施例中，該線路重佈結構27係包括一電性連接該電子元件20之線路層271，且該線路層271用以結合該導電體28之線距係至少為100um。
於一實施例中，該包覆層25,35係直接接觸該線路重佈結構27。
於一實施例中，該包覆層25復形成於該電子元件20之非作用面20b上。
於一實施例中，該封裝層22復形成於該電子元件20之非作用面20b上。
於一實施例中，該封裝層22,32係直接接觸該包覆層25,35。
綜上所述，本發明之電子封裝件，係藉由兩次扇出型 (fan out)之線路重佈層(RDL)之設計(即形成於電子元件上之線路重佈結構及供導電柱接置之線路重佈層)，使具精細(fine pitch)線路而符合微小化需求之電子元件能藉由該線路重佈層接置及電性連接至外部電子裝置。
再者，藉由該包覆層與封裝層之設計，以提升該電子元件之結構強度，因而能避免該電子元件產生裂損，故能提升該電子封裝件之良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (13)

  1. 一種電子封裝件，係包括：電子元件，係具有相對之作用面與非作用面；線路重佈結構，係形成於該電子元件之作用面上，且電性連接該電子元件；複數導電柱，係結合並電性連接該線路重佈結構；線路重佈層，係結合並電性連接該複數導電柱，以令該導電柱一端連接該線路重佈結構，且該導電柱之另一端連接該線路重佈層；包覆層，係結合至該電子元件上；以及封裝層，係結合至該包覆層上。
  2. 一種電子封裝件，係包括：電子元件，係具有相對之作用面、非作用面及鄰接該作用面與非作用面之側面；包覆層，係結合於該電子元件之側面；線路重佈結構，係形成於該電子元件之作用面及該包覆層上，並電性連接該電子元件；複數導電柱，係結合並電性連接該線路重佈結構；線路重佈層，係結合並電性連接該複數導電柱，以令該導電柱一端連接該線路重佈結構，且該導電柱之另一端連接該線路重佈層；以及封裝層，係形成於該線路重佈層上且包覆該包覆層、線路重佈結構與該複數導電柱。
  3. 如申請專利範圍第1或2項所述之電子封裝件，其中， 該線路重佈層結合複數導電元件，以外接電子裝置。
  4. 如申請專利範圍第3項所述之電子封裝件，其中，該線路重佈層用以結合該導電元件之線距係至少為150um。
  5. 如申請專利範圍第1或2項所述之電子封裝件，其中，該線路重佈結構係包含有電性連接該電子元件之線路層，且該線路層結合該些導電柱。
  6. 如申請專利範圍第5項所述之電子封裝件，其中，該線路層用以結合該導電柱之線距係至少為100um。
  7. 如申請專利範圍第1或2項所述之電子封裝件，其中，該電子元件復具有鄰接該作用面與非作用面之側面，且於該電子元件之側面上接觸形成有包覆層。
  8. 如申請專利範圍第7項所述之電子封裝件，其中，該包覆層係直接接觸該線路重佈結構，以令該線路重佈結構結合於該電子元件之作用面及該包覆層上。
  9. 如申請專利範圍第7項所述之電子封裝件，其中，該包覆層復形成於該電子元件之非作用面上。
  10. 如申請專利範圍第7項所述之電子封裝件，其中，該封裝層復形成於該線路重佈層上以包覆該包覆層。
  11. 如申請專利範圍第10項所述之電子封裝件，其中，該封裝層復形成於該電子元件之非作用面上。
  12. 如申請專利範圍第10項所述之電子封裝件，其中，該封裝層係直接接觸該包覆層。
  13. 如申請專利範圍第10項所述之電子封裝件，其中，該電子元件之非作用面或該包覆層之頂面係外露出該封裝層之上表面。
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