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TW201724380A - 電子封裝件及封裝用之基板 - Google Patents

電子封裝件及封裝用之基板 Download PDF

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TW201724380A
TW201724380A TW104144006A TW104144006A TW201724380A TW 201724380 A TW201724380 A TW 201724380A TW 104144006 A TW104144006 A TW 104144006A TW 104144006 A TW104144006 A TW 104144006A TW 201724380 A TW201724380 A TW 201724380A
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substrate
electrical contact
region
electronic package
layer
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TW104144006A
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TWI641087B (zh
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梁芳瑜
張宏憲
賴顗喆
林長甫
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矽品精密工業股份有限公司
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Priority to TW104144006A priority Critical patent/TWI641087B/zh
Priority to CN201610027579.XA priority patent/CN106920778B/zh
Priority to US15/063,592 priority patent/US10062651B2/en
Publication of TW201724380A publication Critical patent/TW201724380A/zh
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Abstract

一種封裝用之基板，係包括：具有相鄰接之第一區域及第二區域的基板本體、以及形成於該第二區域上之材料層，且該第一區域上具有複數電性接觸墊，以藉由該材料層之設計防止該基板本體翹曲。本發明復提供包含該基板之電子封裝件。

Description

電子封裝件及封裝用之基板
本發明係有關一種封裝結構，尤指一種電子封裝件及封裝用之基板。
隨著電子產業的蓬勃發展，許多高階電子產品都逐漸朝往輕、薄、短、小等高集積度方向發展，且隨著封裝技術之演進，晶片的封裝技術也越來越多樣化，半導體封裝件之尺寸或體積亦隨之不斷縮小，藉以使該半導體封裝件達到輕薄短小之目的。
第1圖係為習知封裝結構1之剖面示意圖。如第1圖所示，該封裝結構1係包括：一封裝基板10、一覆晶結合於該封裝基板10上之半導體晶片12、以及用以包覆該半導體晶片12之封裝膠體13。
所述之封裝基板10係具有複數電性接觸墊100，各該電性接觸墊100周圍形成有鈍化層101，且各該電性接觸墊100上形成有一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)102，如第1’及1”圖所示。
所述之半導體晶片12係藉由複數銲錫凸塊11結合於 各該電性接觸墊100上之凸塊底下金屬層102上。
惟，習知封裝結構1於封裝過程中，該封裝基板10係為整版面(即量產尺寸)，且該封裝基板10於佈設該半導體晶片12之位置周圍容易產生應力集中區域K(如第1A及1A’圖所示之角落處，其中，參考第1A’圖可知，越靠近角落，應力越集中，即圖中點的密度)，故於溫度循環(temperature cycle)或應力變化時，如通過回銲爐、或經歷落摔等製程或測試時，該封裝基板10與該半導體晶片12(或封裝膠體13)之間容易因熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)差異(Mismatch)，而使該封裝基板10容易發生翹曲(warpage)，進而導致發生植球(即封裝基板10下側之銲球14)掉落、銲球14不沾錫(non-wetting)或基板本體裂開等問題。
再者，翹曲的情況亦會造成該半導體晶片12發生碎裂，致使產品良率降低。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑒於上述習知技術之缺失，本發明提供一種封裝用之基板，係包括：基板本體，係具有相鄰接之第一區域及第二區域，且該第一區域上具有複數電性接觸墊；以及材料層，係形成於該第二區域上，以防止該基板本體翹曲。
本發明復提供一種電子封裝件，係包括：基板本體，係具有相鄰接之第一區域及第二區域，且該第一區域上具 有複數電性接觸墊；材料層，係形成於該第二區域上，以防止該基板本體翹曲；以及電子元件，係結合於該些電性接觸墊上。
前述之電子封裝件及其封裝用之基板中，該基板本體係為半導體板材、陶瓷材或有機材。
前述之電子封裝件及其封裝用之基板中，該基板本體中係具有複數電性連接該些電性接觸墊之導電穿孔。
前述之電子封裝件及其封裝用之基板中，該第二區域位於該基板本體之角落。
前述之電子封裝件及其封裝用之基板中，該材料層復形成於該第一區域中，使該第一區域分隔成至少二區塊。
前述之電子封裝件及其封裝用之基板中，該材料層之佈設位置係為該基板之應力集中區域。
前述之電子封裝件及其封裝用之基板中，該電性接觸墊周圍形成有鈍化層。例如，該鈍化層之材質與該材料層之材質相同。
前述之電子封裝件及其封裝用之基板中，該電性接觸墊上形成有凸塊底下金屬層。
前述之電子封裝件及其封裝用之基板中，該電性接觸墊復形成於該第二區域上。例如，該第二區域上之電性接觸墊外露或嵌埋於該材料層。
由上可知，本發明之電子封裝件及封裝用之基板中，主要藉由該材料層形成於該電子元件之預設位置周圍，以於封裝過程中，防止該基板本體翹曲，故相較於習知技術， 本發明之電子封裝件及基板能避免該基板本體發生植球掉落或裂開等問題。
再者，因能避免該基板本體發生翹曲的情況，故相較於習知技術，本發明之電子元件不會發生碎裂，因而能提升產品良率。
1‧‧‧封裝結構
10‧‧‧封裝基板
100‧‧‧電性接觸墊
101,201‧‧‧鈍化層
102,202,33‧‧‧凸塊底下金屬層
11‧‧‧銲錫凸塊
12‧‧‧半導體晶片
13‧‧‧封裝膠體
14‧‧‧銲球
2,3‧‧‧電子封裝件
2a‧‧‧基板
20,30’‧‧‧基板本體
200‧‧‧第一電性接觸墊
200’‧‧‧第二電性接觸墊
21,21’,21”‧‧‧材料層
22‧‧‧電子元件
220,320,32‧‧‧導電元件
23‧‧‧封裝層
30‧‧‧承載件
300‧‧‧導電穿孔
301‧‧‧絕緣層
31‧‧‧線路結構
310‧‧‧介電層
311‧‧‧線路層
312,312’‧‧‧絕緣保護層
9‧‧‧封裝基板
A‧‧‧第一區域
B‧‧‧第二區域
K‧‧‧應力集中區域
第1圖係為習知電子封裝件之剖面示意圖；第1’圖係為第1圖的局部放大圖；第1A圖係為第1圖的上視示意圖；第1A’圖係為第1A圖的應力分佈示意圖；第2A圖係為本發明之電子封裝件之第一實施例的剖面示意圖；第2A’圖係為第2A圖的局部放大圖；第2A”圖係為第2A圖的上視示意圖；第2B圖係為第2A”圖的另一實施例；第2B’圖係為第2B圖的另一實施例；第2B”圖係為第2A圖的另一實施例之上視示意圖；第3A至3E圖係為本發明之電子封裝件之第二實施例之製法的剖面示意圖；以及第3B’圖係為第3B圖的另一實施例。
以下係藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本創作可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本創作所能產生之功效及所能達成之目的下，均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「一」、「第一」、「第二」等之用語，亦僅為便於敘述之明瞭，而非用以限定本創作可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本創作可實施之範疇。
請參閱第2A、2A’、2A”、2B、2B’及2B”圖係為本發明之電子封裝件2之第一實施例的示意圖。
如第2A圖所示，所述之電子封裝件2係包括：一封裝用之基板2a、一結合於該基板2a上之電子元件22、以及一用以包覆該電子元件之封裝層23，其中，該基板2a係包含一基板本體20、以及一結合於該基板本體20上之材料層21。
所述之基板本體20係具有一第一區域A及位於該第一區域A周圍之複數第二區域B，且該第一區域A上具有複數第一電性接觸墊200，而該第二區域B上具有複數第 二電性接觸墊200’。
於本實施例中，該基板本體20係為陶瓷板材、絕緣板、金屬板或有機板材，即一般封裝基板。
再者，各該第一電性接觸墊200周圍形成有鈍化層201，且各該第一電性接觸墊200上形成有一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)202。
又，該些第二區域B係位於該基板本體20之角落，如第2A”圖所示。
所述之材料層21係形成於各該第二區域B上。
於本實施例中，形成該材料層21之材質係為氧化矽或氮化矽，且該材料層21未覆蓋該些第二電性接觸墊200’。
再者，該材料層21之材質亦可與該鈍化層201之材質相同，例如，該鈍化層201之材質係為聚亞醯胺(Polyimide，簡稱PI)、苯並環丁烯(Benezocy-clobutene，簡稱BCB)或聚對二唑苯(Polybenzoxazole，簡稱PBO)、環氧樹脂(epoxy)或聚合物(polymer)等，故能同時製作，以節省製作時間。
又，該材料層21之佈設位置係為該基板2a之應力集中區域。
所述之電子元件22係藉由複數導電元件220結合於該些第一電性接觸墊200之凸塊底下金屬層202上。
於本實施例中，該導電元件220係含有銲錫材料或銅凸塊，且該電子元件22係為主動元件、被動元件或其二者組合，其中，該主動元件係例如半導體晶片，而該被動元 件係例如電阻、電容及電感。
再者，該材料層21’亦可覆蓋該第二區域B之第二電性接觸墊200’，如第2B圖所示。或者，該些第二電性接觸墊200’除了前述嵌埋於該材料層21’中，亦可依需求外露於該材料層21’，如第2B’圖所示，使該電子元件22之部分結構覆蓋於該第二區域B上方並電性連接部分該第二電性接觸墊200’。
又，該基板2a可依需求設置複數個電子元件22，如第2B”圖所示。具體地，於設置該些電子元件22之前，該材料層21”復可形成於該第一區域A中，使該第一區域A分隔成兩個新的區塊(如第2B圖所示)，以於各該區塊上分別設有該些電子元件22，致使該材料層21’,21”之佈設位置係為該基板2a之應力集中區域。
另外，於第2A圖中，應可理解地，該電子元件22亦可藉由複數導電元件220結合於該些第二電性接觸墊200’上。
所述之封裝層23係為如環氧樹脂(epoxy)之封裝膠體或介電材。
本發明之電子封裝件2及其基板2a，係藉由該材料層21,21’,21”形成於該電子元件22佈設處之周圍(即置晶區周圍)，如第2A”圖所示之一個置晶區、或如第2B”圖所示之兩個置晶區，即該材料層21,21’,21”形成於該基板2a於封裝製程中之應力集中區域，以於封裝過程中，防止該基板本體20翹曲，故能避免該基板本體20發生植球掉落或 裂開等問題。具體地，當該基板本體20遇到溫度循環或應力變化時，如通過回銲爐、或經歷落摔等製程或測試，該基板本體20與該電子元件22(或封裝層23)之間不會因熱膨脹係數(CTE)差異而使該基板本體20發生翹曲(warpage)。
再者，因能避免該基板本體20發生翹曲的情況，故該電子元件22不會發生碎裂，因而能提升產品良率。
又，藉由該材料層21,21’,21”之設計，能保護落摔或其它應力集中狀況時，直接造成該基板本體20的碎裂。
另外，該基板本體20未整面鋪設該材料層21,21’,21”(或鈍化層201)，其原因在於若該基板本體20整面鋪設該材料層21,21’,21”(或鈍化層201)，會造黃光製程偏移、以及因鈍化層201偏移而產生之未潤濕(non-wetting)等問題。
第3A至3E圖係為本發明之電子封裝件3之第二實施例之製法的剖面示意圖。本實施例與第一實施例之差異在於該基板本體30’之態樣，其它結構大致相同，故以下詳細說明相異處，而不再贅述相同處。
如第3A圖所示，提供一承載件30，且自其表面向內延伸形成有複數導電柱以作為導電穿孔300。
於本實施例中，該承載件30係為如矽材、玻璃等之半導體板材，且該導電柱係為金屬柱，如銅柱。
再者，於製作該導電穿孔300時，先於該承載件30之表面上形成複數通孔，再形成一絕緣層301於該承載件 30與該通孔之孔壁上，之後將導電材(如銅材)填入該通孔中，以令該導電材形成該導電柱，且經由整平製程，使該導電柱之上端面齊平該絕緣層301之表面。
又，可依需求採用不同之製程製作該導電穿孔300，並不限於上述。
如第3B圖所示，形成一線路結構31於該承載件30之表面上。
於本實施例中，該線路結構31係包含複數介電層310、複數形成於該介電層310上之線路層311、以及一形成於最外層介電層310上之絕緣保護層312。
再者，最外層之該線路層311具有複數外露於該絕緣保護層312之第一電性接觸墊200及第二電性接觸墊200’，以於各該第一電性接觸墊200上結合如銲錫材料或銅凸塊之導電元件320，且可選擇性形成凸塊底下金屬層(UBM)202於各該第一電性接觸墊200上，以利於結合該導電元件320。
又，於對應各該第一電性接觸墊200周圍形成有鈍化層201，且於該承載件30角落之絕緣保護層312上形成有材料層21。
另外，於另一實施例中，如第3B’圖所示，該材料層21之材質與該鈍化層201之材質相同，故能同時製作，以節省製作時間。
如第3C圖所示，至少一電子元件22藉由該導電元件220,320設於該些第一電性接觸墊200上，使該電子元件 22電性連接該些第一電性接觸墊200。接著，形成一封裝層23於該絕緣保護層312上，以令該封裝層23包覆該電子元件22。
如第3D圖所示，研磨該承載件30之部分材質，以外露該絕緣層301與該導電穿孔300，以令該承載件30成為矽中介板(Through Silicon interposer，簡稱TSI)，俾令該承載件30與線路結構31作為基板本體30’。
接著，形成另一絕緣保護層312’於該基板本體30’下側，且該絕緣保護層312’外露該些導電穿孔300之下端面。之後，結合複數導電元件32於該些導電穿孔300之下端面上，且該些導電元件32電性連接各該導電穿孔300。
於本實施例中，該導電元件32係含有銲錫材料或銅凸塊，且可選擇性於該導電元件32下方形成有凸塊底下金屬層(UBM)33。
如第3E圖所示，後續即可將該電子封裝件3以其導電元件32設於一封裝基板9上。
本發明之電子封裝件3係藉由該材料層21之設計，以防止該基板本體30’翹曲，故能避免該基板本體30’發生植球掉落或裂開等問題，且能避免該電子元件22發生碎裂，因而能提升產品良率。
綜上所述，本發明之電子封裝件及封裝用之基板，主要藉由該材料層形成於該基板之置晶區周圍，以防止該基板本體翹曲，故能避免因基板本體翹曲所衍生之問題。
上述實施例僅例示性說明本發明之原理及其功效，而 非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
2a‧‧‧基板
20‧‧‧基板本體
200‧‧‧第一電性接觸墊
200’‧‧‧第二電性接觸墊
21‧‧‧材料層
22‧‧‧電子元件
220‧‧‧導電元件
23‧‧‧封裝層
A‧‧‧第一區域
B‧‧‧第二區域

Claims (22)

  1. 一種封裝用之基板，係包括：基板本體，係具有相鄰接之第一區域及第二區域，且該第一區域上具有複數電性接觸墊；以及材料層，係形成於該第二區域上，以防止該基板本體翹曲。
  2. 如申請專利範圍第1項所述之封裝用之基板，其中，該基板本體係為半導體板材、陶瓷材或有機材。
  3. 如申請專利範圍第1項所述之封裝用之基板，其中，該基板本體中係具有複數電性連接該些電性接觸墊之導電穿孔。
  4. 如申請專利範圍第1項所述之封裝用之基板，其中，該第二區域位於該基板本體之角落。
  5. 如申請專利範圍第1項所述之封裝用之基板，其中，該材料層復形成於該第一區域中，使該第一區域分隔成至少二區塊。
  6. 如申請專利範圍第1或5項所述之封裝用之基板，其中，該材料層之佈設位置係為該基板之應力集中區域。
  7. 如申請專利範圍第1項所述之封裝用之基板，其中，該電性接觸墊周圍形成有鈍化層。
  8. 如申請專利範圍第7項所述之封裝用之基板，其中，該鈍化層之材質與該材料層之材質相同。
  9. 如申請專利範圍第1項所述之封裝用之基板，其中，該電性接觸墊上形成有凸塊底下金屬層。
  10. 如申請專利範圍第1項所述之封裝用之基板，其中，該電性接觸墊復形成於該第二區域上。
  11. 如申請專利範圍第10項所述之封裝用之基板，其中，該第二區域上之電性接觸墊外露或嵌埋於該材料層。
  12. 一種電子封裝件，係包括：基板本體，係具有相鄰接之第一區域及第二區域，且該第一區域上具有複數電性接觸墊；材料層，係形成於該第二區域上，以防止該基板本體翹曲；以及電子元件，係結合於該些電性接觸墊上。
  13. 如申請專利範圍第12項所述之電子封裝件，其中，該基板本體係為半導體板材、陶瓷材或有機材。
  14. 如申請專利範圍第12項所述之電子封裝件，其中，該基板本體中係具有複數電性連接該些電性接觸墊之導電穿孔。
  15. 如申請專利範圍第12項所述之電子封裝件，其中，該第二區域位於該基板本體之角落。
  16. 如申請專利範圍第12項所述之電子封裝件，其中，該材料層復形成於該第一區域中，使該第一區域分隔成至少二區塊。
  17. 如申請專利範圍第12或16項所述之電子封裝件，其中，該材料層之佈設位置係為該基板之應力集中區域。
  18. 如申請專利範圍第12項所述之電子封裝件，其中，該電性接觸墊周圍形成有鈍化層。
  19. 如申請專利範圍第18項所述之電子封裝件，其中，該鈍化層之材質與該材料層之材質相同。
  20. 如申請專利範圍第12項所述之電子封裝件，其中，該電性接觸墊上形成有凸塊底下金屬層。
  21. 如申請專利範圍第12項所述之電子封裝件，其中，該電性接觸墊復形成於該第二區域上。
  22. 如申請專利範圍第21項所述之電子封裝件，其中，該第二區域上之電性接觸墊外露或嵌埋於該材料層。
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