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TW201806039A - 電子堆疊結構及其製法 - Google Patents

電子堆疊結構及其製法 Download PDF

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Publication number
TW201806039A
TW201806039A TW105125272A TW105125272A TW201806039A TW 201806039 A TW201806039 A TW 201806039A TW 105125272 A TW105125272 A TW 105125272A TW 105125272 A TW105125272 A TW 105125272A TW 201806039 A TW201806039 A TW 201806039A
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Taiwan
Prior art keywords
substrate
electronic
stack structure
passive
passive element
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TW105125272A
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English (en)
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TWI594338B (zh
Inventor
邱志賢
石啟良
洪家惠
陳嘉揚
張月瓊
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矽品精密工業股份有限公司
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Priority to TW105125272A priority Critical patent/TWI594338B/zh
Priority to CN201610705783.2A priority patent/CN107708300B/zh
Priority to US15/352,942 priority patent/US20180047711A1/en
Application granted granted Critical
Publication of TWI594338B publication Critical patent/TWI594338B/zh
Publication of TW201806039A publication Critical patent/TW201806039A/zh

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    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
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    • H05K1/00—Printed circuits
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Abstract

一種電子堆疊結構，係包括：第一基板、設於該第一基板上之被動元件與第一電子元件、以及設於該被動元件上之第二基板，藉由該第二基板透過該被動元件而堆疊至該第一基板上，以利用該些被動元件的高度與體積，使該第一與第二基板之間的距離得以固定。本發明復提供該電子堆疊結構之製法。

Description

電子堆疊結構及其製法
本發明係關於一種堆疊結構，特別是關於一種電子堆疊結構及其製法。
隨著近年來可攜式電子產品的蓬勃發展，各類相關產品逐漸朝向高密度、高性能以及輕、薄、短、小之趨勢發展，為因應此趨勢，半導體封裝業界遂開發各態樣的堆疊封裝(package on package，簡稱PoP)技術，以期能符合輕薄短小與高密度的要求。
如第1圖所示，係為習知封裝堆疊結構1的剖視示意圖。如第1圖所示，該封裝堆疊結構1包括：具有相對之第一表面11a及第二表面11b之第一基板11；覆晶結合該第一基板11之第一半導體晶片10；形成於該第一基板11之電性接觸墊111上之銲錫柱13；形成於該第一基板11上以包覆該第一半導體晶片10與銲錫柱13之第一封裝膠體14；設於該第二表面11b之植球墊112上之銲球114；藉由銲錫柱13疊設於該第一基板11上之第二基板12；以打線方式結合於該第二基板12上之第二半導體晶片 15a,15b；以及形成於該第二基板12上以包覆該第二半導體晶片15a,15b之第二封裝膠體16。
惟，習知封裝堆疊結構1中，由於該第一與第二基板11,12間係以銲錫柱13作為支撐與電性連接之元件，而隨著電子產品的接點(即I/O)數量愈來愈多，在封裝件的尺寸大小不變的情況下，各該銲錫柱13間的間距需縮小，致使容易發生橋接(bridge)的現象，因而造成產品良率過低及可靠度不佳等問題，致使無法應用於更精密之細間距產品。
尤其是，該銲錫柱13於回銲後之體積及高度之公差大，即尺寸變異不易控制，致使不僅接點容易產生缺陷(例如，於回銲時，該銲錫柱13會先變成軟塌狀態，同時於承受上方第二基板12的重量後，該銲錫柱13容易塌扁變形，繼而與鄰近該銲錫柱13橋接)，導致電性連接品質不良，且該銲錫柱13所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良，導致接點應力(stress)不平衡而容易造成該第一基板11與第二基板12之間呈傾斜接置，甚至產生接點偏移之問題。
再者，若以銅柱取代該銲錫柱13作為支撐，雖可避免傾斜接置之問題，但銅柱之成本較高，故不符合經濟效益。
又，由於該些銲錫柱13會佔用該第一基板11與第二基板12之佈設空間，致使於該第一基板11與第二基板12上難以增加被動元件之數量，因而該封裝堆疊結構1難以符合高性能之需求；若要於該第一基板11與第二基板12 上增加晶片或被動元件之數量，則需增加該第一基板11與第二基板12之佈設面積，致使該封裝堆疊結構1不符合朝輕、薄、短、小方向設計之趨勢。
另外，設於該第一基板11或第二基板12上之被動元件(圖未示)，其接地部(ground)需透過銲錫柱13連結至系統接地部(ground)，致使傳遞路徑過長，而降低該封裝堆疊結構1的電氣特性。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種電子堆疊結構，係包括：第一基板；第二基板，係藉由複數被動元件堆疊於該第一基板上；以及電子元件，係設於該第一基板及/或第二基板上。
本發明復提供一種電子堆疊結構之製法，係包括：提供第一基板及第二基板；以及將該第二基板間隔複數被動元件堆疊於該第一基板上，其中，於該第一基板或第二基板上設有至少一電子元件。
前述之電子堆疊結構及其製法中，該電子元件係藉由複數導電凸塊設於該第一基板或第二基板上。
前述之電子堆疊結構及其製法中，該被動元件電性連接該第一基板或第二基板。
前述之電子堆疊結構及其製法中，該被動元件未電性連接該第一基板與第二基板。
前述之電子堆疊結構及其製法中，該被動元件係位於該第一基板之角落處。
前述之電子堆疊結構及其製法中，復包括形成封裝層於該第一基板與第二基板之間，且該封裝層包覆該些被動元件。
由上可知，本發明之電子堆疊結構及其製法中，係將該第二基板間隔該被動元件而堆疊至該第一基板上，使該第一與第二基板之間的距離固定，故相較於習知技術，本發明之電子堆疊結構無需進行如回銲銲錫柱之製程，而透過維持該些被動元件的高度與體積，以避免電性連接品質不良、共面性不良、傾斜接置等問題，因而不僅可提高產品良率，且無須使用成本較高的銅柱。
再者，藉由該被動元件作為支撐件，因而不需增加該第一基板與第二基板之佈設面積，即可增加被動元件之數量，故相較於習知技術，本發明之電子堆疊結構不僅能符合高性能之需求，且能符合朝輕、薄、短、小方向設計之趨勢。
另外，該被動元件作為支撐件，使該被動元件的接地部能透過較短路徑連結至系統接地部，故相較於習知透過銲錫柱之較長路徑，該電子堆疊結構能提供絕佳的電氣特性。
1‧‧‧封裝堆疊結構
10‧‧‧第一半導體晶片
11,21‧‧‧第一基板
11a‧‧‧第一表面
11b‧‧‧第二表面
111‧‧‧電性接觸墊
112‧‧‧植球墊
114‧‧‧銲球
12,22‧‧‧第二基板
13‧‧‧銲錫柱
14‧‧‧第一封裝膠體
15a,15b‧‧‧第二半導體晶片
16‧‧‧第二封裝膠體
2,2’,4,4’,4”‧‧‧電子堆疊結構
20‧‧‧第一電子元件
200,400‧‧‧導電凸塊
210,220‧‧‧線路層
23,40b‧‧‧被動元件
24,44‧‧‧封裝層
40,40’‧‧‧第二電子元件
40a‧‧‧主動元件
第1圖係為習知封裝堆疊結構之剖面示意圖；第2A至2C圖係為本發明之電子堆疊結構之製法之剖 面示意圖；第3A至3G圖係為第2A圖(省略電子元件)之不同態樣之上視示意圖；其中，第3B圖係為局部上視示意圖；以及第4A至4C圖係為本發明之電子堆疊結構之其它實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2C圖係為本發明之電子堆疊結構之製法之剖面示意圖。
如第2A圖所示，提供一第一基板21，且該第一基板 21上設有至少一第一電子元件20與複數被動元件23。
於本實施例中，該第一基板21係為線路板，其具有複數線路層210。應可理解地，該第一基板21亦可為其它承載件，並不限於上述。
再者，該第一電子元件20係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該第一電子元件20係藉由複數導電凸塊200以覆晶方式設於該第一基板21上側之線路層210上，例如，該導電凸塊200係為銲錫材料。或者，該第一電子元件20可藉由複數銲線(圖略)以打線方式電性連接該第一基板21上側之線路層210。
又，該被動元件23係例如電阻、電容及電感，且該被動元件23可選擇性地電性連接或未電性連接該第一基板21。具體地，該被動元件23係以去耦合電容(decoupling capacitor)為例。
如第2B圖所示，將一第二基板22結合至該被動元件23上，使該第二基板22藉由該些被動元件23堆疊於該第一基板21上，以形成電子堆疊結構2。
於本實施例中，該第二基板22可例如為矽中介板、線路板、亦或封裝件，且該被動元件23可選擇性地電性連接或未電性連接該第二基板22(其線路層220)。例如，當該被動元件23沒有電性連結該第一基板21及第二基板22時，該被動元件23可視為僅具有支撐功能之虛設(dummy)電子元件。
再者，該被動元件23之佈設可依需求作配置。如第3A圖所示，係配合該第二基板22之重量作配置，以於該第一基板21之角落處或重量分佈不均處(如位於基板的1/4等分位置等之不同位置)佈設被動元件23；或者，如第3B至3G圖所示，可依該電子堆疊結構2之應力分佈作配置，以於該第一基板21之單一角落處佈設複數被動元件23，亦即，該電子堆疊結構2之應力集中於角落，故選擇性於角落處設置複數被動元件23，藉以達到平衡應力，以減少該電子堆疊結構2之翹曲。
如第2C圖所示，形成一封裝層24於該第一基板21上側與該第二基板22下側之間，使該封裝層24包覆該第一電子元件20、該些被動元件23與該些導電凸塊200。
於本實施例中，該第一基板21之下側線路層上可形成有銲球(圖略)，以供接置如電路板或另一線路板之電子結構。
再者，如第4A圖所示之電子堆疊結構4，亦可設置第二電子元件40於該第二基板22上側，再形成另一封裝層44於該第二基板22上側，且該另一封裝層44包覆該第二電子元件40，其中，該第二電子元件40係為主動元件40a、被動元件40b或其二者組合等，該主動元件40a係例如半導體晶片，且該被動元件40b係例如電阻、電容及電感。例如，該主動元件40a係藉由複數導電凸塊400以覆晶方式設於該第二基板22上側之線路層220上，且該導電凸塊400係為銲錫材料；或者，該主動元件40a可以打線方式 電性連接該第二基板22。
又，如第4B圖所示之電子堆疊結構4’，該第二電子元件40’亦可藉由複數導電凸塊400設於該第二基板22下側之線路層220上，其製程係先將第二電子元件40’設於該第二基板22下側，再將設有該第二電子元件40’之第二基板22接置於被動元件23上。
另外，如第4C圖所示之電子堆疊結構4”，係同時採用第4A及4B圖之第二電子元件40,40’之佈設。
應可理解地，除了該被動元件23之外，該第一基板21與第二基板22之間復可增設如銲錫柱、銅核球或其它導體元件的支撐件(圖略)，其可電性連接(或不電性連接)該第一基板21或第二基板22。
另外於其它實施例中，亦可先將被動元件23接置於第二基板22下表面，再將結合有該被動元件23之第二基板22間隔該被動元件23而接置於該第一基板21上。此外，可選擇於該第一基板21及第二基板22上擇一設置電子元件或同時設置電子元件(如第一電子元件20及第二電子元件40)。
本發明之製法中，係於該第一基板21與第二基板22之間藉由該被動元件23作為支撐(及電性連接)之元件，故隨著電子產品的接點(即I/O)數量愈來愈多，在封裝件的尺寸大小不變的情況下，各該被動元件23間的間距縮小後，係不會發生橋接(bridge)的現象，因而能提高產品良率及可靠度，使該電子堆疊結構2,2’,4,4’,4”得以應 用於更精密之細間距產品。
尤其是，本發明之製法係藉由該第二基板22直接接觸結合至該被動元件23上，因而該電子堆疊結構2,2’,4,4’,4”無需進行回銲銲錫柱之製程，故能維持該些被動元件23的高度與體積，使該第二基板22與該第一基板21之間的距離固定。因此，該電子堆疊結構2,2’,4,4’,4”能維持良好之電性連接品質，且該些被動元件23所排列成之柵狀陣列(grid array)之共面性(coplanarity)良好，因而接點應力(stress)保持平衡而不會造成該第一與第二基板21,22之間呈傾斜接置，以避免產生接點偏移之問題。
再者，由於該第二基板22與該第一基板21之間的距離固定，故若於該第一基板21與第二基板22之間增設銲錫柱，即使進行回銲該銲錫柱之製程，仍可控制該些銲錫柱的高度與體積，以於回銲該些銲錫柱後，該些銲錫柱所構成之接點仍可維持良好之電性連接品質，且該些銲錫柱所排列成之柵狀陣列之共面性良好，因而接點應力保持平衡而不會造成該第一與第二基板21,22之間呈傾斜接置，以避免產生接點偏移之問題。
又，藉由該被動元件23作為支撐件，因而不需增加該第一基板21與第二基板22之佈設面積，即可增加被動元件之數量，故該電子堆疊結構2,2’,4,4’,4”不僅能符合高性能之需求，且能符合朝輕、薄、短、小方向設計之趨勢。
另外，該被動元件23作為支撐件，使該被動元件23的接地部(ground)能透過最短路徑(亦即直接連接該第一基板21之線路層210與第二基板22之線路層220)連結至該第一電子元件20與系統接地部(ground)，故相較於習知透過銲錫柱之較長路徑，該電子堆疊結構2,2’,4,4’,4”能提供絕佳的電氣特性。
本發明提供一種電子堆疊結構2,2’,4,4’,4”，其包括：第一基板21、設於該第一基板21上之被動元件23、設於該被動元件23上之第二基板22、設於該第一基板21上之第一電子元件20、設於該第二基板22上之第二電子元件40,40’、以及設於該第一基板21與第二基板22之間的封裝層24。
所述之第二基板22係藉由該些被動元件23堆疊於該第一基板21上。
所述之封裝層24係包覆該些被動元件23。
於一實施例中，該第一電子元件20係藉由複數導電凸塊200設於該第一基板21上。
於一實施例中，該第二電子元件40,40’係藉由複數導電凸塊400設於該第二基板22上。
於一實施例中，該被動元件23電性連接該第一基板21及/或第二基板22。
於一實施例中，該被動元件23未電性連接該第一基板21與第二基板22。
於一實施例中，該被動元件23係設於該第一基板21 之角落處。
綜上所述，本發明之電子堆疊結構及其製法，主要藉由將該第二基板透過該些被動元件而堆疊至該第一基板上，使該第二基板與該第一基板之間的距離固定，因而能維持良好之電性連接品質與共面性，且因接點應力保持平衡而不會造成傾斜接置。
再者，藉由該被動元件作為支撐件，因而不需增加該第一基板與第二基板之佈設面積，即可增加被動元件之數量，故本發明之電子堆疊結構不僅能符合高性能之需求，且能符合朝輕、薄、短、小方向設計之趨勢。
另外，該被動元件作為支撐件，使該被動元件的接地部能透過最短路徑連結至系統接地部，故該電子堆疊結構能提供絕佳的電氣特性。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子堆疊結構
20‧‧‧第一電子元件
21‧‧‧第一基板
22‧‧‧第二基板
220‧‧‧線路層
23‧‧‧被動元件

Claims (14)

  1. 一種電子堆疊結構，係包括：第一基板；第二基板，係藉由複數被動元件堆疊於該第一基板上；以及電子元件，係設於該第一基板及/或第二基板上。
  2. 如申請專利範圍第1項所述之電子堆疊結構，其中，該電子元件係藉由複數導電凸塊設於該第一基板上。
  3. 如申請專利範圍第1項所述之電子堆疊結構，其中，該電子元件係藉由複數導電凸塊設於該第二基板上。
  4. 如申請專利範圍第1項所述之電子堆疊結構，其中，該被動元件電性連接該第一基板或第二基板。
  5. 如申請專利範圍第1項所述之電子堆疊結構，其中，該被動元件未電性連接該第一基板與第二基板。
  6. 如申請專利範圍第1項所述之電子堆疊結構，其中，該被動元件係位於該第一基板之角落處。
  7. 如申請專利範圍第1項所述之電子堆疊結構，其中，該被動元件係位於該第一基板之重量分佈不均處。
  8. 一種電子堆疊結構之製法，係包括：提供第一基板及第二基板；以及將該第二基板間隔複數被動元件而堆疊於該第一基板上，其中，於該第一基板或第二基板上設有至少一電子元件。
  9. 如申請專利範圍第8項所述之電子堆疊結構之製法，其 中，該電子元件係藉由複數導電凸塊設於該第一基板上。
  10. 如申請專利範圍第8項所述之電子堆疊結構之製法，其中，該電子元件係藉由複數導電凸塊設於該第二基板上。
  11. 如申請專利範圍第8項所述之電子堆疊結構之製法，其中，該被動元件電性連接該第一基板或第二基板。
  12. 如申請專利範圍第8項所述之電子堆疊結構之製法，其中，該被動元件未電性連接該第一基板與第二基板。
  13. 如申請專利範圍第8項所述之電子堆疊結構之製法，其中，該被動元件係位於該第一基板之角落處。
  14. 如申請專利範圍第8項所述之電子堆疊結構之製法，復包括形成封裝層於該第一基板與第二基板之間，且該封裝層包覆該些被動元件。
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CN109786261A (zh) * 2018-12-29 2019-05-21 华进半导体封装先导技术研发中心有限公司 一种集成被动元件的封装方法及结构
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