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TW201508877A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TW201508877A
TW201508877A TW102129976A TW102129976A TW201508877A TW 201508877 A TW201508877 A TW 201508877A TW 102129976 A TW102129976 A TW 102129976A TW 102129976 A TW102129976 A TW 102129976A TW 201508877 A TW201508877 A TW 201508877A
Authority
TW
Taiwan
Prior art keywords
metal pillar
package substrate
package
electrical contact
semiconductor package
Prior art date
Application number
TW102129976A
Other languages
English (en)
Inventor
蕭承旭
王隆源
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW102129976A priority Critical patent/TW201508877A/zh
Priority to CN201310511469.7A priority patent/CN104425418A/zh
Priority to US14/085,101 priority patent/US20150054150A1/en
Publication of TW201508877A publication Critical patent/TW201508877A/zh

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    • H—ELECTRICITY
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    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01—ELECTRIC ELEMENTS
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Abstract

一種半導體封裝件及其製法，該半導體封裝件之製法係包括：提供第一封裝基板及第二封裝基板，該第一封裝基板具有複數第一電性接觸墊及形成其上的第一金屬柱，該第二封裝基板具有複數第二電性接觸墊、形成其上之第二金屬柱及設於該具有第二電性接觸墊之表面上的半導體晶片；接置該第一封裝基板於該第二封裝基板的第二金屬柱上，該第一封裝基板係以其複數第一電性接觸墊上的第一金屬柱對應電性連接該第二金屬柱；以及於該第一封裝基板與第二封裝基板之間形成包覆該第一金屬柱與第二金屬柱的封裝膠體。本發明能有效避免半導體封裝件之銲料橋接現象，進而增進產品良率與可靠度。

Description

半導體封裝件及其製法
本發明係有關於一種半導體封裝件及其製法，尤指一種層疊式的半導體封裝件及其製法。
隨著時代的進步，現今電子產品均朝向微型化、多功能、高電性及高速運作的方向發展，為了配合此一發展趨勢，半導體業者莫不積極研發能整合有複數個晶片之半導體裝置之堆疊式半導體封裝件(stacked package)，藉以符合電子產品之需求。
第1圖所示者，係習知之堆疊式半導體封裝件的剖面圖。
如圖所示，該堆疊式半導體封裝件係包括一第一半導體封裝件10、以及一堆疊於該第一半導體封裝件10上並與該第一半導體封裝件10電性連接之第二半導體封裝件11。
該第一半導體封裝件10係包括：一晶片承載件101；至少一安置於該晶片承載件101上之半導體晶片102；一提供該半導體晶片102電性連接至該晶片承載件101之第 一導電元件103；一位於該半導體晶片102上方之電路板104；一用以支撐並提供該電路板104電性連接至該晶片承載件101之銲球105；一形成於該晶片承載件101與該電路板104間，且用以包覆該半導體晶片102與銲球105，並外露出該電路板104上表面之封裝膠體106；以及一用以提供該半導體晶片102電性連接至外界之第二導電元件107。藉由將該電路板104上表面外露出該第一半導體封裝件10之外表面，以提供至少一第二半導體封裝件11電性連接至該電路板104，俾整合該第一半導體封裝件10與第二半導體封裝件11，形成一堆疊式半導體封裝件。
惟，由於該晶片承載件101與電路板104間係以銲球105做為支撐與電性連接，隨著電子產品的I/O數量愈來愈多，在封裝件的尺寸大小不變的情況下，銲球105與銲球105間的間距必須縮小，導致容易使得發生銲料橋接的現象，進而造成產品良率過低及可靠度不佳等問題。
因此，如何避免上述習知技術中之種種問題，實已成為目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件之製法，係包括：提供第一封裝基板及第二封裝基板，該第一封裝基板具有相對之第一表面與第二表面，該第一表面具有複數第一電性接觸墊及形成於其上的第一金屬柱，該第二封裝基板具有相對之第三表面與第四表面，該第三表面具有複數第二電性接觸墊、形成於該第二電性 接觸墊上之第二金屬柱及設於該第三表面上的半導體晶片；接置該第一封裝基板於該第二封裝基板的第二金屬柱上，使該第一封裝基板之第一金屬柱對應電性連接該第二金屬柱；以及於該第一封裝基板與第二封裝基板之間形成包覆該第一金屬柱與第二金屬柱的封裝膠體。
於一具體實施例中，該第一金屬柱上復形成有銲料凸塊，以電性連接該第二金屬柱；或者，該第二金屬柱上復形成有銲料凸塊，以電性連接該第一金屬柱。
於前述之半導體封裝件之製法中，於形成該封裝膠體後，復包括於該第二封裝基板之第四表面上形成複數導電元件，且於形成該封裝膠體後，復包括進行切單步驟。
依上所述之半導體封裝件之製法，於形成該封裝膠體後，復包括於該第一封裝基板之第二表面上接置電子元件，該電子元件係為晶片或封裝件，該第一金屬柱與第二金屬柱之粗細不同，且該第二金屬柱較該第一金屬柱粗。
本發明復提供一種半導體封裝件，係包括：第二封裝基板，係具有相對之第三表面與第四表面，該第三表面具有複數第二電性接觸墊及形成於該第二電性接觸墊上之第二金屬柱；半導體晶片，係接置於該第二封裝基板之第三表面上；銲料凸塊，係形成於該第二金屬柱上；第一封裝基板，係具有相對之第一表面與第二表面，該第一表面具有複數第一電性接觸墊及形成於該第一電性接觸墊上的第一金屬柱，且該第一封裝基板係以該第一金屬柱對應電性連接該銲料凸塊之方式接置於該第二封裝基板上；以及封 裝膠體，係形成於該第一封裝基板與第二封裝基板之間，以包覆該第一金屬柱與第二金屬柱。
於本發明之半導體封裝件中，復包括複數導電元件，係形成於該第二封裝基板之第四表面上，且復包括電子元件，係接置於該第一封裝基板之第二表面上。
所述之半導體封裝件中，該電子元件係為晶片或封裝件，該第一金屬柱與第二金屬柱之粗細不同，且該第二金屬柱較該第一金屬柱粗。
由上可知，本發明係二封裝基板上均形成有金屬柱，並藉由二金屬柱相互對應並電性連接以完成一半導體封裝件，由於該金屬柱所需的空間遠較習知之銲球小，因而可避免銲料橋接現象，並能有效增進產品良率與可靠度。
10‧‧‧第一半導體封裝件
101‧‧‧晶片承載件
102、23‧‧‧半導體晶片
103‧‧‧第一導電元件
104‧‧‧電路板
105‧‧‧銲球
106、24‧‧‧封裝膠體
107‧‧‧第二導電元件
11‧‧‧第二半導體封裝件
21‧‧‧第一封裝基板
21a‧‧‧第一表面
21b‧‧‧第二表面
211‧‧‧第一電性接觸墊
212‧‧‧第三電性接觸墊
213‧‧‧第一金屬柱
214、225‧‧‧銲料凸塊
22‧‧‧第二封裝基板
22a‧‧‧第三表面
22b‧‧‧第四表面
221‧‧‧第二電性接觸墊
222‧‧‧第四電性接觸墊
223‧‧‧第五電性接觸墊
224‧‧‧第二金屬柱
226‧‧‧第三金屬柱
231‧‧‧第四金屬柱
25‧‧‧導電元件
26‧‧‧電子元件
第1圖所示者係習知之堆疊式半導體封裝件的剖面圖；以及第2A至2G圖所示者係本發明之半導體封裝件及其製法的剖視圖，其中，第2A’圖係第2A圖之另一實施態樣，第2B’圖係第2B圖之另一實施態樣，第2C’圖係第2C圖之另一實施態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小 等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖所示者，係本發明之半導體封裝件及其製法的剖視圖，其中，第2A’圖係第2A圖之另一實施態樣，第2B’圖係第2B圖之另一實施態樣，第2C’圖係第2C圖之另一實施態樣。
如第2A圖所示，提供一第一封裝基板21，其具有相對之第一表面21a與第二表面21b，該第一表面21a與第二表面21b分別具有複數第一電性接觸墊211與複數第三電性接觸墊212，並於各該第一電性接觸墊211上依序形成第一金屬柱213與銲料凸塊214，形成該第一金屬柱213之材質可為銅。或者，如第2A’圖所示，僅形成該第一金屬柱213，而未形成該銲料凸塊214。
如第2B圖所示，提供一第二封裝基板22，其具有相對之第三表面22a與第四表面22b，該第三表面22a具有複數第二電性接觸墊221與複數第四電性接觸墊222，該第四表面22b具有複數第五電性接觸墊223，並於各該第二 電性接觸墊221上形成第二金屬柱224，且於各該第四電性接觸墊222上形成第三金屬柱226，形成該第二金屬柱224之材質可為銅。或者，如第2B’圖所示，於各該第二電性接觸墊221上依序形成該第二金屬柱224與銲料凸塊225。
如第2C圖所示，於該第三金屬柱226上覆晶接置半導體晶片23；於其他實施例中，亦可無需該第三金屬柱226，而直接以銲料凸塊(未圖示)進行覆晶電性連接。
或者，如第2C’圖所示，該半導體晶片23上先形成有第四金屬柱231，且該第四電性接觸墊222上未形成有該第三金屬柱226，該半導體晶片23係以該第四金屬柱231覆晶接置於該第四電性接觸墊222上。
如第2D圖所示，於該第二封裝基板22的第二金屬柱224上接置該第一封裝基板21，該第一封裝基板21係藉由該銲料凸塊214以該第一電性接觸墊211上的第一金屬柱213對應電性連接該第二金屬柱224，其中，接置該第一封裝基板21之方式可以小單元(unit)或大區塊(block)為單位，該大區塊例如包括有3x3陣列之單位。
如第2E圖所示，於該第一封裝基板21與第二封裝基板22之間形成包覆該第一金屬柱213、第二金屬柱224與半導體晶片23的封裝膠體24。
如第2F圖所示，於該第二封裝基板22之第五電性接觸墊223上形成複數導電元件25。
如第2G圖所示，進行切單步驟，並於該第一封裝基 板21之第三電性接觸墊212上接置電子元件26，該電子元件26係為封裝件；於其他實施例中，該電子元件26可為晶片。
要補充說明的是，該第一金屬柱213與第二金屬柱224之粗細可不同，或者，該第一金屬柱213係可與該第二金屬柱224同等粗細，但較佳實施例係該第二金屬柱224較該第一金屬柱213粗，以避免該第一金屬柱213與第二金屬柱224間的銲料向外溢流。
本發明復揭露一種半導體封裝件，係包括：第二封裝基板22，其具有相對之第三表面22a與第四表面22b，該第三表面22a具有複數第二電性接觸墊221，且該第二電性接觸墊221上形成有第二金屬柱224；半導體晶片23，係覆晶接置於該第二封裝基板22之第三表面22a上；銲料凸塊214，係形成於該第二金屬柱224上；第一封裝基板21，係具有相對之第一表面21a與第二表面21b，並接置於該第二封裝基板22的銲料凸塊214上，且係以其複數第一電性接觸墊211上的第一金屬柱213對應電性連接該銲料凸塊214；以及封裝膠體24，係形成於該第一封裝基板21與第二封裝基板22之間，以包覆該第一金屬柱213與第二金屬柱224。
於本實施例之半導體封裝件中，復包括複數導電元件25，係形成於該第二封裝基板22之第四表面22b上。
於前述之半導體封裝件中，復包括電子元件26，係接置於該第一封裝基板21之第二表面21b上，且該電子元件 26係為晶片或封裝件。
所述之半導體封裝件的第一金屬柱213與第二金屬柱224之粗細不同，且該第二金屬柱224較該第一金屬柱213粗。
綜上所述，相較於習知技術，本發明係於第一封裝基板與第二封裝基板上分別形成有第一金屬柱與第二金屬柱，並藉由該第一金屬柱對應並電性連接該第二金屬柱以完成一半導體封裝件，由於該第一金屬柱與第二金屬柱所需的空間遠較習知之銲球小，因此符合現今封裝件之細間距的趨勢，俾可避免銲料橋接現象，進而能有效增進產品良率與可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
21‧‧‧第一封裝基板
21a‧‧‧第一表面
21b‧‧‧第二表面
211‧‧‧第一電性接觸墊
212‧‧‧第三電性接觸墊
213‧‧‧第一金屬柱
214‧‧‧銲料凸塊
22‧‧‧第二封裝基板
22a‧‧‧第三表面
22b‧‧‧第四表面
221‧‧‧第二電性接觸墊
222‧‧‧第四電性接觸墊
223‧‧‧第五電性接觸墊
224‧‧‧第二金屬柱
226‧‧‧第三金屬柱
23‧‧‧半導體晶片
24‧‧‧封裝膠體

Claims (15)

  1. 一種半導體封裝件之製法，係包括：提供第一封裝基板及第二封裝基板，該第一封裝基板具有相對之第一表面與第二表面，該第一表面具有複數第一電性接觸墊及形成於其上的第一金屬柱，該第二封裝基板具有相對之第三表面與第四表面，該第三表面具有複數第二電性接觸墊、形成於該第二電性接觸墊上之第二金屬柱及設於該第三表面上的半導體晶片；接置該第一封裝基板於該第二封裝基板的第二金屬柱上，使該第一封裝基板之第一金屬柱對應電性連接該第二金屬柱；以及於該第一封裝基板與第二封裝基板之間形成包覆該第一金屬柱與第二金屬柱的封裝膠體。
  2. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第一金屬柱上復形成有銲料凸塊，以電性連接該第二金屬柱。
  3. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第二金屬柱上復形成有銲料凸塊，以電性連接該第一金屬柱。
  4. 如申請專利範圍第1項所述之半導體封裝件之製法，於形成該封裝膠體後，復包括於該第二封裝基板之第四表面上形成複數導電元件。
  5. 如申請專利範圍第1項所述之半導體封裝件之製法， 於形成該封裝膠體後，復包括進行切單步驟。
  6. 如申請專利範圍第1項所述之半導體封裝件之製法，於形成該封裝膠體後，復包括於該第一封裝基板之第二表面上接置電子元件。
  7. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，該電子元件係為晶片或封裝件。
  8. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第一金屬柱與第二金屬柱之粗細不同。
  9. 如申請專利範圍第8項所述之半導體封裝件之製法，其中，該第二金屬柱較該第一金屬柱粗。
  10. 一種半導體封裝件，係包括：第二封裝基板，係具有相對之第三表面與第四表面，該第三表面具有複數第二電性接觸墊及形成於該第二電性接觸墊上之第二金屬柱；半導體晶片，係接置於該第二封裝基板之第三表面上；銲料凸塊，係形成於該第二金屬柱上；第一封裝基板，係具有相對之第一表面與第二表面，該第一表面具有複數第一電性接觸墊及形成於該第一電性接觸墊上的第一金屬柱，且該第一封裝基板係以該第一金屬柱對應電性連接該銲料凸塊之方式接置於該第二封裝基板上；以及封裝膠體，係形成於該第一封裝基板與第二封裝基板之間，以包覆該第一金屬柱與第二金屬柱。
  11. 如申請專利範圍第10項所述之半導體封裝件，復包括複數導電元件，係形成於該第二封裝基板之第四表面上。
  12. 如申請專利範圍第10項所述之半導體封裝件，復包括電子元件，係接置於該第一封裝基板之第二表面上。
  13. 如申請專利範圍第12項所述之半導體封裝件，其中，該電子元件係為晶片或封裝件。
  14. 如申請專利範圍第10項所述之半導體封裝件，其中，該第一金屬柱與第二金屬柱之粗細不同。
  15. 如申請專利範圍第14項所述之半導體封裝件，其中，該第二金屬柱較該第一金屬柱粗。
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