TW201320097A - Method and system for reducing write-buffer capacities within memristor-based data-storage devices - Google Patents

Abstract

One example disclosed in the application is an electronic data-storage device comprising one or more arrays of memory elements. The data-storage device also includes an error-control-coding encoder that encodes received data and a READ/WRITE controller that writes encoded data received from the error-control-coding encoder to a number of memory elements by applying the switching-inducing force or gradient to the one or more arrays of memory elements until more than a maximum-allowed number of WRITE requests have been queued to the WRITE-request buffer, until feedback signals indicate that the WRITE operation has completed, or until the switching-inducing force or gradient has been applied for a maximum application time.

Description

Method and system for reducing write buffer capacity in a memristor-based data storage device Field of invention

The present invention relates to a device for storing data in a non-linear bit storage medium, such as a memristive bit storage medium, and more specifically, a method and system for reducing write buffer capacity by encoding data prior to storage. .

Background of the invention

Over the past half century, the size of electronic circuit components has rapidly shrunk. Well-known circuit components, including resistors, capacitors, inductors, diodes, and transistors, were once giant-scale devices that were hand-welded into giant-view circuits, but today they are fabricated in sub-micron dimensions inside integrated circuits. . Microlithography-based semiconductor fabrication technology can produce integrated circuits with tens of millions of circuit components per square centimeter. The sturdy reduction in circuit component size and the increase in the density of integrated circuit components have led to an increase in the operational clock speed of integrated circuits, and the functionality, computational bandwidth, and integration of integrated circuits and integrated circuit-based electronic devices. Data storage capacity and operational efficiency have increased dramatically.

Unfortunately, the physical limits of further increasing the density of internal components of integrated circuits using the lithography method are approaching. Finally, the lithography method is limited by the wavelength of the ray that is fixed and etched by the lithography mask, and as the circuit line and component size is further reduced to the nanometer size, the leakage current through the tunneling and the cause The current loss caused by the relatively high resistance of nano-scale components is further improved by the traditional manufacturing and design methods of integrated circuits. The challenge of reducing component size and increasing component density in one step. These challenges foster novel approaches to the design and manufacture of nanoscale circuits and circuit components. Current research and development efforts are spent on self-assembly through nanoscale components, nanoscale imprinting, and other fairly new methods to produce extremely tight nanoscale electronic circuits. In addition, other types of circuit components, including memristive switching materials, that operate in nanoscale dimensions have been found to be useful as bistable nanoscale memory components. Unfortunately, memristive switching materials and other candidate bistable memory device materials have non-linear response characteristics to the applied voltage, temperature, and other forces and gradients applied to change the material state, often with a fairly broad dispersion of asymmetry. Sexual probability density function (PDF), which characterizes the probability of a memory element switching relative to the different durations at which a switching force or gradient is applied. The symmetry PDF can have quite long tail features, corresponding to the fact that the force or gradient may have to apply a comparative average switching time for significantly longer to ensure switching. In addition, PDF determines the switching performance characteristics of a large number of memory elements, which correspond to a small component of the plurality of memory elements, which compares a majority of the plurality of memory elements with significantly longer forces or Gradient application time switching. This fact in turn leads to a significantly reduced operating bandwidth and/or confidence relative to a theoretical device with a narrowly distributed symmetry PDF, for which the PDF is guaranteed to correspond to the maximum allowable bit error rate. The probability that the force or gradient needs to be applied is not significantly greater than the average application time for switching. Theorists, designers, and developers based on non-linear data storage materials, memory devices such as memristive materials, and other data storage devices continue to seek broadly distributed decentralized switching that can improve some of these devices. Time characteristic Method and device architecture.

In accordance with an embodiment of the present invention, a data storage device is specifically provided comprising: one or more arrays of memory elements each comprising a material in at least two different states by applying a switching inductive force or gradient to the material Inter-switching, and a feedback signal; a write request buffer buffering a received write request; an error control code encoder encoding data associated with the write request; and a read/write controller that will The data encoded by the error control code encoder coupled to the write request of the write request buffer is written to a plurality of memory elements, and the read/write controller applies the switching induced force or gradient to The one or more memory element arrays up to more than one maximum allowable number of write requests have been queued to the write request buffer, the feedback signal indicating that the write operation has been completed, or the switching induction force or gradient has been applied through one The maximum application time.

Simple illustration

1A-B illustrate an example of a nanoscale single bit data storage device having two stable electronic states.

Figure 2 shows the current versus voltage performance of the bistable nanoelectronic device illustrated in Figures 1A-B.

Figure 3A illustrates a log-normal probability density function (PDF).

Figure 3B shows the corresponding progressive distribution function (CDF) for the log-normal distribution PDF shown in Figure 3A.

Figure 4 illustrates the first of two approaches to improve switching between memristive memory components and other non-linear data storage devices. The logarithm of time - the normal distribution effect.

Figure 5 illustrates a second approach to improving the effect of log-normal distribution switching time for memristive memory elements and other bistable data storage materials.

Figures 6A-B illustrate the application of switching pulses to a memristive memory element or other non-linear data storage material.

The 7A-F diagram illustrates six data writing methods for writing data to a memory device including a memory element characterized by a log-normal distribution switching time.

Fig. 8 exemplifies the dependence of the total expected time T _avg of the applied write voltage on the first pulse length T ₁ in the two-pulse writing method.

Figure 9 illustrates the dependence of the expected progressive time T _avg of the applied write voltage on the maximum application time T _max for the continuous write method.

Figure 10 presents a table showing a comparison of various writing methods for writing data into memory, the memory including memory elements characterized by log-normal distribution switching times.

Figure 11 is a diagram illustrating the information from the first horizontal section of the table provided in Figure 10.

Figure 12 provides a table listing the different number of pulses and the number of average pulses for the multiple pulse write method for each of the different components of the desired write failure probability that are expected for the write time.

Figure 13 shows a line graph of expected waiting time versus write intermediate arrival time for the uncoded 2-pulse write method and the encoded 2-pulse write method.

Figure 14 illustrates a data storage device incorporating both a feedback signal and an ECC code.

Figure 15 shows a control flow chart of the operation of the write buffer component (1434 in Fig. 14).

Figure 16 provides a control flow chart for the conventional "input" (1506 of Fig. 15).

Figure 17 provides a control flow chart for the conventional "output" (1508 of Figure 15).

Figure 18 provides a control flow diagram illustrating the operation of the read/write controller (1430 of Figure 14).

Figure 19 provides a control flow chart for the conventional "write" (1806 of Figure 18).

Detailed description of the preferred embodiment

The present invention relates to an electronic data storage device for storing data in a memory component characterized by a relatively broad and/or asymmetric switching time probability density function. These types of memory components, many of which incorporate nonlinear bistable materials, including memristive materials, may have the worst case switching times that are significantly greater than the average switching time. The probability distribution reflects the switching time observed when the memory component is repeatedly switched from the first bistable to the second bistable. The probability distribution reflects the switching time of the plurality of memory elements observed when switching voltages, currents, or other forces or gradients are applied to a plurality of individual memory elements. For conventional data storage devices, potentially lengthy switching times result in relatively long switching cycles and correspondingly low data storage device input bandwidth.

The electronic data storage device related to this case is discussed in the following six sections: (1) A comprehensive review of memory components with asymmetrically distributed switching times; (2) Error control code; (3) hypothesis writing method; (4) analysis of various writing methods; (5) analysis results of various writing methods; and (6) examples of electronic data storage devices related to the present case.

A comprehensive review of memory components with asymmetrically distributed switching times

1A-B illustrate an example of a nanoscale single bit data storage device having two stable electronic states. Figure 1A shows that the device is in a relatively high resistance state, and Figure 1B shows that the device is in a relatively low resistance state. The resistivity of the dielectric material between the electrodes can be electronically sensed, such that the two different resistance states shown in Figures 1A-B can be used to store information for a single bit.

Figures 1A-B are all using the same illustrative conventions. In Fig. 1A, the dielectric material 102 is interposed between the two conductive electrodes 104 and 106. The electrode portions above and below the bistable dielectric material 102 are shown in Figure 1A. In general, the electrodes can be nanowires or other conductive elements that electrically interconnect the nanoscale electronic device with other nanoscale electronic devices, nanoscale circuits, and ultimately, micron and giant Stage circuit. In FIG. 1, dielectric material 102 is shown as having two distinct portions: (1) a low resistivity portion 108 and a high resistivity portion 110. The low resistivity portion is a depletion region, for example, including oxygen vacancies for assisting current conduction as an example. The high resistivity portion 110 of the dielectric material lacks vacancies and thus has an undoped semiconductor or dielectric conductance. In FIGS. 1A-B, when a sufficiently large voltage is applied across the dielectric material in an upward vertical or z-direction, oxygen vacancies may be redistributed within the dielectric material between the two electrodes, As shown in Figure 1B. The redistribution of oxygen vacancies results in a relatively low electrical resistance throughout the dielectric material. Apply a large enough voltage to the opposite direction or apply a negative voltage in Figure 1B In the upward vertical direction, the oxygen vacancies themselves are forced to be distributed closer to the lower electrode, as shown in Figure 1A.

Figure 2 shows the current versus voltage performance of the bistable nanoelectronic device illustrated in Figures 1A-B. The relatively large slope portion 202 of the IV curve is the lower resistance portion of the IV curve corresponding to the IV curve, as shown in FIG. 1B. The slope of this curve is proportional to the conductivity of the dielectric material between the two electrodes and inversely proportional to the resistivity. The portion 204 of the IV curve having a relatively small amplitude is the portion of the IV curve corresponding to the high resistance portion of the nanoscale electronic device, as shown in FIG. 1A. Starting from the origin 206 of the voltage axis 208 and the current axis 210, and assuming that the nano-electronic device is in a high resistance state as shown in FIG. 1A, an increased positive voltage is applied from the lower electrode to the upper electrode, resulting in crossing the dielectric. The current of the material is rarely increased, as indicated by the right part of the IV curve 204 until the applied positive voltage is close to the voltage V _W ⁺ 212, at which point the oxygen vacancies rapidly re-distribute throughout the dielectric material or semiconducting material, resulting in a fast current The increase, as indicated by the near vertical portion of the IV curve 204, until point 216 reaches the portion of the IV curve representing the low resistance state. A further increase in the positive voltage results in a relatively large corresponding increase in current along the far right portion 220 of the low resistance IV curve until the voltage V _D ⁺ 222 is reached, at which point the device fails due to high current flow. The resistance heating of the device produces excess heat. Once at point 216, the low resistance state is reached, and as the applied voltage across the electrode decreases, the low resistance IV curve 202 follows the leftward, descending back to the origin 206; and as the voltage is further reduced to a negative increase in amplitude The voltage, current is switched in the direction and increases in amplitude to point 224, at which point the oxygen vacancies are redistributed back to the close layer close to the lower electrode, as shown in Figure 1A, resulting in a rapid current amplitude flowing through the device. Decrease, and return to the high resistance state of point 226. A further increase in the magnitude of the negative voltage applied across the device ultimately results in a voltage V _D ^- 230 at which point the device fails again due to resistive heating.

The transition of the voltage of the nanoscale electronic device from a low resistance state to a high resistance state is called V _W ^- 232. Select high resistance state to indicate Boolean value "0", and low resistance state to indicate Boolean value "1", apply positive voltage V _W ⁺ can be regarded as write-1 operation, and apply negative voltage V _W ^- can be regarded as write-0 operation . The application of the intermediate amplitude voltage V _R 236 can be used to query the value currently stored in the nanoscale electronic device. When the voltage V _R is applied to the device, and as a result of a relatively large current flowing through the device, the device is in a low resistance state, that is, a Boolean 1 state; but when very little current flows through the device, the device is in Bulin 0 state. Thus, the nanoscale electronic devices illustrated in FIGS. 1A-B and 2 may be used as arrays of nanoscale memory devices, and two-dimensional or three-dimensional arrays of such devices may be employed as two-dimensional and three-dimensional memory arrays.

While this and subsequent examples show bistable materials having any of two different stable electronic states, depending on the voltage history applied across the device, three or more steady state devices can be used for each application. For example, a device with three steady states can store one of three different values "0", "1" or "2" in the base-3 number system, or three stables using a tri-state device The two of the states store a single value with an unassigned state that provides further separation from the information storage state. In many cases, a voltage is applied to change the state of the bistable memory element. However, other types of bistable materials can be switched by applying other forces and/or gradients, including temperatures for devices based on phase change materials. Other types of devices may have other than resistive states State type.

As discussed above, Figure 2 provides an idealized description of a type of memristor switching. However, memristive memory components, and other types of memory components that have non-linear characteristics under applied voltage or other forces or gradients, cannot switch from one bistable to another bistable, as opposed to time, as Many other physical phenomena have a switching time of probability distribution. For example, some memristive memory elements have a switching time that can be modeled by a log-normal probability distribution. Figure 3A illustrates a log-normal probability density function (PDF). In Fig. 3A, the vertical axis 302 represents the probability density of a specific memristive memory element switching at time t with respect to the start time of the applied force or gradient, or in other words, the time t is equal to the applied force or gradient for switching the recall. The switching time t _{SW of the} device during the application of the memory element from the first state to the second state. In the 3A diagram, the horizontal axis 304 represents the time t , and the origin corresponds to the time t=0 at which the application of the force or gradient is started.

For the hypothesis log-normal distribution shown in Figure 3A, the average switching time t is 1.0, where time units such as nanoseconds, microseconds, or milliseconds are dependent on a particular memristive element and are not relevant to this discussion. In the normal probability distribution, or Gaussian distribution, the probability distribution function peaks coincide with the average of the random variables. However, as shown in Fig. 3A, the peak 306 of the probability density function of the log-normal distribution is shifted to the left of the mean value of the independent variable t . PDF is asymmetry, not like a normal or Gaussian PDF, and has the feature of extending the right tail 308, corresponding to the fact that there is a significant chance to apply a voltage or other force or gradient to the actual switching of a particular memristive memory element. Time can occur at times significantly greater than the average or mean switching time.

For multi-type electronic devices, including memory, commercial applications require extremely low error rates. As a result, in order to ensure that a sufficient portion of the written memory element does switch when a particular write voltage is applied to the memory, the write voltage may need to be applied to the memory over the period of time that is equal to the average switching time of the memory element, or in other words For a time, for a normalized PDF, the area under the PDF between 0 and the application time approaches 1.0, and the area under the PDF to the right of the application time approaches 0. Figure 3B shows the corresponding progressive distribution function (CDF) for the log-normal distribution PDF shown in Figure 3A. The vertical axis 314 represents a memory-based switching time t _sw probability equal to or less than the time t, and the horizontal axis represents time t. The CDF has a relatively extended hatching approach 310 to the horizontal dashed line, indicating a probability of 1.0 corresponding to the right end of the PDF extension.

The appropriate representation of the PDF of the modeled memristive memory component is provided as follows: Secondly, a suitable expression of the CDF of the modeled memristive memory component is proposed: In the above expression, the function erfc represents a complementary error function. PDF and CDF can be regarded as the distribution expression of t / τ , where the median value is 0 and ln( t / τ ) is a Gaussian distribution. The ratio t / τ represents the switching time normalized by the median switching time τ . The parameter τ is modeled in some types of memristive memory elements by the following expression:

τ _ON is the τ parameter of the positive applied voltage, which switches the memristive memory element to the ON state or the "1" state, and τ _OFF is the τ parameter of the negative applied voltage, which sets the memristive memory element from "1" or ON. The state is switched to "0" or OFF state. The constants a _ON , a _OFF , b _ON , and b _OFF are experimentally determined positive real constants, and v is the applied switching voltage.

In several instances, two approaches are used to design and manufacture cost-effective memory and other data storage devices, using memory components characterized by a log-normal distribution and/or a broad distribution switching time PDF with desired data entry. bandwidth. These two methods can be used separately or in combination. Figure 4 illustrates the first of two approaches to improve the log-normal distribution effect of switching time possessed by memristive memory components and other non-linear data storage devices. Figure 4 shows a single bit memory element 402 sandwiched between two conductors 404 and 406 through which a read voltage and a write voltage are applied to the memory element. In addition, the memory component is coupled to a circuit component 408, which is modeled as a circuit component in FIG. 4, and outputs a feedback signal 410 depending on the voltage difference between the two input signals 412 and 414. For example, in the present model, when the write voltage is applied via conductors 404 and 406 and memory element 402 is in the first of two bistable resistance states, the feedback signal can have a voltage value; when the write voltage is The feedback signal can have a different voltage value when applied via conductors 404 and 406 and memory element 402 is tied to the second of the two bistable resistance states. Such a feedback signal 410 informs the write controller or other memory circuit of the current state of the memory device. So like an instance, permission to write The length of time required for the voltage to be applied to the memory element through the switching of the memory element from the first state to the second state. Thus, as an example, instead of applying a write voltage for a long enough time to ensure that the memory component has switched to a certain degree, sufficient time is available for the PDF operation to determine the characteristics of the memory component, and the write voltage is applied for a long time. To actually switch the memory component. As discussed above with reference to FIG. 3A, the write voltage application time required to ensure switching to a high degree of certainty can be several times longer than the average switching time of a particular memristive memory element, such that the feedback signal typically results in a significantly shortened average voltage. Apply time.

Figure 5 illustrates a second approach to improving the effect of log-normal distribution switching time for memristive memory elements and other bistable data storage materials. In Figure 5, the input binary data 502 is represented by an array of long bit values, and each cell in the array stores a single bit value that is decomposed into a plurality of sub-arrays 504-507 of length k . These k- arrays are then encoded using one of a myriad of different types of error control codes (ECCs), resulting in the addition of r redundant bits to each array 510 of length k . The encoded sub-array is then stored in memory 512. When the stored data is retrieved from the memory during the read operation 514, the encoded stored information is decoded by the decode logic 516 to produce a k- length sub-array 520-523. In general, as discussed in the following section, adding r redundant bits to each sub-array of length k permits a certain number of incorrectly stored bits or incorrectly read bits within each k-length sub-array to be decoded logic. Correction. Thus, during the write/read process, the memory has a certain number of bit errors without causing erroneous data. As an example, with ECC, the length of time during which a write voltage is applied can be significantly shortened while at the same time achieving the same error rate as would be achieved by applying a write voltage for a longer period of time but writing and reading unencoded information.

Error control code

The excellent reference for error control codes is the textbook "Error Control Codes: Fundamentals and Applications", Lin and Costello, Plantis Hall, New Jersey, 1983 and "Introduction to Code Theory", Ron M. Roth, Cambridge University Society 2006. Next, a brief description of the error detection and error correction techniques used by the error control code will be presented. Additional details are available from the aforementioned textbooks, as well as many other textbooks, reports, and journal articles from the field.

The error control code technique systematically introduces the supplementary bit or symbol to be a plaintext message. Comparing the insulation requires using a larger number of bits or symbols to encode the plaintext message to provide information in the form of a coded message for permission to appear during storage or transmission. Errors are detected and corrected in some cases. When the codeword group is treated as a vector in a vector space, and the codeword group spacing is a measure of vector deduction derived from the codeword group, an effect of the bit or symbol that is added or exceeded is required for insulation. Increase the effective codeword spacing.

In the description of error detection and correction, it is useful to describe the data to be transmitted, stored, and retrieved as one or more messages, where a message μ contains an ordered sequence of symbols μ _i , which is a definition The element of the domain F. A message μ can be expressed as: μ = ( μ ₀ , μ ₁ , ... μ _{k -1} ) where μ _i F. The definition field F is a set enclosed by multiplication and addition, including multiplication reciprocal and addition reciprocal. The operational error detection and correction, it is common finite domain GF (p ^m), comprising an integer subset size based equal to m th power of a prime number p of addition and multiplication element is defined as the factorial of m GF (p ) Add and multiply an irreducible polynomial. The binary domain GF (2) or the binary extension domain GF (2 ^m ) is often used, and the discussion below assumes the domain GF (2). Commonly, the original message is encoded into a message c , which also contains an ordered sequence of elements of the domain GF (2), expressed as follows: c = ( c ₀ , c ₁ , ... c _{n -1} ) Where c _i GF (2).

Block coding techniques use block coding data. In this discussion, a block can be regarded as a symbol k μ message contains a fixed number, k the symbol train is encoded as an ordered sequence of n symbols one message c. The encoded message c usually contains a larger number of symbols than the original message μ , so the n is greater than k . r additional symbols in the encoded message, where r is equal to n - k , used to carry redundant check information, permitting errors generated during transmission, storage, and retrieval with extremely high probability of detection It is detected and corrected in many cases.

To a linear block code, ^k 2 k-dimensional codeword subspace group forming one of the vector space of all n-tuples of the (2) in the domain GF. The Hamming weight of a codeword group is the number of non-zero elements in the codeword group, and the Hamming distance between the two codeword groups is the number of elements different from the two codeword groups. For example, consider the following two codeword groups a and b , assuming that the elements are from the binary domain: a = (10011)

b = (10001). The codeword group a has a Hamming weight value of 3, the codeword group b has a Hamming weight value of 2, and the Hamming distance between the codeword groups a and b is 1, because the codeword group a and b has four different elements. Linear block codes are often labeled with a three-element tuple [n, k, d] , where n is the length of the codeword group, k is the length of the message, or equivalently, the base of the number of codeword groups is a logarithm of 2, and d The minimum Hamming distance between different codeword groups is equal to the minimum Hamming weight non-zero codeword group in the code.

The encoding of the data used for transmission, storage, and retrieval, and subsequent decoding of the encoded data, when no error occurs during the transmission, storage, and retrieval of the data, may be symbolized as follows: μ → c ( s → c ( r ) → μ where c(s) is the encoded message before transmission, and c(r) is the message originally retrieved or received. Thus, the initial message μ is encoded to produce the encoded message c(s) , which is then transmitted, stored, or transmitted and stored, and then retrieved or received as the initial received message c(r) . When not delayed, the initial received message c(r) is decoded to produce the original message μ . As indicated above, when no error occurs, the originally encoded message c(s) is equal to the initial received message c(r) , and the preliminary received message c ( r ) is decoded directly into the original message μ without error correction.

When an error occurs during transmission, storage, and retrieval of an encoded message, the message encoding and decoding can be expressed as follows: μ ( s ) → c ( s ) → c ( r ) → μ ( r ). In the foregoing, the final message μ(r) may or may not be equal to the preliminary message μ(s) , and the final received message μ(r ) is generated depending on the encoding of the original message μ(s) and decoding or reconstructing the preliminary received message c(r) . ) the fidelity of the error detection and error correction techniques. Error detection is a process that determines the following formula: c ( r ) ≠ c ( s ) and the error is corrected to the process of reconstructing the initial encoded message from the initial received message: c ( r ) → c ( s ).

The encoding process is a processing procedure whereby the message represented by the symbol μ is transformed into the encoded message c . In addition, the message μ can be regarded as an ordered set containing the symbols of the alphabet composed of the free elements F , and the encoded message c can be regarded as a codeword group, and also contains the symbols of the alphabet composed of the free elements F. Ordered collection. The block μ may be any ordered set of k symbols selected from the F element, and the code block c is defined as an ordered sequence of n symbols selected from the F element by encoding: { c : μ → c }.

The linear block coding technique encodes a block of length k by considering the block μ as a vector in the k-dimensional vector space and multiplying the vector μ by a generator matrix, as follows: c = μ . G. Extending the symbols in the above formula by the notation produces one of the following expressions: Where g _i =( g _{i ,0} , g _{i ,1} , g _{i , 2} ... g _{i , n -1} ).

The generation matrix G of the linear block code has the following form: Or in addition: G _{k , n} =[ P _{k , r} | I _{k , k} ]. Thus, the generator matrix G can be placed in the form of a matrix P expanded by the kxk identity matrix I _k,k . Further, the generator matrix G may have the following form: G _{k , n} = [ I _{k , k} | P _{k , r} ]. The code generated by the generator matrix of this form is referred to as a "systematic code". When a generator matrix having the first form as above is applied to a character μ , the resulting codeword group c has the following form: c = ( c ₀ , c ₁ , ..., c _{r -1} , μ ₀ , μ ₁ ,..., μ _{k -1} ) where c _i = μ ₀ p _{0, i} + μ ₁ p _{1, i} , ..., μ _{k -1} p _{k -1, i} ). Using a generator matrix of the second form, the codeword group is generated with a tail parity check bit. Thus, in a systematic linear block code, the codeword group includes r co-located reconciliation codes c _i followed by k symbols containing the original character μ , or k symbols containing the original character μ followed by r A parity check code. When no error occurs, the original character or message μ appears in the corresponding codeword group in plain text or is easily retrieved from the corresponding codeword group. The parity check result is a linear combination of the symbols of the original message, or the character μ .

One form of the second useful matrix is the parity check matrix H _r,n defined as: H _r,n =[ I _r,r |- P ^T ] or, The parity check matrix can be used for systematic error detection and error correction. Error detection and error correction involves calculating a parity S from the initially received or retrieved message c(r) as follows: S = ( s ₀ , s ₁ , ..., s _{r -1} ) = c ( r ) . Where H ^T H ^T in the parity check matrix of H _{r, n} transpose, expressed as: Note that when binary definition fields are used, x = -x, so the negative sign shown above for H ^T is usually not displayed.

The check bit S is used for error detection and error correction. When the parity S is an all-zero vector, no error is detected in the codeword group. An error is indicated when the check digit includes a bit with the value "1". There is a technique for estimating the error vector ê from the check bit and the code block operation, and when the modulo-2 addition is added to the code block, the best estimate of the original message μ is generated. The details used to generate the error vector ê are presented in the aforementioned context. Note that up to a certain maximum number of errors can be detected, and less than the maximum number of errors that can be detected can be corrected.

Hypothesis writing method

Figures 6A-B illustrate the application of switching pulses to a memristive memory element or other non-linear data storage material. For a large discussion later, consider applying a switching pulse or multiple switching pulses. One switching pulse can be a positive voltage v _ON 602 over a time period t 604, or a negative voltage v _OFF 606 over a time period t 608. In either case, the appropriate τ parameter is selected from τ _ON and τ _OFF to calculate the appropriate log-normal switching time PDF and the corresponding CDF phase from which the time of a pulse T can be determined, where T is the average switching time. The multiple is a unit that provides a probability of switching between the memory elements above a specific minimum switching probability corresponding to a maximum expected bit error rate (BER).

The switching failure probability P _b (T) for a given component, or the bit error rate of a multiple memory device device is as follows from the log-normal CDF operation discussed above: Here, F _{τ , σ} (T) is the CDF discussed above. In the following discussion, for the sake of brevity, the asymmetry between the on-switching and the off-switching is ignored, as in the case where the successful application of the write operation does not change the state of the memory element, so the write operation fails without changing the memory. Component status. Ignoring these conditions does not change the comparison between the various methods, as detailed later. In the following discussion, the switching failure of memristive memory components and other non-linear data storage materials is modeled as binary symmetric noisy channels.

In the following discussion, when ECC is adopted, it is assumed that the code C is a [n, k, d] code, so that the bit error occurring in writing and/or reading each code block is as high as ( d -1)/2 Can be corrected. Of course, the ability to recover from bit errors sacrifices the redundant bits r added to the binary information bits of each group length k, resulting in an information rate R defined as follows: Information rate = R = k / n

R <1 for coded information

R =1 is used for unencoded information.

As discussed above, when the unencoded information is stored in and retrieved from the memory, it is assumed that no error occurred during the reading of the stored information, and the error bit component in the information retrieved from the memory is P _b , That is, the failure probability or BER is switched. BER when the encoded information is stored in memory and subsequently retrieved and processed by the error correction decoder for:

Where s = = the maximum number of bits that can be corrected by the code C, ie [n, k, d] code. In this expression, the probability of all error patterns, including the number of errors exceeding the maximum number of errors that can be corrected by ECC, is Add and divide by n, which is the length of the codeword group.

Second, consider the various different data writing methods using one or both of the feedback signal and the ECC discussed above with reference to Figures 4 and 5. First, various conventional notation methods used in these discussions are summarized.

For a single pulse method, the total time T _t applied to write pulses or other forces or gradients used to switch a memory element is equal to T single pulse time. For multiple pulse method, T _t is equal to multiple pulses and: T _t = T ₀ +... + T _i . Average voltage application time T _avg is the desired total application time: T _avg =E( T _t ). In the single pulse method, T _avg =T. Average voltage application time per bit using the ECC method for: Consider the extra time to write additional redundant bits. Finally, for a particular data write method w, the energy consumption or memory bandwidth gain G or expected savings for each information bit is: Where G is expressed in decibels; T _{avg , r} is the expected pulse length for the uncoded one-pulse scheme discussed below; T _{avg , w} is the average pulse time per bit for a particular data writing method.

Therefore, the following comparisons, uncoded BER P _b , coded BER The total time T _t of the applied voltage or other force and/or gradient used to write the data, the average application time T _{avg of the} multiple pulse method, and the average voltage application time per bit And the gain G is evaluated to aid in the comparison of different data writing methods. although It is a good number to be used when comparing the energy consumption between different writing methods and the memory bandwidth, but T _avg and T _max reflect the device wear and the worst case potential considerations.

As discussed earlier, ensure that the data is stored in a logarithm with switching time - often One way to improve the potential for long-term write voltage application is to use a feedback signal that allows the memory controller to decide whether to switch at a selected point in time. Specific memory components. It should be noted that this feedback-based method, which is used to reduce the average application time of the write voltage, is subject to significant cost of additional circuitry and circuit components. Similarly, as discussed above, the ability to correct errors provided by ECC involves storing additional redundant bits and reducing the information rate of the memory device.

In the following discussion, various simplifications were made. For example, the above pairs In the expression provided, it is assumed that when more than s bits of a codeword group are corrupted, the decoder often fails, or in other words, the decoder can often detect an uncorrectable error pattern. When the decoder detects an uncorrectable error pattern, the decoder continues to attempt to decode the codeword group, but no additional errors are imported. In fact, this is not always the case. There are a few possible decoders that will generate incorrectly decoded codeword groups for an uncorrectable error pattern. Assuming that this possibility is ignored, it is actually reasonable because the assumption does not significantly affect the overall BER operation.

For devices having memory elements with log-normal distribution switching time characteristics, there are a number of different parameters that can be optimized. For example, during the application of a write voltage or other force or gradient, in addition to changing the length T and the number of pulses, the voltage itself can be changed. Higher voltages typically reduce the average pulse time required to achieve a particular BER, but also increase memory or other The data storage device consumes energy for storing information. In many cases, however, there is no optimum write voltage over the range of write voltages that can be applied. Instead, using a larger write voltage typically results in lower energy consumption. In other words, the write applied to the memory component The higher the voltage, the shorter the time required to apply the write voltage and the less total energy used to switch a memory component. Of course, at some point, increasing the write voltage causes the device to malfunction, and the lifetime of the device may also be adversely affected by the use of high write voltage. As another example, as discussed above, the natural logarithm of the switching time modeled by the PDF and CDF representations set forth above is dependent on the applied write voltage. However, the coherence is weak and thus does not constitute a good candidate for the optimization parameters.

As described above, in the following discussion, the application time is reported in units of τ , or in other words, randomly changed due to t/τ . In the discussion that follows, the results are provided on a time scale independent basis. In the following calculations for various parameters of various information writing methods, a Bose (Ray-Chaudhuri, Hocquenghem (BCH)) ECC code C is used . This code is [4304, 4096, 33] ECC with R 0.952, up to 16 random errors can be corrected for every 4096 bit code area. In the following discussion, this particular code is used to correct switching failure errors for good performance, but in the actual memory system, the additional considerations of the selection code also include the code failure mode type and the code appropriate handling of each type. The ability to make multiple bit errors. In the following analysis, consider two different target BER levels: (1) P _b = 10 ^-12 , which means that the BER level of the current storage device is low, and it corresponds to storing two hours of high-definition video without Expected error; and (2) P _b =10 ^-23 , indicating the expected BER level in the future.

The 7A-F diagram illustrates six data writing methods for writing data to a memory device including a memory element characterized by a log-normal distribution switching time. These methods form a hypothesis experiment in which six kinds of data are written. The method of entry is determined by first writing the data to the memory and then writing the data back from the memory. As discussed later, based on the log-normal distribution PDF and CDF along with other assumptions and considerations, parameters can be estimated for such hypothesis experiments.

In the first method, as shown in FIG. 7A, referred to as "a pulse uncoded writing method", in step 702, the data is written to the memory using a single pulse of length T; in step 703, from the memory Reading back; and in step 704, the data read back from the memory is compared with the data originally written to the memory to determine the bit error rate (BER) of the one pulse uncoded write method. Of course, the experiment will be repeated multiple times, or multiple memory elements will be tested, or both, to achieve statistically meaningful results. A pulse uncoded write method represents a reference point, which is compared to an additional method using one or more of an error control code (ECC) and a feedback signal as follows. As shown in FIG. 7B, in a pulse encoded method, in step 706, the data is first encoded into a codeword group, and then in step 707, the memory is written using a single write pulse of length T. In step 708, the data is read back from the memory and decoded in step 709. Then, in step 710, the decoded data is compared to the data originally stored in the memory to obtain the BER for a pulse encoded method. In the multi-pulse uncoded method shown in Fig. 7C, the data is written in multiple pulses. In the target loop of steps 712-716, a sequence of pulses is used to attempt to write data to the memory. In each iteration of the back-loop, the data is attempted to use a pulse of the next length T _i , where i is an iterative repeating variable indicating the number or exponent of the current iteration. Then at step 714, the feedback signal provided from the feedback enabled memory component is considered to determine if the material has been correctly written to the memory. In addition, the memory component can be read to confirm that a switch has occurred. When the data has not been correctly written to the memory, and when the current iteration index i is less than the iteration end value num, as determined in step 715, then the next iteration of the loop is performed. Otherwise, in step 717, the data is read back from the memory and compared to the data written to the memory to determine the BER derived from the multi-pulse uncoded method. As previously discussed, the pulse time and T ₀ +...+ T _{i are} equal to the total pulse time T _t and in turn are less than or equal to a particular maximum voltage application time T _max . To model this and related methods, it is assumed that the switching probability is related to the total progressive voltage application time of one or more pulses applied to the memory element during a write operation. In other words, applying a write voltage with three 1 second pulses is equivalent to applying the write voltage over a single 3 second pulse. The multi-pulse encoded method shown in Figure 7D is similar to the multi-pulse unencoded method discussed above with reference to Figure 7C, but in step 720, the data is first encoded using ECC, and then decoded at step 722.

Figure 7E shows a continuous unencoded method. This continuous uncoded method is equivalent to the limit of the multi-pulse uncoded method, where the pulse time T _i is shortened to an infinitesimal period, and summed together to the maximum voltage application time T _max . At step 724, a write voltage is applied to the memory device to begin writing data to the memory elements internal to the device. Then, in the in-loop of steps 725-726, the feedback signal from the memory component is continuously monitored to determine when the memory component to be switched by applying the write voltage actually switches to its desired state. . When it occurs, when the - loop ends, the data is read back from the memory in step 727, and in step 728, the data is compared to the previously written data to determine the BER of the continuous uncoded method. The continuous encoded method shown in Figure 7F is similar to the continuous unencoded method, but in step 730, the data is first encoded using ECC and, after being read from the memory, subsequently decoded in step 732.

All of the methods illustrated in Figures 7A-F represent a hypothesis data storage method in which neither feedback nor ECC, or one or both of feedback and ECC, is employed in a pulse unencoded method. The feedback system is used in a multi-pulse uncoded and multi-pulse coded method as well as a continuous uncoded and continuous coded method. The ECC is based on a pulse-encoded method, a multi-pulse coded method, and a continuous coded method. For a pulse method, T _avg = T _max = T . For a pulse encoded method, = T _avg / R . For a pulse unencoded method, = T _avg .

Analysis of various writing methods

The analysis methods for the various writing methods discussed with reference to Figures 7A-F are discussed in this section. The analysis provides various references as discussed above including T _avg , And the valuation of G. The results of each analysis are discussed in the following subsections.

In a pulse method, the choice of T determines the input BER P _b (T) of the stored data, which is assumed to have been encoded in C in the encoded method. The output BER of the encoded method is then estimated using the parameters n = 4304, s = 16 of the aforementioned BCH code.

The multi-pulse writing method using two pulses is the simplest data writing method with feedback. The initial pulse of time T ₁ and the state of the sensing device are applied. When the device is found to have switched to the target state during the period, the write operation is considered complete. When the device has not switched, an additional pulse of duration T _max - T ₁ is applied, where T _max > T ₁ . Note that although interrupting the operation at time T ₁ will shorten the average total pulse time, the probability of switching failure is still determined by T _max , resulting in P _b = 1 - F _{τ , σ} ( T _max ). The expected total pulse time is T _avg ( T _max , T ₁ )= F _{τ , σ} ( T ₁ ) T ₁ +(1 - F _{τ , σ} ( T ₁ )) T _max . Given a target value of P _b , The T ₁ value of the minimized T _avg can be found. Indeed, it is easy to confirm that T _avg ( T _max ,0)= T _avg ( T _max , T _max )= T _max , and as a function of T ₁ , T _avg has a sharp minimum in the interval (0, T _max ). Fig. 8 exemplifies the dependence of the total expected time T _avg of the applied write voltage on the first pulse length T ₁ in the two-pulse writing method. In order to find the T ₁ value that minimizes T _avg , after substituting the complete expression of F _{τ , σ} as provided above, the right side of the above expression is differentiated and solved for the value of derivative zero, denoted as T ₁ ^opt ( T _max ). The best expected total pulse length is given by T _avg ( T _max , T ₁ ^opt ( T _max )).

For binary symmetric noisy channels, the 2-pulse method is the same as the 1-pulse method, but far shorter pulses are expected and, correspondingly, far lower energy is used to obtain the same BER. The worst case duration is the same as for the 1-pulse case. Also, as in the 1-pulse case, ECC is used, resulting in a further reduction in the expected pulse length and energy consumption, but in addition, the result is that the worst case vs. average pulse length ratio is greatly reduced.

The 3-pulse writing method is analyzed in a manner similar to the 2-pulse writing method, but the sensing of the memory element state is permitted to be performed at discrete times T ₁ and T ₂ , 0 T ₁ T ₂ T _max . The total pulse length is expected to be given by: T _avg ( T _max , T ₁ , T ₂ ) = F _{τ , σ} ( T ₁ ) T ₁ + ( F _{τ , σ} ( T ₂ )- F _{τ , σ} ( T ₁ )) T ₂ +(1 - F _{τ , σ} ( T ₂ )) T _max . For a given value of T _max corresponding to the target value of P _b , T _avg has a global minimum of T ₁ and T ₂ It is easy to find the minimum value by taking the partial derivative of T ₁ and T ₂ and solving the obtained equations by numerical methods.

Continuous feedback write method, when the device state is continuously monitored, the maximum pulse duration T _max, occurs immediately after switching off the applied voltage. The expected pulse length of the continuous feedback writing method is given by the following formula When T _max tends to be infinite, as expected, the above expression tends to be , that is, the log-normal density f _{τ ,} the average of _σ . In fact, when T _max / τ > 1, it is quite fast to approach this limit. Figure 9 illustrates the dependence of the expected progressive time T _avg of the applied write voltage on the maximum application time T _max for the continuous write method.

The feedback provides a significant gain in the expected duration of the write operation. These gains are directly translated into a reduction in expected energy consumption and a reduction in device wear. The use of ECC further strengthens this gain, occasionally reaching a significant margin. Further, since the encoding resulting in very significant shortening of T _max, resulting in a gain corresponding to the flux system, even when the limited write requests occur at least so too interval T _max time units. In order to allow the flux to benefit from the shortening of T _avg and to increase the operating rate beyond the T _max limit, the queue waiting or buffering mechanism of the write operation can be embodied because some operations will take time T _max at a higher rate. The written write request will have to wait for the completion of these operations. The buffering requirements and confidence of such systems can be analyzed using the queue waiting theory tool.

Consider the 2-pulse method with parameters T ₁ , T _max , and T _avg . For the sake of simplicity, it is assumed that the write request arrives at a fixed rate, and the intermediate time of the arrival time is A time units. If A T _max does not need to wait for a queue, so it is estimated to be A < T _max . Obviously, the queue A > T ₁ for any remaining restriction opportunities (actually, the theoretical results are awaited by well-known queues and will also be revealed from the analysis below, A > T _avg ). Yet another simplifying assumption is that the ratio d = ( T _max - A ) / ( A - T ₁ ) is an integer. Since the ratio T _max / T _{avg is} quite large, this is not a very restrictive assumption given that a target BER is achieved with a certain value of T _max . In most cases, T _max can be slightly increased to make d an integer. Using these assumptions, the analysis of the waiting time in the queue is reduced to the study of simple integer value random walks.

Let w _i denote an integer random variation representing the waiting time in the i-th write request queue (the actual waiting time is ( A - T ₁ ) w _i ), and let p = P ( t _i = T ₁ ), where T _i in the actual total pulse length of the i-th writing, i.e. the i-th write service time requirements. Let a(b) ⁺ denote ab, or otherwise denote 0.

Here, D _i is a random variable, assuming values of {1, -d}, P ( D _i =1) = p , and P ( D _i =- d ) = 1 - p . Based on previous assumptions, these odds are independent of i independence. The random walk w _{i is} a Markov chain, which is continuous for a sufficiently large p , and often returns the state w _i =0 infinitely. Under this assumption, the chain has a static distribution Obviously, from w _i = w + 1 , through D _i = 1 , the state w _i + 1 = w can be reached. w The range of d -1. therefore Here u = P _d . On the other hand, the statement w =0 can be reached from w = 0 or w =1, again with D _i =1. Thus, P ₀ = pP ₀ + pP ₁ = pP ₀ + p ^d u . Solving for P ₀ Finally, for w d , statement w can arrive from w +1 with D _i =1; or arrive from w - d with D _i =- d to obtain recursion The explicit expression of the generator can be obtained from the above expression. From this expression, it is possible to derive the expected value of the waiting time. Let W = ( A - T ₁ ) w and translate back to the time unit, As expected, when A approaches T _max (when A When T _{max does} not need to be listed, E [ W ] approaches zero; and when A approaches T _avg , E [ W ] approaches infinity. By Leigh (Little) theory [3], the expected value of the queue size Q system is given by E [Q] = E [W ] / A.

From the expression provided above, it is apparent that the factor u is multiplied by the full probability P _w . Consider G ( z )= uG ₀ ( z ) z ⁱ + uz ^d G ₁ ( z ), where and Directly following the explicit expression of G ₀ ( z ) As for G ₁ ( z ), applying the expression G ₁ ( z ) and the recursion provided above, and remembering u = P _d , obtain the following expression Rearrange the items, and after some algebra manipulation, get the following expression Where g _h ( z )=(1- z ^h )/(1- z ), for the integer h 1, delete a common factor (1- z) from a molecule G ₁ (z) and the denominator of the formula is represented. The above expression determines the factor of G ( z ) as high as u . When G (1) = 1 is set, the following expression u = (1 - p ) (( d +1) p - d ) p ^{- ( d +1) is obtained} , and the measurement of G ( z ) is completed. The expected value of W is given by the following formula The first provided expression of E [ w ] is obtained. The second representation of E [ W ] as provided above is then substituted for d =( T _max - A )/( A - T ₁ ) into the first provided expression, multiplied by the time scale A - T ₁ , remembering T _Avg = pT ₁ +(1- p ) T _max . Note that in order for u to be positive, p > d /( d +1) results in A > T _avg .

Consider again the discrete pulse writing method, intermediate intervention reading to confirm the switch, but not to impose a clear limit on the number of pulses, but instead to impose penalties on the corroboration/reading operation and to determine the optimal pulse method to comply with this penalty.

Let T ₁ < T ₂ <... < T _{n -1} < T _max denote a sequence of pulse end times, also coincident reading, except for the final pulse ending at T _max , where there is no subsequent reading. Thus, the first pulse has time T ₁ , the second pulse has time T ₂ - T ₁ , and so on. As mentioned above, it is assumed that T _max has been determined by the error rate T _max = for several expected coarse bits. ( p ), P _b = P . It is also assumed that the read operation takes time t _r . Therefore, the total expected time penalty for pulsing and reading can be expressed as Here, T ₀ =0 and T _sw are random quantities of the aggregated pulse time for switching. consider The minimum average pulse and the confirmation time for all possible pulse end times and the number of pulses.

Department T _t t = the time interval is limited to a small positive integer multiples of T _max / m _max, as time T _t = m _i t, and m _i is optimized for. Therefore, the maximum number of pulses is T _max / t = m _max . Assume Indicates the best T _avg obtained under the constraints of such pulse end time. Obviously, And can be displayed Given an unconstrained set of pulse end times T ₁ ,..., T _{n -1} , let T ={ : i {1,..., n -1}} is the quantization end time set, and <...< An element whose T is less than T _max . This composition implies Compare T _avg ( T _max , n , T ₁ ,..., T _{n -1} ) with , T _avg ( T _max , n , T ₁ ,..., T _{n -1} ) can be interpreted as the expected value of the random variable f ( T _sw ), where f ( x ) is And the same, Interpreted as the expected value of the random variable g ( T _sw ) and g ( x ) is For any , by expecting an interpretation, g ( x )< f ( x )+ t is sufficient to establish . Assume ,then . There will be some i such that T _{i -1} < x T _i , here = T ₀ =0 and = T _n = T _max . in this way And then from T _i > Imply i > j , then i > j - 1 or i j . In addition, it is T _i > The case of -t is that otherwise it will not be in the set of quantization end times T as defined above. Combine these two facts For , determine exactly g ( x ) < f ( x ) + t . Nearly identical self-variables can be applied to . So, the purpose is to operate The standard way of doing this is dynamic programming. For any 0 m m _max and m = m ₀ < m ₁ <...< m _{n -1} < m _max , definition It corresponds to the average remaining write time, assuming that a new pulse starts at mt with a subsequent pulse end time {m, t} and that no switching occurs before time mt . Then define As the best choice for the pulse end time after the pulse time mt , it is assumed that the pulse starts at mt .

Obviously = (0). Dynamic programming involves recursive operations ( m ), based on m' > m ( m '). Note that for m = m _max -1, there is exactly one possible pulse end time, ie the end at m _max t , For m < m _max - 1 , a single pulse can be used to end m _max t , in which case T _avg ( m ,1)=( m _max - m ) t , or n can be used 2 pulses end at intermediate time. In response to this situation, turn This is shown below Combine T _avg ( m ,1)=( m _max - m ) t with T _avg ( m , n , m ₁ ,..., m _{n -1} ) is obtained for the initially provided expression So for m' > m , from ( m ') can be operated ( m ), all the way until m = 0 . An optimized pulse end time can be found for each m- tracking optimization m ₁ , where an external minimum is achieved by the first term, corresponding to ending a pulse at T _max , the optimization m _{1 is} desirable As m _max .

It's easy to understand the complexity of the algorithm is not better than O ( ) Poor operation. A simple manner with respect to the complete search, greatly accelerate the operation speed is minimized m ₁ of the system for connecting a large minimum value calculating respective mobile m _1, the starting m ₁ = m + _1; such that when m ₁ m ₁ t - When mt + t ₁ exceeds the minimum value of the move, the search is discarded. Since m ₁ t - mt + t ₁ is increased in m ₁ and the other component due to cost is often non-negative, the optimization is discarded in this way.

Analysis results of various writing methods

Figure 10 presents a table showing a comparison of various writing methods for writing data into memory, the memory including memory elements characterized by log-normal distribution switching times. The table is horizontally partitioned into horizontal segments 1002 and 1004 that display computational characteristics for various write methods, wherein the read cost of the method of monitoring the feedback signals from the memory elements is not considered; and the horizontal segment 1004 The computational characteristics of the multiple pulse writing method are shown, where the reading cost is estimated and the characteristic calculations included in the respective writing methods are included. The table shown in Fig. 10 is vertically cut into two vertical sections, including a first vertical section 1006, wherein the characteristics are calculated to ensure a switching failure probability P _b = 10 ^-12 ; and a second vertical zone Segment 1008, where the characteristics are calculated to ensure a switch failure probability P _b = 10 ^-23 . In each vertical section of each horizontal section, or in other words, each quadrant in the table, is displayed for various considered writing methods , T _avg , T _max , And gain, clearly displayed for the encoding method . The second horizontal section 1004 for displaying the resultant multi-write method characteristics, and having a specific T _max has read the respective cost factor between pulses is equal to τ.

By analyzing the data shown in the table provided in Figure 10, the gain G of the coded write method is usually larger than the uncoded write method, and the average or expected pulse time T _avg is usually smaller than the uncoded method for the coded method. . In all cases, the T _max voltage application time of the encoded method is significantly less than the T _{max of the} uncoded method. Even when the cost of reading is taken into account in the calculation, the T _max reduction of the encoded method relative to the uncoded method occurs. Again, the gain of the multi-pulse method using feedback is significantly greater than that of a pulse encoding method.

Figure 11 is a diagram illustrating the information from the first horizontal section of the table provided in Figure 10. In Figure 11, the switching failure probability is plotted against the vertical axis 1102 and the expected pulse time for each bit. The plot is plotted against the horizontal axis 1104. Individual curves, such as curve 1106, illustrate the probability of switching failures for eight different write methods. The relationship between the functions. visible Significantly reduced as the number of pulses used increases; and the coded method The value is generally less than the unencoded method.

At P _b =10 ^-23 , the coded 2-pulse method provides an additional 3 dB gain for the uncoded 2-pulse method. More notably, the code reduces the worst case to an average ratio from about 50:1 to 3: 1. In fact, the 2-pulse uncoded method has a gain of only 1.8 dB over the 1-pulse coded method. Comparing the 3-pulse uncoded and coded methods, the code provides an additional gain for the expected total pulse length (1 dB at P _b = 10 ^-23 ), and the worst case ratio is greatly improved. In fact, as shown in Fig. 11, for the P _b range of interest, the 3-pulse uncoded method is very close to the 2-pulse coded method, and the 3-pulse uncoded method obtains 107 from P _b = 10 ^-23. The worst case vs. average ratio of 1 is compared to the 3:1 ratio of the 2-pulse coded method. For the continuous writing method, the fast convergence to the log-normal density average f _{τ ,} the effect of _σ can be seen in Fig. 11, where the curve of the continuous writing method can be seen to decrease substantially with the vertical slope, and the uncoded condition is For the parameter σ ₁ ) used in the example, and For the encoded method. As a result, the average pulse length is virtually independent of the target BER, and in this case, the difference in coding gain between the unencoded method and the encoded method is -10 log ₁₀ R 0.2dB, the unencoded method is superior to the already encoded method. Again, the coded method again provides a significant improvement in the worst case ratio for the worst case: from P _b = 10 ^-23 , from 239:1 for uncoded cases to 6.9:1 for coded cases.

Using continuous feedback, an additional coding gain of about 2.3 decibels (average pulse length of 1.7:1 ratio) over the 3-pulse coded method is provided. In principle, this gap can be narrowed by a random increase in the number of pulses in a discrete pulse setting. In fact, when the number of pulses tends to be infinite, the continuous pulse condition can be considered as the limit of the discrete pulse case.

In summary, the effects and interactions of the two mechanisms have been analyzed to address the challenges imposed by the log-normal switching performance of a memristor device. In multiple settings, using the code to shorten the average switching time and the worst case switching time can significantly improve the overall performance of the system. These improvements translate into energy savings and device wear, as well as a significant increase in write throughput. With the sensible combination of feedback mechanism and error correction code, the logarithmic-normal switching performance of memristor should not be a stumbling block to meet the credibility requirements of modern storage systems.

Figure 12 provides a table listing the expectations for the write time considered. The probability of write failure is a different component of τ, the maximum number of pulses and the number of average pulses for the multiple pulse write method. As can be seen in the table provided in Figure 12, the maximum number of pulses is significantly smaller for the coded method than for the uncoded method.

Figure 13 shows a line graph of expected waiting time versus write intermediate arrival time for the uncoded 2-pulse write method and the encoded 2-pulse write method. As can be seen from Figure 13, the expected wait time for the encoded 2-pulse write method is significantly shorter than the expected wait time for the uncoded 2-pulse write method for all write intermediate arrival times. Encoding an additional burden for the system incorporated into the A law encoded ^* = A / R, while for the uncoded Method A ^* = A, permit fair comparison between the two methods; time T _max and T _avg also have the same scale. The information write flux is proportional to 1/A ^* . The frontal impact of this flux code is evident in the figure, including the no-column system ( A ^* = ) and the array system ( < A ^* < )both. When using a queue, E[Q] is expected to provide a suitable buffer design guide for write requirements.

Examples of electronic data storage devices related to this case

Figure 14 illustrates a data storage device incorporating both a feedback signal and an ECC code. Prior to writing, by using both the feedback signal and by encoding the data, as opposed to when the ECC encoding is not used, as discussed above, the data display as provided in FIG. 10 and the required T as illustrated in FIG. _max, maximum write delay T _max system significantly shortened. The shortening of the maximum write latency and the shortening of the T _avg result in a shorter average and maximum write period for the data storage device and a corresponding higher data input bandwidth. Once the switching for all expected memory elements is complete, the feedback signal permits a write voltage or other force or gradient that needs to be applied to switch a particular memory element within the memory to be terminated or shorted. The ECC encoding permits the maximum duration of the write voltage application, or a significant reduction in the switching of another force or gradient application time of the memory component, but still provides the desired bit error rate for the data storage device. In Figure 3A, shortening T _max shifts T _{max to} the left in the horizontal axis of the PDF, providing more area beyond T _max in the PDF tail, corresponding to the application of the write voltage over a long period of T _max without switching Probability. However, using ECC encoding, a number of switching errors are subsequently corrected after the read operation, effectively reducing the tail area to a level corresponding to the desired bit error rate. As detailed later, the use of ECC encoding and monitoring of the feedback signal may require smaller buffers for input writes, reducing the cost and complexity of the data storage device.

An information storage device representing an instance includes one or more two-dimensional memory element arrays 1402. In Fig. 14, each memory element is represented by a disc such as a disc 1404. The memory elements are arranged in columns and rows, and the memory elements in a column are interconnected by a horizontal electrode, and the memory elements in each row are interconnected by a vertical electrode or signal line. For example, in FIG. 14, memory elements 1406-1413 are interconnected by horizontal signal lines 1414. Memory elements 1413 and 1416-1423 are interconnected by horizontal signal lines 1424. A first demultiplexer or other control element 1426 controls the voltage applied to the horizontal signal line, and a second demultiplexer or other control element 1428 controls the voltage applied to the vertical signal line.

Referring to Figure 5, as discussed above, each memory component also produces a feedback signal that is output to both the horizontal and vertical feedback signal lines. In Figure 14, the feedback signal generated by the memory component is shown as a diagonal segment. A diagonal segment 1429, such as from memory element 1413. During a write operation, the first and second controllers 1426 and 1428 monitor the feedback signals to generate a write completion signal that is looped back to the read/write controller. When the borrowing/writing controller 1430 supplies the data storage unit address to the first and second controllers 1426 and 1428, and the data of the data storage unit is to be written to the data storage device, the first and second controllers 1426 and 1428 Applying an appropriate voltage to a particular signal line places the memory component corresponding to the address data storage unit in a state of the data internal bit value to be written to the data storage device. The data input to the write information storage device 1432 is buffered by the write buffer unit 1434, and buffers the data in the circular buffer 1436. The write buffer component permits the write operation to be received by the information storage device during a short burst interval at a rate that is faster than the rate at which the information storage device is adapted over time. The write burst can end and be stored inside the circular buffer, and then, after receiving the burst write end write operation, the write operation is processed as quickly as possible by the read/write controller, eventually exhausting the loop queue. The read/write controller receives a write operation available signal 1438 from the write buffer component, and the license read/write controller cooperates with the write buffer component to wait for the write operation to cancel the write operation from the loop queue and input to the ECC encoder 1440. The data to be written to the device is first supplied to the ECC encoder 1440. As previously discussed, the ECC encoder 1440 encodes the data into a series of codeword groups and then transmits to the read/write controller 1430. The read/write controller not only controls the first and second controllers 1426 and 1428 to write data to the data storage device, but also controls the first and second controllers 1426 and 1428 to read the stored data from the data storage device. And transmitting the read data to the ECC decoder 1442, which decodes the codeword group read from the data storage device, and outputs the uncoded data 1444. Read/write control The controller 1430 receives the data 1446 and outputs the data 1448, receives the control signal 1450, and outputs the non-data information 1452. The output data and control signals 1454 and 1456 are respectively provided to the first and second controllers 1426 and 1428, and respectively from the first The first and second controllers 1426 and 1428 receive the data and control signals 1458 and 1460.

In another example, the ECC encoder appears in the input sequence upstream of the write buffer, and the encoded data queue waits for an internal write operation instead of waiting for the uncoded data queue as in the previous example. In yet another example, the ECC encoder can be incorporated into a read/write controller, or an additional location within the input sequence that appears in front of the first and second controllers.

In another example, the first and second controllers or the read/write controller use the aforementioned multiple pulse method to iteratively repeatedly write data to the memory component, read back the data, and determine whether the write was successful. In this alternative example, the memory component does not generate a feedback signal. Instead, the first and second controllers 1426 and 1428 apply multiple overwrite pulses to the memory elements, and after each pulse, read the contents of the memory elements to which the pulses are applied to determine if the data was written correctly. Based on multiple pulse writes and intermediate read operations to confirm proper data storage, the first and second controllers generate a write completion signal that is sent back to the read/write controller, as in the first example, where the state or memory is continuously monitored. element.

In the discussion that follows, note that the write operation contains some maximum amount of data that can be written by the first and second controllers to the array of one or more memory elements during an internal write operation. Therefore, the data associated with the write operation is ECC encoded and then sent to the first and second controllers for writing to the one or more An array of memory components. The feedback signal provided by the one or more memory element arrays indicates whether the entire internal write was successful. The first and second controllers can apply write voltages to individual memory elements over different time periods, or can apply different numbers of pulses to individual memory elements during internal write operations. In addition, more sophisticated buffering mechanisms can be used to store write operations associated with larger amounts of data that can be written than a single internal write operation, and to generate multiple internal write operations for received write operations associated with large amounts of data. During an internal write operation, typically the first and second controllers control the storage to multiple memory elements in parallel.

Figure 15 shows a control flow chart of the operation of the write buffer component (1434 in Fig. 14). In step 1502, multiple variables are initiated. The variable "inPtr" is set to point to or contain the address of the first data storage unit inside the circular buffer. The variation "outPtr" is set equal to the variation factor "inPtr". The variable "full" is set to false. This variation corresponds to a signal sent by the write buffer component to the read/write controller to indicate when the circular buffer is close to full load. The variable "avail" is set to false. This variation corresponds to a signal sent by the write buffer component to the read/write controller to indicate when a write operation is available for delivery to the read/write controller. The variable "newWrite" is set to false, and the variable "writeDQ" is also set to false. The variable "newWrite" corresponds to a signal transmitted from an external device indicating a desired write operation; and the variable "writeDQ" corresponds to a signal sent from the read/write controller to the write buffer component to indicate the read/ The write controller has read the next read from the circular buffer.

Next, in the continuous loop of steps 1504-1508, in step 1505, The write buffer component determines if the external device has requested any new write operations, and in step 1506, handles the write operations by calling the normal "input". In step 1507, the write buffer component also continuously monitors the "wirteDQ" signal; and in step 1508, when the read/write controller has processed the next write operation, the call routine "output" is used to adjust the loop queue.

Figure 16 provides a control flow chart for the conventional "input" (1506 of Fig. 15). In step 1602, the routine "input" determines whether the loop queue is full. The loop queue is full when the variable "outPtr" is equal to the value stored in the variable "inPtr" incremented by 1, or when outPtr points to the last data storage unit in the buffer and inPtr points to the buffer. When the first data storage unit. This should not happen. However, if this happens, the information storage device should simply discard the received write operation because the received write operation cannot be processed because a large number of previously received write operations are currently stored in the circular buffer. Next, in step 1604, the normal "input" stores the write operation into the slot of the loop queue pointed to by the variable "inPtr", and then adjusts the variable "inPtr" to point to a subsequent buffer slot. Module arithmetic is used to circulate a linear buffer. Next, in step 1605, the normal "input" will change the "avail" to true, generating a signal to the read/write controller indicating that the next write operation is available. As determined in step 1606, when there are two or fewer slots remaining in the circular buffer, in step 1608, the normal "input" will change the "full" to true, generating a signal to the read/write controller. , indicating that the circular buffer is freed as quickly as possible to avoid discarding subsequent write operations. Finally, in step 1610, the variable "newWrite" is set to false so that the next write operation received from the external device can be subsequently detected.

Figure 17 provides a control flow chart for the conventional "output" (1508 of Figure 15). In step 1702, the variable "outPtr" is arithmetically adjusted by the module to the circular buffer slot behind the circular buffer slot of the write/write controller that receives a write operation. If it is determined in step 1704, when the free loop buffer slot has increased the number of empty loop buffer slots to three or more, then in step 1706, the variable "full" is set to false to interrupt the communication notification read/write controller. Empty the circular buffer as soon as possible. In step 1708, the variable "writeDQ" is set to false to communicate the read/write controller, and after the next write operation is transferred from the write buffer component to the read/write controller, the loop queue has been adjusted. At step 1710, the write buffer component determines if the circular buffer is currently vacant. If so, then in step 1712, the variable "avail" is set to false to indicate that the read/write controller has no currently available write operations.

Figure 18 provides a control flow diagram illustrating the operation of the read/write controller (1430 of Figure 14). At step 1802, the read/write controller is initialized when power is turned on or reset. Then, in the continuous loop of steps 1804-1808, the read/write controller monitors the signal indicated by the variable "avail" and the read request from the external source. When the write request is obtained from the write buffer component, the call routine " Write "1806" and when the new read request is received, the call routine "reads" 1808.

Figure 19 provides a control flow chart for the conventional "write" (1806 of Figure 18). The conventional "write" includes one of the outer continuous loops of steps 1902-1911, which includes one of the loops in steps 1906-1909. In step 1903, when the "avail" signal indicates that a write request is pending, the normal "write" receives the next write request from the circular buffer and uses ECC to encode the data associated with the write request. Then, in step 1904, the normal "write" setting variable "writeDQ" is true, and the communication notification write buffer component next write request has been received by the read/write controller, enabling the write buffer component to complete the write request release. Waiting for the process. At step 1905, a timer t is initialized, and the read/write controller begins writing data associated with the write request to the memory. When the data is written, the normal "write" monitors the signal corresponding to the "full", the feedback signals from the first and second controllers (1426 and 1428 of Figure 14), and the timer t. To terminate the write operation when the indication ends. When the signal corresponding to the "full" has been declared, as determined in step 1907, the read/write controller immediately terminates the attempted write processing and removes the extra write request from the loop queue to permit the borrowing. The write buffer component queues the write request in the input. The early end of a write operation may result in one or more memory elements failing to switch. As discussed above, then when the data is read back from the memory, the read/write controller relies on the ECC code to correct for data corruption of these types. When the feedback signals from the first and second controllers (1426 and 1428 of FIG. 14) indicate that the write has been successful, as determined at step 1908, the write is ended. Otherwise, when the timer indicates that the writing has been performed is equal to or greater than the T _max of time, as determined at step 1909, the writing is ended. In step 1910, the read/write controller ends the write operation, and when there is still a write request pending, as determined in step 1911, control returns to step 1903. Otherwise, return to "write". In Fig. 19, the data required for writing is written in parallel to the corresponding memory element by the first and second controllers. In some instances, the write request may contain a larger amount of data than can be written by a single parallel write operation. In this case, the additional iterations corresponding to the additional iteration of Figure 16 are repeated, and additional logic is used. Performs two or more write operations required to write all of the material associated with a single write request to the corresponding memory component. In several other examples, memory cells can be written in series rather than in parallel.

In the above routine, it is assumed that the normal write "write" writes the data corresponding to a write operation to the one or more memory device arrays to compare the received write operation with the normal write buffer. It takes a significantly longer time, so when the normal write "write" is set to true, in step 1904, the normal "write buffer" buffers the next write operation, and handles the adjustment of the buffer indicator, and is often Write can complete the current internal write operation and before doing another operation, set the writeDQ to false by calling the routine "output". If this assumption cannot be made, additional tests and steps will be used to properly synchronize the two routines and/or the additional synchronization signals will be used to synchronize the two routines. Of course, in general, the operation of the hardware device that can be embodied by the logic circuit is exemplified as above using the routine, and the operation is synchronized at a lower embodiment level.

Figure 19 provides a schematic illustration of a continuous write method in which the state of the memory elements is continuously monitored. In the alternative example discussed above, where the multiple pulse write method is employed, the internal loop of steps 1906-1909 will iteratively repeat until the write completion signal is received from the read/write controller, whether the write was successful or until the full flag Or the signal is set.

In this way, in addition to monitoring the feedback signals from the first and second controllers, by using the ECC, a smaller circular buffer that compares the circular buffers used when the ECC is not used can be used. In other words, the buffer size can be shrunk to a size that causes a certain percentage of write operations to end early, resulting in a comparison of the number of errors that can be tolerated, resulting in a larger number of switching errors during the write operation. However, when the data is read back from the memory, the error correction capability of the ECC decoder is used to reduce a large number of switching errors.

Although the disclosure herein has been described with respect to specific examples, it is not intended to limit the disclosure herein to such examples. The amendments will be apparent to those skilled in the art. For example, the use of feedback signals and ECC codes can be used in a wide variety of information storage devices, including memory elements with asymmetric switching time PDF, including memristive memory elements, phase change memory elements, and Other types of memory components. The specific ECC code and the specific T _max value used in the information storage device can be respectively set to different codes and calculated values to ensure that the bit error rate of the information storage device satisfies or exceeds the bit error rate requirement. In some types of information storage devices, the maximum write voltage depends on the BER requirements, the age of the information storage device, especially the age of the memory component, the total number of read/write cycles on the information storage device, and other characteristics and parameters. application time T _max and the ECC codes are used to encode information may be reset via a control or dynamically.

It is to be understood that the foregoing description of the disclosed embodiments may be made or utilized by those skilled in the art. Modifications of these examples will be apparent to those skilled in the art, and the general principles defined herein may be applied to other examples without departing from the spirit and scope of the disclosure. The disclosure is not intended to be limited to the examples shown herein, but rather the broad scope of the principles and novel features disclosed herein.

102‧‧‧Dielectric, dielectric materials

104, 106‧‧‧Conductor, conductive electrode

108‧‧‧ Low resistivity part

110‧‧‧High resistivity part

202, 220‧‧‧Low-resistance I-V curve

204‧‧‧Small slope I-V curve

206‧‧‧ origin

208‧‧‧Voltage axis, V

210‧‧‧ Current axis, I

212‧‧‧V voltage V _w ⁺

214‧‧‧ Near vertical part of the I-V curve

216, 224, 226‧ ‧ points

222‧‧‧V Voltage V _D ⁺

230‧‧‧Voltage V _D ^-

232‧‧‧Voltage V _w ^-

236‧‧‧Amplitude voltage V _R

302, 314, 1102‧‧‧ vertical axis

304, 312, 1104‧‧‧ horizontal axis

306‧‧‧ Peak

308‧‧‧Extension of the right tail

310‧‧‧ Shadow line approaching

402‧‧‧One-dimensional memory component

404, 406‧‧‧ conductor

408‧‧‧ memory components

410‧‧‧Return signal

412, 414‧‧‧ input signal

502‧‧‧ Binary data

504-507, 510, 520-523‧‧‧ sub-array of length k

512‧‧‧ memory

514‧‧‧Read operation

516‧‧‧Decoding logic

602‧‧‧ positive voltage

604, 608‧‧ ‧ length of time

606‧‧‧ Negative voltage

702-732, 1502-1508, 1602-1610, 1702-1712, 1802-1808, 1902-1911‧‧ steps

1002, 1004‧‧‧ horizontal section

1006, 1008‧‧‧ vertical section

1106‧‧‧ Curve

1402‧‧‧Two-dimensional memory element array

1404‧‧ discs

1406-1413, 1416-1423‧‧‧ memory components

1414, 1424‧‧‧ horizontal signal lines

1426, 1428‧‧‧ Control elements

1429‧‧‧ diagonal segments

1430‧‧‧Read/Write Controller

1432‧‧‧Information storage device for writing

1434‧‧‧Write buffer assembly

1436‧‧ Circulating buffer

1438‧‧‧Write operation available signal

1440‧‧‧Error Control Code (ECC) Controller

1442‧‧‧ECC decoder

1444‧‧‧Uncoded material

1446, 1448, 1454, 1458‧‧‧ Information

1450, 1456, 1460‧‧‧ control signals

1452‧‧‧ Non-information information

1A-B illustrate an example of a nanoscale single bit data storage device having two stable electronic states.

Figure 2 shows the current versus voltage performance of the bistable nanoelectronic device illustrated in Figures 1A-B.

Figure 3A illustrates a log-normal probability density function (PDF).

Figure 3B shows the corresponding progressive distribution function (CDF) for the log-normal distribution PDF shown in Figure 3A.

Figure 4 illustrates the first of two approaches to improve the log-normal distribution effect of switching time possessed by memristive memory components and other non-linear data storage devices.

Figure 5 illustrates a second approach to improving the effect of log-normal distribution switching time for memristive memory elements and other bistable data storage materials.

Figures 6A-B illustrate the application of switching pulses to a memristive memory element or other non-linear data storage material.

The 7A-F diagram illustrates six data writing methods for writing data to a memory device including a memory element characterized by a log-normal distribution switching time.

Fig. 8 exemplifies the dependence of the total expected time T _avg of the applied write voltage on the first pulse length T ₁ in the two-pulse writing method.

Figure 9 illustrates the dependence of the expected progressive time T _avg of the applied write voltage on the maximum application time T _max for the continuous write method.

Figure 10 presents a table showing a comparison of various writing methods for writing data into memory, the memory including memory elements characterized by log-normal distribution switching times.

Figure 11 illustrates an illustration of the first water from the table provided in Figure 10. Information on the flat section.

Figure 12 provides a table listing the different number of pulses and the number of average pulses for the multiple pulse write method for each of the different components of the desired write failure probability that are expected for the write time.

Figure 13 shows a line graph of expected waiting time versus write intermediate arrival time for the uncoded 2-pulse write method and the encoded 2-pulse write method.

Figure 14 illustrates a data storage device incorporating both a feedback signal and an ECC code.

Figure 15 shows a control flow chart of the operation of the write buffer component (1434 in Fig. 14).

Figure 16 provides a control flow chart for the conventional "input" (1506 of Fig. 15).

Figure 17 provides a control flow chart for the conventional "output" (1508 of Figure 15).

Figure 18 provides a control flow diagram illustrating the operation of the read/write controller (1430 of Figure 14).

Figure 19 provides a control flow chart for the conventional "write" (1806 of Figure 18).

1402‧‧‧Two-dimensional memory element array

1404‧‧ discs

1406-1413, 1416-1423‧‧‧ memory components

1414, 1424‧‧‧ horizontal signal lines

1426, 1428‧‧‧ Control elements

1429‧‧‧ diagonal segments

1430‧‧‧Read/Write Controller

1432‧‧‧Information storage device for writing

1434‧‧‧Write buffer assembly

1436‧‧ Circulating buffer

1438‧‧‧Write operation available signal

1440‧‧‧Error Control Code (ECC) Controller

1442‧‧‧ECC decoder

1444‧‧‧Uncoded material

1446, 1448, 1454, 1458‧‧‧ Information

1450, 1456, 1460‧‧‧ control signals

1452‧‧‧ Non-information information

R‧‧‧Read

W‧‧‧written

Claims (15)

A data storage device comprising: one or more memory element arrays each comprising a material, switching between at least two different states by applying a switching inductive force or gradient to the material, and a feedback signal a write request buffer buffering a received write request; an error control code encoder encoding data associated with the write request; and a read/write controller to be received from the write request buffer The write request requires that the data encoded by the error control code encoder be written to a plurality of memory elements by applying the switching induction force or gradient to the one or more memory element arrays until A write request for a maximum allowable number has been queued to the write request buffer, the feedback signal indicating that the write operation has completed, or the switching sense or gradient has been applied for a maximum application time. The data storage device of claim 1, wherein the memory elements are characterized by a log-normal distribution switching time. The data storage device of claim 1, wherein the maximum application time is shorter than one of a specific bit error rate that will be provided for an uncoded write operation. The data storage device of claim 3, further comprising an error control code decoder for decoding data read by the read/write controller from the one or more memory element arrays. For example, the data storage device of claim 1 of the patent scope, wherein the writing request The size of the buffer is smaller than the one of the following write-required buffer sizes, which will ensure that any write operation corresponding to a received write request does not successfully complete or apply the switching sense or gradient to a maximum End before the application time. The data storage device of claim 5, further comprising an error control code decoder for decoding data read by the read/write controller from the one or more memory element arrays In the decoding process, a sufficient number of error bit values are corrected to provide a particular bit error rate, although the write sensing force or gradient is applied over a maximum application time due to a write operation corresponding to the received write request. This is also the case when a successful completion or pre-application is completed. The data storage device of claim 1, wherein the data storage medium is a memristive material, and when a switching induced voltage is applied across the data storage medium, the memristive material is in a first resistance state and a Switching between the second resistance states. A method of writing data to a data storage device, the device comprising one or more arrays of memory elements each comprising a material that is applied to at least two by applying a switching induction force or gradient to the material Switching between different states, and a feedback signal, the method includes: encoding, by an error control code encoder, data associated with an accepted write request; and listing the write request to a write request buffer; And writing the encoded data to a plurality of memory elements by applying the switching inductive force or gradient to the one or more memory element arrays until more than one maximum allowable number of write requests have been queued to The write A buffer is required, the feedback signal indicating that the write operation has been completed, or the switching induction force or gradient has been applied for a maximum application time. The method of claim 8, further comprising selecting the maximum application time, which is shorter than a minimum calculated to ensure that a particular bit error rate is used to write uncoded material to the one or more arrays. Applying time; but long enough for the decoder to correct data read from the one or more arrays when the data is subsequently read from the one or more arrays and decoded by an error control code decoder Up to a certain number of bit errors, the total bit error rate used to write data to and read back from the data storage device is less than or equal to the specific bit error rate. The method of claim 8, further comprising selecting a size for the write request buffer that is smaller than one of the write write buffer sizes described below, ensuring that a corresponding received write is ensured Any write operation required will not end before the successful completion or application of the switching induction force or gradient over a maximum application time; but large enough that the data is subsequently read from the one or more arrays and borrowed When the error control code decoder is decoded, the decoder corrects up to a certain number of bit errors in the data read from the one or more arrays for writing data to and from the data storage device. The total bit error rate of the material being read back is less than or equal to the specific bit error rate. The method of claim 8, wherein the data storage medium is a memristive material, and when a switching induced voltage is applied across the data storage medium, the memristive material is in a first resistance state and a second Switch between resistance states. The method of claim 8, wherein the memory elements are characterized by a log-normal distribution switching time. The method of claim 8, wherein the switching inductive force or gradient is continuously applied to the one or more memory element arrays when the feedback signals are continuously monitored. The method of claim 8, wherein the switching inductive force or gradient is applied to the one or more memory element arrays during discrete intervals, wherein the feedback signals are used to determine Whether the material has been successfully written. A data storage device comprising: one or more memory element arrays each comprising a data storage medium, the data storage medium being at least two different by applying a switching induction force or gradient to the data storage medium Inter-state switching; a write request buffer; an error control code encoder that encodes the received data; and a read/write controller that writes data encoded by the error control code encoder into a plurality of a memory component that applies the switching inductive force or gradient to the one or more memory element arrays by using a plurality of pulses, and confirms the write operation by a read operation after each pulse until more than A maximum allowable number of write requests has been queued to the write request buffer until the write operation has completed, or until a maximum number of pulses have been applied.