CN105976023B - A kind of episodic memory circuit and its operating method based on memristor - Google Patents

Abstract

The invention discloses a scene memory circuit based on a memristor and its operation method. The circuit includes an encoding circuit and a retrieval circuit; the encoding circuit can encode and store events in the circuit according to the event itself and its related characteristics, The signal erases the stored information, and the generated memory trace signal is used as the input signal of the lower circuit; the retrieval circuit can match the memory trace signal and the retrieval signal to generate corresponding episodic memory behavior; the present invention can Pulse operation, simulating the episodic memory behavior of organisms.

Description

Memristor-based episodic memory circuit and operating method thereof

technical field

The invention belongs to the field of artificial neural networks, and more specifically relates to a memristor-based scene memory circuit and an operation method thereof.

Background technique

Episodic memory is a declarative memory that is different from semantic memory. It is characterized by the ability to match the memory traces stored in the brain with the stimulus signals (retrieval cues) perceived from the outside world, thereby generating episodic signals, and through the episodic signals To control the biological behavior of recall and recognition in organisms. Episodic memory is an advanced cognitive behavior, which constitutes the connection of organisms to events, their occurrence time and place, which is of great significance to the basic life activities of living organisms. The biological basis of episodic memory is joint learning. In its model, episodic memory is generally divided into two processes, namely the encoding process (encoding) and the retrieval process (echpory), in which the encoding process integrates and preserves events and their corresponding features. In the biological brain, the retrieval process matches memory traces with external stimuli to generate episodic signals. Episodic memory embodies the intelligent memory and recognition behavior for individuals, and it is of guiding significance for solving the information explosion in the era of big data, improving the storage capacity of computers and information analysis and retrieval capabilities, and developing and researching intelligent robots to realize multi-level recognition of robots.

At present, the research on episodic memory in artificial neural network is in its infancy. Usually, some conceptual models of episodic memory and corresponding operation methods are provided through simulation methods. It is difficult to realize specific episodic memory circuits to simulate corresponding episodic memory. Function.

Contents of the invention

Aiming at the defects of the prior art, the object of the present invention is to provide a memristor-based episodic memory circuit that can be used to simulate the encoding process and retrieval process of biological episodic memory.

The present invention provides a memristor-based episodic memory circuit, comprising: a sequentially connected encoding circuit and a retrieval circuit; the encoding circuit includes a first memristor M1, a second memristor M2, a third memristor M3, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5; one end of the first memristor M1 is used as the first input end of the encoding circuit, the The other end of the first memristor M1 is grounded through the first resistor R1 and the fifth resistor R5 sequentially connected in series, and the other end of the first memristor M1 is used as the second input end of the encoding circuit One end of the second memristor M2 is used as the third input end of the encoding circuit, the other end of the second memristor M2 is used as the fourth input end of the encoding circuit, and the second memristor M2 is used as the fourth input end of the encoding circuit. The other end of the resistor M2 is also connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the series connection end of the first resistor R1 and the fifth resistor R5; the third One end of the memristor M3 is used as the fifth input end of the encoding circuit, the other end of the third memristor M3 is used as the sixth input end of the encoding circuit, and the other end of the third memristor M3 is Also connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to the series connection end of the first resistor R1 and the fifth resistor R5; one end of the fourth resistor R4 serves as The seventh input end of the encoding circuit, the other end of the fourth resistor R4 is connected to the series connection end of the first resistor R1 and the fifth resistor R5; the first resistor R1 and the fifth resistor The serial connection end of the resistance R5 is used as the output end of the encoding circuit; the retrieval circuit includes a memristor M and a fixed-value resistor R connected in series in turn, and the non-series connection of the fixed-value resistor R and the memristor M terminal as the first input terminal of the retrieval circuit, the serial terminal of the memristor M as the second input terminal of the retrieval circuit, and the serial terminal of the memristor M as the output terminal of the retrieval circuit ; The other end of the fixed value resistor R is grounded.

Furthermore, the first memristor M1, the second memristor M2 and the third memristor M3 are the same, and the resistance value of the first resistor R1 and the resistance value of the second resistor R2 , the resistance value of the third resistor R3 and the resistance value of the fifth resistor R5 are equal to the low resistance value of the first memristor, and the resistance value of the fourth resistor R4 is equal to the resistance value of the fifth resistor R5 Half; the resistance value of the fixed-value resistor is equal to the low resistance value of the first memristor.

Furthermore, the first input end and the second input end of the encoding circuit are respectively used to receive the event stimulus signal and the environmental stimulus signal of the first encoding signal; the third input end and the fourth input end of the encoding circuit are respectively used for For receiving the event stimulus signal and the environment stimulus signal of the second coding signal; the fifth input terminal and the sixth input terminal of the coding circuit are respectively used for receiving the event stimulation signal and the environment stimulation signal of the third coding signal; the coding circuit first The seven input terminals are used to receive the fourth encoding signal; the output end of the encoding circuit is used to output the memory trace signal of episodic memory, and serve as the input signal of the retrieval circuit; wherein the first encoding signal, the second The coded signal and the third coded signal are used as three element signals of event, time and place of episodic memory content respectively, and the fourth coded signal is used as other memory content of episodic memory to accommodate expansion of more memory content.

Furthermore, the first memristor includes a first electrode layer, a functional material layer and a second electrode layer electrically connected in sequence.

Furthermore, the functional material layer is an oxide functional material layer TiO _x , TaO _x , WO _x , CuO _x , AlO _x , NiO _x , HfO _x , ZrO _x , SiO _x , NbO _x , VO _x or GeO _x .

Furthermore, the functional material layer is a chalcogenide functional material layer GeSe, Ag ₂ Se, Ag ₂ S, Cu ₂ S, GeS _x , Ge ₂ Sb ₂ Te ₅ , GeTe or AgInSbTe.

Furthermore, the functional material layer is a perovskite functional material layer of SrTiO ₃ , BaTiO ₃ , BiFeO ₃ , CaMnO ₃ , PrMnO ₃ or La _0.7 Sr _0.3 MnO ₃ .

The present invention also provides an operation method based on the above-mentioned scene memory circuit, the operation method includes an encoding step, an erasing step and a reading step;

The coding step includes: simultaneously inputting the event signal of the first coded information, the event signal of the second coded information, the event signal of the third coded information, the The encoding operation is realized by an environmental signal of the first encoded information, an environmental signal of the second encoded information and an environmental signal of the third encoded information; The erasing signal of the first coded information, the erasing signal of the second coded information and the erasing signal of the third coded information are respectively input into the sixth input terminal to realize the erasing operation; The first input terminal, the third input terminal, the fifth input terminal and the seventh input terminal of the encoding circuit apply read signals to read corresponding encoded information and extended information to form a series of time sequence pulses.

Furthermore, at the same time, the memory trace signal is input to the first input terminal of the retrieval circuit, and the retrieval signal is input to the second input terminal, and the episodic memory signal is output from the output terminal after matching the two signals.

The invention provides an episodic memory circuit and a corresponding operation method to simulate the episodic memory physiological behavior of a living body. The episodic memory circuit can store the memory traces of episodic memory according to the principle of joint learning, and use the external retrieval information to realize the recall of memory traces.

Description of drawings

Fig. 1 is the encoding circuit of the episodic memory circuit based on the memristor provided by the present invention;

Fig. 2 is the retrieval circuit of the episodic memory circuit based on the memristor provided by the present invention;

Fig. 3 is the device prototype of the memristor used in the memristor-based episodic memory circuit provided by the present invention and its resistance-voltage characteristic curve; Wherein Fig. 3 (a) is the device prototype of the memristor; Fig. 3 (b) is the resistance-voltage characteristic curve of the memristor;

Fig. 4 is the encoding-reading method of the episodic memory encoding process provided by the present invention; Wherein Fig. 4 (a) is the first, second, third encoding information encoding and corresponding reading method; Fig. 4 (b) is the first, second Coding information coding and corresponding reading method; Fig. 4 (c) is the first coding information coding and corresponding reading method; Fig. 4 (d) is the corresponding reading method without information coding process;

Fig. 5 is the erasing-reading method of the episodic memory coding process provided by the present invention; Wherein Fig. 5 (a) is the 3rd coding information erasure and corresponding reading method; Fig. 5 (b) is the 2nd, the 3rd coding Information erasure and corresponding reading method; Fig. 5 (c) is the first, second and third encoded information erasure and corresponding reading method;

Fig. 6 is the impact of matching accuracy on episodic memory in the episodic memory retrieval operation method provided by the present invention, wherein Fig. 6 (a) is the episodic memory retrieval operation under no coding element matching under the memory trace unchanged; Fig. 6 (b ) is the episodic memory retrieval operation under the matching of the first coding element with the memory trace unchanged; Fig. 6(c) is the episodic memory retrieval operation under the matching of the first and second coding elements under the unchanged memory trace; Fig. 6 (d) is the episodic memory retrieval operation under the matching of the first, second, and third coding elements under the memory trace unchanged;

Fig. 7 is the impact of retrieval signal strength on episodic memory in the episodic memory retrieval operation method provided by the present invention, wherein Fig. 7 (a) is the episodic memory retrieval operation when retrieval signal strength is-1V; Fig. 7 (b) is retrieval signal Episodic memory retrieval operation at a strength of -1.5V;

Fig. 8 is the impact of engram intensity on episodic memory in the episodic memory retrieval operation method provided by the present invention; Wherein Fig. 8 (a) is the episodic memory retrieval operation when engram signal intensity is 0.7V; Fig. 8 (b) is memory Episodic memory retrieval operation when trace signal strength is 0.4V;

Fig. 9 is the impact of memory trace complexity on episodic memory in the episodic memory retrieval operation method provided by the present invention; wherein Fig. 9 (a) is the episodic memory retrieval operation in which the memory trace contains three encoding elements; Fig. 9 (b) is the memory trace Traces of episodic memory retrieval operations containing six encoding elements;

Fig. 10 is the impact of chaos on episodic memory in the episodic memory retrieval operation method provided by the present invention; wherein Fig. 10 (a) is the episodic memory retrieval operation matching the same retrieval information and a memory trace; Fig. 10 (b) is the same retrieval An episodic memory retrieval operation in which information is matched with another memory trace.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

To achieve the above object, the present invention provides a memristor-based episodic memory circuit. According to the basic model of episodic memory, its circuit is divided into two parts, encoding and retrieval, which respectively realize the function of encoding process and retrieval process in the episodic memory model. The scene memory encoding circuit includes a first memristor M1, a second memristor M2, a third memristor M3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5 ; One end of the first memristor M1 is used as the first input end of the episodic memory encoding circuit, and the other end of the first memristor M1 is connected to one end of the first resistor R1 as the second input end of the episodic memory encoding circuit; One end of the second memristor M2 is used as the third input end of the episodic memory encoding circuit, and the other end of the second memristor M2 is connected to one end of the second resistor R2 as the fourth input end of the episodic memory encoding circuit; One end of the resistor M3 is used as the fifth input end of the episodic memory coding circuit, and the other end of the third memristor M3 is connected to one end of the third resistor R3 as the sixth input end of the episodic memory coding circuit; the fourth resistor R4 One end is used as the seventh input end of the scene memory encoding circuit, the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5; the other end of the first resistor R1 is connected to one end of the fifth resistor; the other end of the second resistor R2 Connected to one end of the fifth resistor; the other end of the third resistor R3 is connected to one end of the fifth resistor; the other end of the second resistor R2 is connected to one end of the fifth resistor; one end of the fifth resistor R5 is used as the scene memory encoding circuit output, and the other end is grounded. The first input end and the second input end of the episodic memory encoding circuit are respectively used to receive the event stimulus signal and the environmental stimulus signal of the first encoded signal; the third input end and the fourth input end of the episodic memory encoding circuit are respectively used to receive the second encoding signal The event stimulus signal and the environment stimulus signal of the signal; the fifth input terminal and the sixth input terminal of the episodic memory coding circuit are respectively used to receive the event stimulus signal and the environment stimulation signal of the third coding signal; the seventh input terminal of the episodic memory coding circuit is used for Receive the fourth encoding signal; the output end of the episodic memory encoding circuit is used to output the memory trace signal (engram) of the episodic memory, as the input signal of the episodic memory retrieval circuit; wherein the first encoding signal, the second encoding signal and the third encoding signal The three element signals (event, time and place) of the content of episodic memory are used respectively, and the fourth coded signal is used as other memory content of episodic memory to accommodate the expansion of more memory content.

The episodic memory retrieval circuit includes a memristor M and a fixed-value resistor R, and the non-serial end of the resistor R and the memristor M is used as the first signal input end, which is connected to the output end of the episodic memory encoding circuit, and is used to input the memory trace signal (engram ); the non-serial end of the memristor M is used as the second signal input end, and the other end of the fixed value resistor is grounded to input the retrieval clue signal (retrieval cue); wherein the series end of the fixed value resistor R and the memristor M is also As a signal output terminal, it is used to output the scene information signal (echporic information).

The encoding operation of episodic memory is divided into encoding operation, erasing operation and reading operation. The three operations are arranged in sequence, and the operations that do not need to be executed are realized as defaults under the current timing conditions. The biological principle of the encoding operation is joint learning, that is, it is necessary to apply the event stimulus signal and the corresponding environmental stimulus signal at the same time to complete the corresponding encoding; the erasure operation needs to input a positive erasure signal at the second, fourth, and sixth input terminals , to restore the original resistance state of the memristor; for the read operation, it is necessary to apply a read signal to the first, third, fifth, and seventh input terminals to read the resistance state of the corresponding memristor, wherein the fourth encoding signal is a The signal used for expansion is only read out here, and it does not need to be encoded and erased, so a fixed-value resistor is used in the circuit to replace the corresponding memristor and resistor. The encoding and erasing of the first coded signal, the second coded signal and the third coded signal can be performed simultaneously in time sequence, but the read operation must be completed in strict accordance with the sequence of the coded signals. In the present invention, according to the corresponding Timing, the reading operations of the first, second, third, and fourth encoded signals are performed in sequence.

According to the episodic memory model, the retrieval operation of episodic memory needs to input the memory signal and the retrieval signal at the same time, make the two signals match each other, generate the corresponding episodic signal, and finally complete the episodic memory. With reference to the characteristics of episodic memory, the present invention provides 5 kinds of retrieval operations to realize the corresponding 5 kinds of memory characteristics of episodic memory. These include the influence of precision, that is, under the condition of constant memory trace, the better the matching of retrieval signal and memory trace, the easier it is to realize episodic memory; the influence of memory trace strength, that is, the stronger the strength of memory trace under the condition of constant retrieval signal, The easier it is to realize episodic memory; the influence of retrieval signal strength, that is, under the condition that the memory trace remains unchanged, the stronger the retrieval signal strength, the easier it is to realize episodic memory; the influence of memory trace complexity, that is, the matching degree between memory trace and retrieval signal remains unchanged Under certain conditions, the more complex the memory trace is, the less likely it is to realize episodic memory; the effect of chaos, that is, under certain special conditions, the same retrieval signal can be matched with different memory traces to achieve different episodic memory.

The memristor includes a first electrode layer, a functional material layer and a second electrode layer electrically connected in sequence.

The resistance value of the fixed value resistor R is approximately equal to the low resistance value of the memristor.

The functional material layer _is an oxide functional material layer _TiOx , _TaOx , WOx, _CuOx , _AlOx , _NiOx , _HfOx , _ZrOx , _SiOx , _NbOx , _VOx or _GeOx .

The functional material layer is a chalcogenide functional material layer GeSe, Ag ₂ Se, Ag ₂ S, Cu ₂ S, GeS _x , Ge ₂ Sb ₂ Te ₅ , GeTe or AgInSbTe.

The functional material layer is a perovskite structure functional material layer SrTiO ₃ , BaTiO ₃ , BiFeO ₃ , CaMnO ₃ , PrMnO ₃ or La _0.7 Sr _0.3 MnO ₃ .

The invention provides an episodic memory circuit and a corresponding operation method to simulate the episodic memory physiological behavior of a living body. The episodic memory circuit can store the memory traces of episodic memory according to the principle of joint learning, and use the external retrieval information to realize the recall of memory traces.

In order to further illustrate the episodic memory circuit and its operation method provided by the embodiments of the present invention, the details are as follows in conjunction with specific examples and accompanying drawings:

The episodic memory circuit of the present invention can simulate the episodic memory behavior of living beings, wherein the circuit includes two parts: an episodic memory encoding circuit and an episodic memory retrieval circuit, which respectively simulate the episodic memory encoding process and the episodic memory retrieval process. The episodic memory coding circuit is composed of seven input terminals and one output terminal, wherein the input terminals respectively input the event signal of the first coded signal of the episodic memory coded signal, the environment signal of the first coded signal, the event signal of the second coded signal, the The environment signal of the second coded signal, the event signal of the third coded signal, the environment signal of the third coded signal and the extended signal; the output end outputs the memory trace of the episodic memory, which is used as the input end of the retrieval circuit. The episodic memory retrieval circuit is composed of two input terminals and one output terminal, wherein the two input terminals respectively input the memory trace signal and the retrieval signal of the episodic memory, and the output terminal outputs the episodic memory memory signal.

The artificial neural network circuit based on the memristor of the present invention can realize the scene memory function similar to that of the brain, and is helpful for the development of multi-level recognition and intelligent storage.

Fig. 1 is an episodic memory coding circuit provided by the present invention. Which includes a first signal input end 101, a second signal input end 102, a third signal input end 103, a fourth signal input end 104, a fifth signal input end 105, a sixth signal input end 106, and a seventh signal input end 107 And signal output terminal 108. The circuit consists of three memristors M1, M2, M3, and five fixed-value resistors R1, R2, R3, R4, R5; three of them can be memristors of the same type; the fixed-value resistors are The selection needs to refer to the high resistance and low resistance of the memristor used. In general, the resistance values of resistors R1, R2, R3, and R5 are approximately equal to the low resistance value of the memristor, and the resistance value of resistor R4 is approximately equal to the resistance value of R5. half of the value.

Fig. 2 is an episodic memory retrieval circuit provided by the present invention. It includes a first signal input terminal 201 , a second signal input terminal 202 and a signal output terminal 203 , where the second signal input terminal and the signal output terminal may share one port. The circuit consists of a memristor M and a fixed value resistor R. Wherein, the selection of the resistance value of the fixed-value resistor needs to refer to the high-resistance and low-resistance values of the memristor used. Generally, the resistance value of the fixed-value resistor is approximately equal to the low resistance value of the memristor.

Fig. 3 is the prototype of the memristor device in the episodic memory circuit provided by the present invention and its voltage-resistance properties. FIG. 3( a ) is a device prototype of the memristor, including a first electrode layer 301 , a second electrode layer 303 and a functional material layer 302 between the first electrode layer 301 and the second electrode layer 303 . The first electrode layer 201 and the functional material layer 302 , and the functional material layer 302 and the second electrode layer 303 form electrical contacts. Wherein, the functional material layer 302 can be an oxide functional material layer, including TiO _x , TaO _x , WO _x , CuO _x , AlO _x , NiO _x , HfO _x , ZrO _x , SiO _x , NbO _x , VO _x or GeO _x etc.; the functional material layer 302 can also be a chalcogenide functional material layer, including GeSe, Ag ₂ Se, Ag ₂ S, Cu ₂ S, GeS _x , Ge ₂ Sb ₂ Te ₅ , GeTe or AgInSbTe, etc.; the functional material layer 302 It can also be a perovskite structure functional material layer, including SrTiO ₃ , BaTiO ₃ , BiFeO ₃ , CaMnO ₃ , PrMnO ₃ or La _0.7 Sr _0.3 MnO ₃ . Wait.

Fig. 3(b) is the relation of resistance value variation of the memristor controlled by a single pulse. The resistance value of the memristor has a gradual change characteristic, and can gradually change as the number of pulse signals increases. A pulse signal is applied to the first electrode 301 of the memristor, and the second electrode 303 of the memristor is grounded. When the pulse signal is positive, the resistance decreases; when the pulse signal is negative, the resistance increases. The larger the amplitude of the pulse signal, the greater the change in resistance; the smaller the amplitude of the pulse signal, the smaller the change in resistance.

In the embodiment of the present invention, the episodic memory circuit based on the memristor can simulate the episodic memory behavior of the biological brain, including the information encoding and storage process of the episodic memory and the memory trace retrieval process of the episodic memory. The episodic memory encoding process is to encode external event signals and their corresponding time and space characteristics into a number of encoded information through joint learning, and store them in the encoding circuit. The encoding circuit provided by the present invention can realize the encoding and storage of three encoding elements and one extension element, wherein the three encoding elements respectively represent the event of the episodic memory signal and its spatial and temporal characteristics, and the extension element is used for more encoding elements in the future coding. The operation of the encoding circuit is divided into three parts: encoding, erasing, and reading; the encoding and erasing operations of each information element have no chronological order, and the reading of information elements has a chronological order, and the corresponding encoding elements need to be read in sequence. The encoding process is based on the principle of joint learning. The memristor is initially in a high-impedance state. A single time event signal and environmental signal cannot significantly change the resistance state of the memristor. Only when the time signal and environmental signal are input at the same time can joint learning be formed. The memristor is changed from high resistance to low resistance, and the corresponding coding elements are coded and stored in the coding circuit. The erasing process is to input a positive pulse at the second, fourth, and sixth input terminals of the encoding circuit, so that the resistance changes from low resistance to high resistance, and the information stored in it is erased. The reading process is to input the read signal at the first, third, fifth, and seventh input terminals successively in chronological order, and output a series of pulse signals at the output terminal by means of voltage division. When the memristor is high resistance, the read signal If the divided voltage is small, it is considered that there is no corresponding encoding signal; when the memristor is low resistance, the read signal has a corresponding divided voltage, and it is considered that there is a corresponding encoded signal output.

The retrieval process of episodic memory is to match the memory trace signal with the external retrieval signal, obtain the corresponding episodic signal, and realize the recall of the event. In the situational memory retrieval circuit provided by the present invention, the initial state of the memristor is a high-impedance state, and the resistance state of the memristor cannot be changed by inputting the memory trace signal and the retrieval signal alone. Only by inputting the memory trace signal and the retrieval signal simultaneously can the memory The resistor is converted from high resistance to low resistance. Since the resistance value of the memristor has a gradual change characteristic, the change of its resistance value is affected by the number, amplitude and pulse width of the pulse signal applied to the device. The memory trace signal and the retrieval signal match The higher the degree, the greater the conversion will be. When the memristor is in a high-impedance state, the memory trace signal is input alone, and its output is almost zero, and it is considered that no memory is formed; when the memristor is in a low-impedance state, the memory trace signal is input alone, and the signal is divided by a resistor. With a corresponding output, it is considered to form a memory. According to the characteristics of episodic memory, the matching accuracy of engram signal and retrieval signal, the strength of engram signal, the complexity of engram signal, and the strength of retrieval signal will all affect episodic memory, and episodic memory has a certain degree of chaos. That is, in some cases, the same retrieval signal will be matched with different memory traces at the same time to achieve recall.

Referring to FIG. 4 is another embodiment of the present invention, which provides an encoding-reading method of an episodic memory encoding process. Fig. 4 (a) is the encoding-reading method of encoding three information elements in the episodic memory encoding process, in the encoding process, input the first encoding element event signal 401 and the corresponding read signal at the first input terminal 101 of the episodic memory circuit at the same time; The second input terminal 102 inputs the first coding element environment signal 402; the third input terminal 103 inputs the second coding element event signal 403 and the corresponding read signal; the fourth input terminal 104 inputs the second coding element environment signal 404; the fifth input The terminal 105 inputs the third encoding element event signal 405 and the corresponding read signal; the sixth input terminal 106 inputs the third encoding element environment signal 406; the seventh input terminal 107 inputs the extended element reading signal 407; 3, 5, and 7 input read signals must follow a certain time sequence; the output terminal 108 outputs the coded memory trace 408 stored in the circuit, which contains three information elements and one expansion element.

Fig. 4 (b) is the encoding-reading method of encoding two information elements in the episodic memory encoding process, in the encoding process, input the first encoding element event signal 409 and the corresponding read signal at the first input terminal 101 of the episodic memory circuit; The second input terminal 102 inputs the first coding element environment signal 410; the third input terminal 103 inputs the second coding element event signal 411 and the corresponding read signal; the fourth input terminal 104 inputs the second coding element environment signal 412; the fifth input Terminal 105 inputs the read signal 413 of the third encoding element; the seventh input terminal 107 inputs the extended element read signal 414; wherein, the input read signals at the first, third, fifth, and seventh input terminals must follow a certain time sequence; The output terminal 108 outputs the encoded memory trace 415 which is stored in the circuit and contains two information elements and one extension element.

Fig. 4 (c) is the encoding-reading method of encoding an information element in the episodic memory encoding process, in the encoding process, input the first encoding element event signal 416 and the corresponding read signal at the first input terminal 101 of the episodic memory circuit at the same time; The second input terminal 102 inputs the first coding element environment signal 417; the third input terminal 103 inputs the reading signal 418 of the second coding element; the fifth input terminal 105 inputs the reading signal 419 of the third coding element; the seventh input terminal 107 inputs the extension Element read signal 420; wherein, the input read signals at the first, third, fifth, and seventh input terminals must follow a certain time sequence; the output terminal 108 outputs encoded and stored in the circuit containing an information element and an extended element Memory Engram 421.

Fig. 4 (d) is the coding-reading method without coding element in the episodic memory coding process, in the coding process, input the read signal 422 of the first coding element at the first input end 101 of the episodic memory circuit at the same time; The third input end 103 inputs The read signal 423 of the second encoding element; the fifth input terminal 105 inputs the read signal 424 of the third encoding element; the seventh input terminal 107 inputs the extended element read signal 425; The input read signal at the terminal must be in a certain time sequence; at the output terminal 108, the encoded memory trace 426 containing an extended element stored in the circuit is output.

Referring to FIG. 5 is another embodiment of the present invention, which provides an erasing-reading method in the coding process of episodic memory.

Suppose when there are three encoded elements already stored in the encoding circuit. Fig. 5 (a) is the erasing-reading method of erasing an information element, in erasing process, the 6th input terminal 106 inputs forward erasing signal 504; Take signal 501, the third input terminal 103 inputs read signal 502, the fifth input terminal 105 inputs read signal 503, the seventh input terminal 107 inputs extended element read signal 505; the memory of erasing one element is output at output terminal 108 Trace 506.

Fig. 5 (b) is the erasing-reading method of erasing two information elements, in erasing process, the 4th input terminal 104 inputs forward erasing signal 509, the 6th input terminal 106 inputs forward erasing signal 511: input the read signal 507 at the first input terminal 101 in time order, input the read signal 508 at the third input terminal 103, input the read signal 510 at the fifth input terminal 105, and input the extended element read at the seventh input terminal 107 Signal 512 ; output at output 108 erased memory trace 513 of two elements.

Fig. 5 (c) is the erasing-reading method of erasing three information elements, in the erasing process, the second input terminal 102 inputs the forward erasing signal 515, and the fourth input terminal 104 inputs the forward erasing signal 517, the sixth input terminal 106 inputs the positive erasing signal 519; the first input terminal 101 inputs the read signal 514 in time sequence, the third input terminal 103 inputs the read signal 516, and the fifth input terminal 105 inputs the read signal Signal 518 , the seventh input terminal 107 inputs the expanded element read signal 520 ; the output terminal 108 outputs memory traces 521 for erasing three elements.

Fig. 6 is another embodiment provided by the present invention, which provides the operation method of the retrieval process of episodic memory and the influence of accuracy on episodic memory, wherein the accuracy is represented by the matching degree between memory trace signal and retrieval signal. The higher the accuracy, the easier it is to achieve episodic memory, and the lower the accuracy, the less likely it is to achieve episodic memory.

Figure 6(a) shows retrieval signals and engrams without encoding element matching. The memory trace signal 601 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses containing three encoding elements and one expansion element, which are respectively used to detect the situation of episodic memory recall before matching, Signal matching and episodic memory recall after matching; the corresponding memory trace signal 602 is output at the signal output 203 .

Figure 6(b) shows that the retrieval signal and the memory engram have an encoded element match. The memory trace signal 603 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses containing three encoding elements and one expansion element, which are respectively used to detect the situation of episodic memory recall before matching, Signal matching and episodic memory recall after matching; a retrieval signal 604 is input to the second input terminal 202 of the episodic memory retrieval circuit, wherein the retrieval signal contains a retrieval element that matches the memory trace; the corresponding memory trace signal 605 is output at the signal output 203 .

Figure 6(c) shows that the retrieval signal and the memory engram have two encoded elements that match. The memory trace signal 606 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses containing three coding elements and one expansion element, which are respectively used to detect the situation of episodic memory recall before matching, Signal matching and episodic memory recall after matching; the retrieval signal 607 is input at the second input end 202 of the episodic memory retrieval circuit, wherein the retrieval signal contains two retrieval elements that match the memory trace; the corresponding memory trace signal 608 is output at the signal output 203 .

Figure 6(d) shows that the retrieval signal and the memory engram have three encoding elements that match. The memory trace signal 609 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses containing three encoding elements and one expansion element, which are respectively used to detect the situation of episodic memory recall before matching, Signal matching and episodic memory recall after matching; the retrieval signal 610 is input at the second input terminal 202 of the episodic memory retrieval circuit, wherein the retrieval signal contains three retrieval elements that match the memory trace; the corresponding memory trace signal 611 is output at the signal output 203 .

Fig. 7 is another embodiment provided by the present invention, which provides the operation method of the episodic memory retrieval process and the influence of the retrieval signal strength on the episodic memory, wherein the retrieval signal strength is represented by the retrieval signal amplitude. The stronger the retrieval signal, the easier it is to realize episodic memory, and the weaker the retrieval signal, the less likely it is to realize episodic memory.

Fig. 7(a) shows the episodic memory retrieval operation when the retrieval signal strength is -1V. The memory trace signal 701 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses containing three encoding elements and one expansion element, which are respectively used to detect the situation of episodic memory recall before matching, Signal matching and episodic memory recall after matching; the retrieval signal 702 is input at the second input terminal 202 of the episodic memory retrieval circuit, wherein the retrieval signal contains three retrieval elements that match the memory trace, and the corresponding pulse amplitude is -1V; The output 203 outputs a corresponding engram signal 703 .

Fig. 7(b) shows the context memory retrieval operation when the retrieval signal strength is -1.5V. The memory trace signal 704 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses containing three coding elements and one expansion element, which are respectively used to detect the recall situation of the episodic memory before matching, Signal matching and episodic memory recall after matching; the retrieval signal 705 is input at the second input terminal 202 of the episodic memory retrieval circuit, wherein the retrieval signal contains three retrieval elements that match the memory trace, and the corresponding pulse amplitude is -1.5V; Signal output 203 outputs a corresponding engram signal 706 .

Fig. 8 is another embodiment provided by the present invention, which provides the operation method of the episodic memory retrieval process and the influence of engram strength on episodic memory, wherein the engram strength is represented by the amplitude of the engram signal. The stronger the memory trace, the easier it is to achieve episodic memory, and the weaker the memory trace, the less likely it is to achieve episodic memory.

Figure 8(a) is the episodic memory retrieval operation when the engram signal strength is 0.7V. The memory trace signal 801 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses containing three encoding elements with an amplitude of 0.7V and one expansion element, which are respectively used to detect matching Pre-episodic memory recall situation, signal matching and post-matching episodic memory recall situation; input retrieval signal 802 at the second input terminal 202 of episodic memory retrieval circuit, wherein the retrieval signal contains three retrieval elements and match the memory trace; output at signal output 203 The corresponding engram signal 803 .

Figure 8(b) is the episodic memory retrieval operation when the engram signal strength is 0.4V. The memory trace signal 804 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses containing three encoding elements with an amplitude of 0.4V and one expansion element, which are respectively used to detect matching Pre-episodic memory recall situation, signal matching and post-matching episodic memory recall situation; input retrieval signal 805 at the second input terminal 202 of episodic memory retrieval circuit, wherein retrieval signal contains three retrieval elements and match memory trace; output at signal output 203 The corresponding engram signal 806.

Fig. 9 is another embodiment provided by the present invention, which provides the operation method of the episodic memory retrieval process and the influence of memory trace complexity on episodic memory, wherein the complexity is represented by the number of coding elements. The more complex the memory trace, the less likely it is to realize episodic memory, and the simpler the memory trace, the easier it is to realize episodic memory.

Figure 9(a) is an episodic memory retrieval operation with a memory trace containing three encoding elements. The memory trace signal 901 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses including three coding elements and one expansion element, which are respectively used to detect the situation of episodic memory recall before matching , signal matching and episodic memory recall after matching; input retrieval signal 902 at the second input end 202 of episodic memory retrieval circuit, wherein retrieval signal contains three retrieval elements and memory trace match; output corresponding memory trace signal at signal output 203 903.

Figure 9(b) is an episodic memory retrieval operation with a memory trace containing six encoding elements. The memory trace signal 904 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses containing six coding elements and one expansion element, which are respectively used to detect the situation of episodic memory recall before matching , signal matching and episodic memory recall after matching; input retrieval signal 905 at the second input terminal 202 of episodic memory retrieval circuit, wherein the retrieval signal contains six retrieval elements and match memory trace; output corresponding memory trace signal at signal output 203 906.

Fig. 10 is another embodiment provided by the present invention, which provides an operation method of episodic memory retrieval and the influence of chaos on episodic memory; it shows that the same retrieval signal can be matched with different memory trace signals to generate episodic memory.

Figure 10(a) is an episodic memory retrieval operation where the same retrieval information is matched with a memory trace. The memory trace signal 1001 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical time sequence pulses containing two encoding elements (the first encoding element and the third encoding element) and one expansion element , are respectively used to detect episodic memory recall before matching, signal matching, and episodic memory recall after matching; the retrieval signal 1002 is input to the second input terminal 202 of the episodic memory retrieval circuit, wherein the retrieval signal contains three retrieval elements that match the memory trace ; Output the corresponding engram signal 1003 at the signal output 203 .

Figure 10(b) is an episodic memory retrieval operation where the same retrieval information is matched with another memory trace. The memory trace signal 1004 is input to the first input terminal 201 of the episodic memory retrieval circuit, wherein the memory trace signal is composed of three identical timing pulses containing two encoding elements (the second encoding element and the third encoding element) and one expansion element , are respectively used to detect episodic memory recall before matching, signal matching, and episodic memory recall after matching; the retrieval signal 1005 is input to the second input terminal 202 of the episodic memory retrieval circuit, wherein the retrieval signal contains three retrieval elements that match the memory trace ; Output the corresponding engram signal 1006 at the signal output 203 .

It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (9)

1. A memristor-based episodic memory circuit, characterized in that it comprises: an encoding circuit and a retrieval circuit connected in sequence; the encoding circuit comprises a first memristor M1, a second memristor M2, a third memristor Resistor M3, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4 and fifth resistor R5; One end of the first memristor M1 is used as the first input end (101) of the encoding circuit, and the other end of the first memristor M1 passes through the first resistor R1 and the first resistance R1 connected in series in sequence. Five resistors R5 are grounded, the other end of the first memristor M1 is used as the second input end (102) of the encoding circuit; one end of the second memristor M2 is used as the third input end of the encoding circuit (103), the other end of the second memristor M2 is used as the fourth input end (104) of the encoding circuit, and the other end of the second memristor M2 is also connected to the second resistor R2 One end, the other end of the second resistor R2 is connected to the series connection end of the first resistor R1 and the fifth resistor R5; one end of the third memristor M3 is used as the fifth input of the encoding circuit end (105), the other end of the third memristor M3 is used as the sixth input end (106) of the encoding circuit, and the other end of the third memristor M3 is also connected to the third resistor R3 One end of the third resistor R3, the other end of the third resistor R3 is connected to the series connection end of the first resistor R1 and the fifth resistor R5; one end of the fourth resistor R4 is used as the seventh input end of the encoding circuit (107), the other end of the fourth resistance R4 is connected to the series connection end of the first resistance R1 and the fifth resistance R5; the series connection end of the first resistance R1 and the fifth resistance R5 As the output terminal (108) of the encoding circuit; The retrieval circuit includes a memristor M and a fixed-value resistor R connected in series in sequence, and the non-serial end of the fixed-value resistor R and the memristor M is used as a first input terminal (201) of the retrieval circuit, The series terminal of the memristor M is used as the second input terminal (202) of the retrieval circuit, and the serial terminal of the memristor M is also used as the output terminal (203) of the retrieval circuit; The other end of R is grounded. 2. The episodic memory circuit according to claim 1, wherein the first memristor M1, the second memristor M2 and the third memristor M3 are the same, and the first memristor M3 The resistance value of the resistor R1, the resistance value of the second resistor R2, the resistance value of the third resistor R3 and the resistance value of the fifth resistor R5 are respectively equal to the low resistance value of the first memristor, and the resistance value of the fourth resistor R4 The resistance value is equal to half of the resistance value of the fifth resistor R5; the resistance value of the fixed value resistor is equal to the low resistance value of the first memristor. 3. The episodic memory circuit according to claim 1 or 2, characterized in that, the first input end (101) and the second input end (102) of the encoding circuit are respectively used to receive the event stimulation of the first encoding signal signals and environmental stimuli; The third input terminal (103) and the fourth input terminal (104) of the encoding circuit are respectively used to receive the event stimulus signal and the environment stimulus signal of the second encoding signal; The fifth input terminal (105) and the sixth input terminal (106) of the encoding circuit are respectively used to receive the event stimulus signal and the environment stimulus signal of the third encoding signal; The seventh input terminal (107) of the encoding circuit is used to receive the fourth encoding signal; The output terminal (108) of the encoding circuit is used to output the memory trace signal of episodic memory, and serves as the input signal of the retrieval circuit; Wherein the first coded signal, the second coded signal and the third coded signal are respectively used as three element signals of event, time and place of episodic memory content, and the fourth coded signal is used as memory content of episodic memory, Expansion to accommodate memory content. 4. The episodic memory circuit according to claim 2, wherein the first memristor comprises a first electrode layer (301), a functional material layer (302) and a second electrode layer (303) electrically connected in sequence ). 5. The episodic memory circuit according to claim 4, wherein the functional material layer is an oxide functional material layer _TiOx , _TaOx , _WOx , _CuOx , _AlOx , _NiOx , _HfOx , ZrO _x , _SiOx , _NbOx , _VOx or _GeOx . 6. The episodic memory circuit according to claim 4, wherein the functional material layer is a chalcogenide functional material layer GeSe, Ag ₂ Se, Ag ₂ S, Cu ₂ S, GeS _x , Ge ₂ Sb ₂ Te ₅ , GeTe or AgInSbTe. 7. The episodic memory circuit according to claim 4, wherein the functional material layer is a perovskite structure functional material layer SrTiO ₃ , BaTiO ₃ , BiFeO ₃ , CaMnO ₃ , PrMnO ₃ or La _0.7 Sr _0.3 MnO ₃ . 8. An operating method based on the episodic memory circuit according to claim 1, characterized in that, the operating method comprises an encoding step, an erasing step and a reading step; The encoding step includes: inputting the event signal of the first encoding information, the event signal of the second encoding information, the third encoding information respectively at the first input end (101) to the sixth input end (106) of the encoding circuit The event signal of the information, the environment signal of the first encoded information, the environment signal of the second encoded information and the environment signal of the third encoded information to realize the encoding operation; The erasing step includes inputting the erasing signal of the first encoded information, the second The erasure signal of the coded information and the erasure signal of the third coded information are used to realize the erasing operation; The reading step includes: applying a read signal sequentially to the first input terminal (101), the third input terminal (103), the fifth input terminal (105) and the seventh input terminal (107) of the encoding circuit , to read the corresponding coded information and extended information to form a series of timing pulses. 9. The operation method as claimed in claim 8, characterized in that, at the same time, the memory trace signal is input at the first input terminal (201) of the retrieval circuit, and the retrieval signal is input at the second input terminal (202), and the two After the signals are matched, the output terminal (203) outputs the episodic memory signal.