201246212 _ 六、發明說明： 【發明所屬之技術領域】 本案是關於一種記憶體陣列裝置’特別是關於不受溫度影 響的記憶體陣列裝置° 【先前技術】 傳統的相變化§己憶體彳呆作在早極模式(ujjjpolgj m〇de)，其 意謂著重設電流及設定電流的方向相同。記憶體狀態是藉由相 變化物質的相來定義，相包含用來作為高電阻狀態的非晶相 (amorphous)，以及用來作為低電阻狀態的結晶（ciystalHne) 相、。操作於單極模式下的記憶祕有小尺寸的記憶胞陣列、在 低溫的範圍(低於攝氏85)較佳的資料保存能力、以及可操作於 高速的優點。 _ :參閱第-圖⑷’其為習知記憶胞與單極定址電路⑴的 不忍圖。"己憶胞101包含第一電極10U、第二電極1012、以 第一電極職與第二電極1012之間的記憶材料 1013。 以及为；^路102包含電晶體103、位元線104、字元線105、 以及源極線1〇7。 圖。二ΓΓ *圖⑼’其為在單極操作下_極電壓的波形 二Γ"奈秒為單位哪代表電壓，以伏特為 極的電壓v的中的波形撕代表施加於電晶體103的閘 Vwu。在第1圖電壓Vgl等於施加於字元線105㈣壓 一健操作，該第a—的記憶胞101受到定址電路102的一第 偏壓操作可使記憶胞101程式化為高電阻 201246212 狀態。該第-偏壓操作包含：施加電屋I— ⑽、施加輕Vwl辦元線他、施 ·伏^ 電晶==編、以及施加電w特於 不才y 以及2奈秒，當電廢* :9,的上升期間-伏概地上升以伏特後= 持7G奈秒·，此時通過記憶胞⑽的電流為 :對車:爾流㈣〇微安培(如第一圖⑻所示)，然後電壓 如在2奈秒的下降_從2.4伏特快速地下降至Q伏特 ^F1形成的高紐及快速下降難，使記紐料咖形成 非晶相’該非晶相會形成記憶材料1013的高電阻狀態。 請參閱第一圖(c)，其為習知記憶胞與單極定址電路的示意 ^在第-圖⑹中的單極定址電路112與第一圖⑻中的單極 :址電路102的差異在於所施加於字元線105的電壓VwL2。 :參閱第其為在單極操作下的閘極電壓的波形圖。 橫軸代表_ .，以奈秒為單位’縱軸代表龍，錄特為單位。 在第一圖⑷中的波形搬代表施加於電晶體103的閘極電壓 Vg2的波形，_賴Vg2雜施加於字元線⑽㈣壓％。 在第一圖(d)中的記憶胞1〇1受到單極定址電路ι〇2的一第二 偏壓操作’娜二偏壓操作可使記憶胞1G1抹除為低電阻狀 態。該第二偏壓操作包含：施加電壓VBL1=4伏特於位元線 104、施加電壓Vwu於字元線105、施加電壓Vsub=〇伏特於 電晶體103的基底B、以及施加電歷Vsu=〇伏特於源極線1〇7。 在第一圖(d)中，波形的上升期間、波寬、以及下降 201246212 期間分別為100奈秒、400奈秒、以及細奈秒當電壓 在刚奈秒的上升期間從0伏特上升至12伏特後，電壓2 在I·2伏特維持400奈秒，此時通過記憶胞1〇1的電流為相 較低的電流12=350微安培(如第一圖(c)所示），然後電壓〜 在厕奈秒的下降期間從1.2伏特相對緩慢地下降至〇伏特。2 波形WF2形成的低電流及緩慢下降過程，使記㈣料ι〇ΐ3形 成結晶相，該結晶相會造成記憶材料1〇13的低電阻狀態。 雖然操作於單極模式下的由記憶胞1()1卿成的記憶胞 _具有較小尺寸、在低溫的(低簡氏8s)雛的資料保 存此力、以及可操作於高速的伽，但是當記，馳⑻在非晶 狀L下部很谷易叉到⑥溫的轉而產钱退火(麵峡），使 得材料由非晶相轉變為低電阻狀態的結晶相，也就是說，儲存 於德胞1G1的資料别⑧溫的影響而被抹除，此為操作於單 極模式下的記憶胞1〇1的缺點。 然而，另-種操作模式稱為雙極操作模式可使記憶胞不易 受溫度的影響。請參閱第工圖⑻，其為習知記憶胞與雙極定址 電路20的示意圖。記憶胞2〇1包含第三_2〇11、第四電極 觀、以及位於第三電極亂與第叫極加2之間的記憶材 枓測3。雙極定址電路2〇2包含電晶體2〇3、位元線綱、字 元線205、以及源極線207。 -月參閱第―圖⑼’其為在雙極操作下的閘極電壓的波形 ，。橫轴代表触’時秒為單位，_代表電壓，以伏特為 單位在第一圖(b)中的波形侧代表施加於電晶體的間 極電壓vgs的波形，閘極電壓％等於施加於字元線2〇5的電 201246212 壓Vwu。在第二圖⑻中的記憶胞2〇1受到定址電路2〇2的— 第三偏壓操作，該第三偏壓操作可使記憶胞2〇ι 阻狀態n餅猶衫：齡㈣雜 線204施加電壓於字元線205、施加電壓vsub=〇伏特 於電晶體203 _底b、以及施加電壓VsL2=4伏特於源極線 在第 圖(b)中，波形WF3的上升期間、波寬、以及下降 期間分別為100奈秒、4〇〇奈秒、以及2〇〇〇奈秒當電壓V祀 在100奈秒的上升期離0伏特上升至3 8伏特後電壓 在—伏特維持400奈秒，此時通過記憶胞2〇1的電流Ι3=· 微女如第二圖⑻所示），然後電壓Vwl2在2000奈秒的下降 ^從3.8伏特下降至G伏特。在該第三偏觀作巾會使記憶 13巾的電絕緣物質(未顯示)與其分離，而造成記憶材 料2013的高電阻狀態。 _ ‘圖(C)’其為習知記憶胞與雙極定址電路的示意 二。第二圖(c)中的雙極定址電路212與第二圖⑻中的雙極 疋址路202的差異在於：所施加於字元線 205的電壓Vwu、 堍207 ;位凡線2〇4的電壓VBL3=4伏特、以及所施加於源極 線207的電壓Vsu=〇伏特。 5月參閱第 圖第—圖⑷’其為在雙極操作下的閘極電壓的波形 圖。杈軸代表時間，1 單位。在筮- 秒為單位’縱轴代表電壓’以伏特為 極雷厭ν 一圖(d)中的波形綱代表施加於電晶體203的閘 壓Vwl Μ的波形，閣極電壓Vg4等於施加於字元線205的電 机4在第一_中的記憶胞2〇1受到雙極定址電路212 201246212 =偏:Γ ’該第四偏壓操作可使記憶胞2。1抹除為低 元绩"第四倾操作包含：脉電壓VBL3=4伏特於位 = 施加電壓、於字元線205、施加電壓Vsub=〇伏 ==晶體203的基底B、以及施加電壓1=〇伏特於源極 跟 2U7 〇 在第二_中，波形職的上升期間、波寬、以及下降 期間刀別為100奈秒、4〇〇奈秒、以及2_奈秒，當電壓^ f觸奈秒的上升期間從〇伏特上升至12伏特後，電壓V聰 丄·2伏特維持_奈秒，此時通過記憶胞201 的電流14=350 政女培(如第二_)所示）’然後糕Vwu在2000奈秒的下降 期間伏特下降至G伏特。由於該第四偏縣作與該第三 禹塑操作互為輕極性相反的操作，因此會使記憶材料2〇13 中的電絕緣物質至少—部分(未顯示)合併至其中，而造成記憶 材料2013的低電阻狀態。 雖然在雙極操作下的記憶胞2〇1不易受溫度的影響而使 資料被抹除’然而操作於雙極模式下的由記憶胞观所形成的 :己隐胞陣列部具有較大尺寸，而且在此模式下的偏壓電路也較 為複雜、以及操作速度較差。因此使記憶胞陣列兼具單極操作 與雙極操作下的優點為—重要的課題。 【發明内容】 有鑑於上述單極操作下記憶體陣列的缺點以及雙極操作 下記憶體_的缺點，—種記髓_裝置被提出，該記憶體 陣列裝置使用具有相同結構的記憶胞，唯—的差別在於不同的 偏壓電路的設計，其肋偏壓於記碰陣列，從製程的觀點而 201246212 5不需要增加額外的成本’而且兼具小尺寸、高記憶容量、可 操作於高速、不枝溫影響、高t寫次數、減高度可信賴的 資料保存能力。 依照上述構想，一種記憶體陣列裝置被提出，該記憶體陣 列裝置包含-記憶體陣列、—第—電路、以及_第二電路。該 誠體陣列包含-第—分部以及—第二分部，該第—分部包括 複數第-5己億胞，該第二分部包括複數第二記憶胞。該第一電 路電連接於該記憶體陣列，用以使該第一分部操作於一第一模 式。該第二電路電連接於該記憶體陣列，用以使該第二分部操 作於-第—模式，該第—模式為—雙極操作模式，該第二模式 為一單極操作模式。 、 照上述構想，另—種賴_膽置被提出，該記憶體 ^裝置包含-記憶體陣列，該記憶體陣列具複數記憶胞，該 複數記憶胞分獅作於—第—模式和—第二模式。 陣列構想’另—種記憶斷列裝置被翻，該記憶體 車歹m置記健_，該記紐 -第二分部。該第-分部操作在-第-操作模;中該二 部操作在-第二操作模式+。 ^这第-刀 依照上述構想，—種記憶體陣列裝置 該記憶體陣列裝置包含—第一分部及 乍方去被楗出 下歹J步驟加-雙極操作模式於該第 。 作模式於該第二分部。 七靶加-早極細 的操作方法被提 使用者可選擇將 依照上述構想，另一種記憶體陣列裝置 出’該方法包含下列步驟：以-可信賴方式， 201246212 資料儲存於該第—分部或該第二分部，方法包含下列步驟.施 加-雙極操倾式於該第-分部。施加—單極操作模式於 二分部。 、°义 依照上述構想.，另-種記憶體陣列裝置的操作方法被提 出，該方法包含下列步驟：區分—記憶體陣列為—第—種記憶 第二種她包。以一可信賴方式，於該第-種記憶胞儲 存-貝料’俾當該第二種記憶胞需要該資料時，自該第一種記 憶胞提供該資料給該第二種記憶胞。 依照上述構想，另一種記憶體陣列裝置的操作方法被提 法包含下列步驟：區分—記憶體_為—第—種記憶 二::一?ΐ憶胞、以一可信賴方式，於該第-種記憶胞儲 予貝;斗’俾當該第二種記憶胞流失該資料時 憶胞取得該資料。 ^ 【實施方式】 中提楚地且扼要地說明本發明’在下列的實施方式 1 了 &佳貫施例，細並极此為限。 _^第圖(a)，其為本案較佳實施例記憶體陣列裝置 =示意圖。該記憶斷職置3G包含—記憶斷列36、一 部路。該記憶體陣列36包含-第-分 二電路分別為;。在第三圖⑷中’該第-電路與該第 刀似偷偏壓電路32以及單極電路34。該第一 於-tr該記憶斷列36，____36操作 使該記憶二列電第：_車列36,用以 201246212 請參閱第三圖(b)，其為本案第一分部361操作於該第一 模式下的電路圖。在第三圖⑷中，第一分部361操作於該第一 模式下的電路37包含控制邏輯31、雙極偏壓電路32、以及第 一分部361。在第三圖(b)中，雙極偏壓電路32包含位元線解 碼器311、字元線解碼器與驅動器312、以及源極線控制單元 313。第一分部361包含複數記憶胞：記憶胞36ιι、記憶胞 3612、記憶胞3613、記憶胞3614，電晶體320、電晶體322、 電晶體324、電晶體326、位元線32卜位元線323、字元線 325、字元線327、以及源極線328、29。其中第一分部撕 的每一記憶胞是一次可程式化的或多次可程式化的。 在第三圖¢)中的雙極偏壓電路32可針對第一分部361中 不同的記憶胞分別做程式化或抹除的控制，舉例來說，在一第 -時段内對記憶胞3611利用該第三偏祕作進行程式化，則 源極線控制單元313解碼至源極線328並提供4伏特於 328、位元線解 311解碼至位元線321並提供〇伏特於位 兀線321、以及字元線解碼器與驅動器312解碼至字元線325 並提供閘極電壓vg3。在-第二時段内對記憶胞3613利用該第 四偏壓操作進行抹除，則源極線控制單元313解碼至源極線 328並提供〇伏特於源極線328、位元線解碼ϋ 311解碼至位 元，321並提供4伏特於位元線32卜以及字元線解碼器與驅 動f 解碼至字元線327錄供閘極電塵Vg4，依此類推。 值得注意的是，雙極偏壓電路32的設計㈣應雙極操作模式 (Γ第一f式)的設計’其源極線328、329必須分開接至源i 、、控制單το 313，®此在設計上較為娜，所佔的面積也比較 201246212 大，但是禮她齡對於轉 響而造成資料的遺失。 』寡度阿，不受溫度影 請翏閲第三圖(C)，其為本: •第 式下的電路圖。在第三圖(c);=:==該第二模 式下的電路38包含控制邏輯3 '、®第-模 分部淑。在第三陶中，单極倾電 =字:線解碼器與_ 312、以及源極線:= 第一刀。p 362包含複數記憶胞：記憶胞⑽ 電曰曰體344、電晶體346、位元線34卜位元線祕、字元線 345、字兀線347、以及源極線348。其中第二分部尬的每— 記憶胞是多次可程式化的。 在第三_)中的單極偏壓電路34可針對第二分部362中 不同的記憶胞分別做程式化或抹除的控制，舉例來說，在一第 三時段内對記龍3621 該第—偏難作進行程式化，則 源極線348接地、位元線解碼器311解碼至位元線341並提供 4伏特於位元線341、以及字元線解碼器與驅動器312解碼至 子元線345並提供閘極電壓vgl。在一第四時段内利用該第二 偏壓操作對記憶胞3623進行抹除，則源極線348接地、位元 線解碼器311解碼至位元線341並提供4伏特於位元線341、 以及字元線解碼器與驅動器312解碼至字元線347並提供閑極 電壓Vg2，依此類推。值得注意的是，單極偏壓電路34的設計 疋因應单極操作模式(即第二模式)的設計’其源極線348可共 同接在一起，、因此在設計上較為簡單，所佔的面積也比較小，201246212 _ VI. Description of the invention: [Technical field of the invention] The present invention relates to a memory array device 'especially for a memory array device that is not affected by temperature. [Prior Art] Conventional phase change § 己 彳 彳In the early pole mode (ujjjpolgj m〇de), it means that the direction of setting the current and setting the current is the same. The state of the memory is defined by the phase of the phase change substance, which contains an amorphous phase used as a high resistance state and a crystal (ciystal Hne phase) used as a low resistance state. The memory operating in unipolar mode has a small size memory cell array, a good data retention capability in the low temperature range (below 85 degrees Celsius), and the advantage of being able to operate at high speed. _ : Refer to the figure - (4)' which is an unbearable picture of the conventional memory cell and the unipolar addressing circuit (1). "Recalling cell 101 comprises a first electrode 10U, a second electrode 1012, and a memory material 1013 between the first electrode and the second electrode 1012. And the circuit 102 includes a transistor 103, a bit line 104, a word line 105, and a source line 1〇7. Figure. 2 ΓΓ * Figure (9) 'It is the waveform of the _ pole voltage under unipolar operation." The nanosecond is the unit of voltage. The waveform in the voltage v of volts represents the gate applied to the transistor 103. . In Fig. 1, the voltage Vgl is equal to the voltage applied to the word line 105. The first a-side memory cell 101 is subjected to a first bias operation of the addressing circuit 102 to program the memory cell 101 into a high-resistance 201246212 state. The first-bias operation includes: applying the electric house I-(10), applying the light Vwl line, the volt, the electric crystal== knitting, and applying the electric w to the special y and the second nanosecond, when the electric waste * :9, the rising period - volts rises in general after volts = 7G nanoseconds. At this time, the current through the memory cell (10) is: for the car: the flow (four) 〇 microamperes (as shown in the first figure (8)) Then, the voltage drops as fast as 2 nanoseconds _ from 2.4 volts to 2.4 volts, and the volts formed by the FF ^F1 are difficult to form, so that the amorphous phase forms an amorphous phase. The amorphous phase will form the memory material 1013. High resistance state. Please refer to the first figure (c), which is a schematic diagram of a conventional memory cell and a unipolar addressing circuit. The difference between the unipolar addressing circuit 112 in the first figure (6) and the unipolar address circuit 102 in the first figure (8). It is the voltage VwL2 applied to the word line 105. : Refer to the waveform diagram of the gate voltage under unipolar operation. The horizontal axis represents _. In nanoseconds, the vertical axis represents the dragon, and the recording is a unit. The waveform in the first figure (4) represents the waveform of the gate voltage Vg2 applied to the transistor 103, and _ V Vg2 is applied to the word line (10) (four) voltage %. The memory cell 1〇1 in the first figure (d) is subjected to a second bias operation of the single-pole addressing circuit ι〇2, and the nano-bias operation can erase the memory cell 1G1 to a low resistance state. The second biasing operation includes: applying a voltage VBL1 = 4 volts to the bit line 104, applying a voltage Vwu to the word line 105, applying a voltage Vsub = 〇 volts to the substrate B of the transistor 103, and applying an electrical history Vsu = 〇 Volt is at the source line 1〇7. In the first diagram (d), the rise period, the wave width, and the fall 201246212 of the waveform are 100 nanoseconds, 400 nanoseconds, and fine nanoseconds, respectively, when the voltage rises from 0 volts to 12 during the rise of the nanoseconds. After volts, the voltage 2 is maintained at 400 nanoseconds at 1.2 volts, at which time the current through the memory cell 1〇1 is the lower current 12=350 microamperes (as shown in the first figure (c)), then the voltage ~ During the fall of the toilet nanoseconds, from 1.2 volts to a relatively slow underground to 〇 volts. 2 The low current and slow descent process formed by the waveform WF2 causes the (4) material ι〇ΐ3 to form a crystalline phase, which causes a low resistance state of the memory material 1〇13. Although the memory cell operated by the memory cell 1 () 1 in the unipolar mode has a smaller size, the data in the low temperature (low Jane's 8 s) chicks preserves this force, and is operable at high speed gamma, However, when it is recorded, Chi (8) is in the lower part of the amorphous L. It is easy to fork to 6 temperature and then to produce an annealing (face gorge), which causes the material to change from amorphous phase to crystalline phase of low resistance state, that is, storage. The data of Yude 1G1 was erased by the influence of 8 temperature, which is a disadvantage of the memory cell 1〇1 operating in the unipolar mode. However, another mode of operation, called the bipolar mode of operation, makes the memory cells less susceptible to temperature. Please refer to the figure (8), which is a schematic diagram of a conventional memory cell and bipolar addressing circuit 20. The memory cell 2〇1 includes a third _2〇11, a fourth electrode view, and a memory material 位于3 located between the third electrode disorder and the first electrode. The bipolar addressing circuit 2〇2 includes a transistor 2〇3, a bit line class, a word line 205, and a source line 207. - Month refers to Figure - (9)' which is the waveform of the gate voltage under bipolar operation. The horizontal axis represents the time in seconds, _ represents the voltage, and the waveform side in the first figure (b) represents the waveform of the inter-pole voltage vgs applied to the transistor in volts. The gate voltage % is equal to the word applied to the word. Yuan 2〇5's electricity 201246212 pressure Vwu. The memory cell 2〇1 in the second figure (8) is subjected to a third bias operation of the addressing circuit 2〇2, and the third biasing operation can cause the memory cell to be in a state of 〇ι 状态 n : : : : : : : : : : : : : : : : 204 applies a voltage to the word line 205, applies a voltage vsub=〇Vat to the transistor 203_bottom b, and applies a voltage VsL2=4 volts to the source line. In the figure (b), the rising period of the waveform WF3, the wave width And the falling period is 100 nanoseconds, 4 nanoseconds, and 2 nanoseconds respectively. When the voltage V祀 rises from 0 volts to 3 8 volts in the rising period of 100 nanoseconds, the voltage is maintained at 400 volts. Second, at this time, the current through the memory cell 2〇1=· micro female is as shown in the second figure (8), and then the voltage Vwl2 drops from 3.8 volts to G volts at 2000 nanoseconds. The third biasing wiper separates the electrically insulating material (not shown) of the memory 13 from it, resulting in a high resistance state of the memory material 2013. _ ‘Fig. (C)’ is a schematic representation of a conventional memory cell and a bipolar addressing circuit. The difference between the bipolar addressing circuit 212 in the second figure (c) and the bipolar address path 202 in the second figure (8) is: the voltages Vwu, 堍207 applied to the word line 205; the line 2〇4 The voltage VBL3 = 4 volts, and the voltage applied to the source line 207 Vsu = 〇 volts. Refer to Figure - Figure (4)' for the waveform of the gate voltage under bipolar operation. The x axis represents time, 1 unit. In the 筮-second unit, the vertical axis represents the voltage 'in volts, and the waveform in the figure (d) represents the waveform of the gate voltage Vwl Μ applied to the transistor 203. The gate voltage Vg4 is equal to the word applied to the word. The memory 4 of the motor 4 of the first line 205 is subjected to the bipolar addressing circuit 212 in the first _2012 20121212 = bias: Γ 'The fourth bias operation can erase the memory cell 2. 1 to a low probability " The fourth tilting operation includes: pulse voltage VBL3 = 4 volts in place = applied voltage, word line 205, applied voltage Vsub = 〇 = = base B of crystal 203, and applied voltage 1 = 〇 volts at the source 2U7 〇 In the second _, the rising period, the wave width, and the falling period of the waveform are 100 nanoseconds, 4 nanoseconds, and 2_nsec, when the voltage is f After the volts rise to 12 volts, the voltage V 丄 丄 2 volts maintains _ nanoseconds, at this time the current through the memory cell 201 14 = 350 政女培 (as shown in the second _)) then the cake Vwu in 2000 The volt drops to G volts during the second drop. Since the fourth partial county performs the opposite operation to the third plastic molding operation, at least a part (not shown) of the electrical insulating material in the memory material 2〇13 is incorporated into the memory material. The low resistance state of 2013. Although the memory cell 2〇1 under bipolar operation is not susceptible to temperature, the data is erased. However, it is formed by the memory cell view in the bipolar mode: the cell array has a larger size. Moreover, the bias circuit in this mode is also complicated and the operation speed is poor. Therefore, the advantages of both the unipolar operation and the bipolar operation of the memory cell array are important issues. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the memory array under unipolar operation and the disadvantages of the memory under the bipolar operation, a magnetic recording device is proposed, which uses a memory cell having the same structure, The difference lies in the design of different bias circuits, the ribs being biased to the collision array, from the viewpoint of the process, 201246212 5 does not need to add extra cost' and has a small size, high memory capacity, and can operate at high speed. , the ability to save data without the influence of temperature, high t write times, and high reliability. In accordance with the above concept, a memory array device is proposed which includes a memory array, a first circuit, and a second circuit. The honest array includes a - part - and a second part, the first part comprising a plurality of -5 billion cells, the second part comprising a plurality of second memory cells. The first circuit is electrically coupled to the memory array for operating the first sub-portion in a first mode. The second circuit is electrically coupled to the memory array for operating the second portion in a -first mode, the first mode being a bipolar mode of operation and the second mode being a unipolar mode of operation. According to the above concept, another method is proposed, the memory device comprises a memory array, the memory array has a plurality of memory cells, and the plurality of memory cells are made in the first mode and the first Two modes. Array conception </ RTI> Another type of memory break device is turned over, and the memory 歹m remembers the health _, the note - the second branch. The first-part operation is in the -first-operation mode; the two operations are in the -second mode of operation +. ^This knives According to the above concept, a memory array device includes a first portion and a second portion to be extracted. The J-step plus-bipolar operation mode is in the first step. The mode is in the second division. The seven-target plus-early-fine operation method is selected by the user to select another memory array device according to the above concept. The method includes the following steps: in a -trusted manner, 201246212 data is stored in the first division or The second sub-portion includes the following steps: applying-bipolar steering to the first sub-portion. Apply - the unipolar mode of operation is in the second division. According to the above concept, another method of operating a memory array device is proposed, which comprises the following steps: distinguishing - the memory array is - the first type of memory, the second type of her package. In a trustworthy manner, the first type of memory cell stores the material from the first type of memory cell to the second type of memory cell when the second type of memory cell requires the data. According to the above concept, another method of operating a memory array device is proposed to include the following steps: distinguishing - memory _ is - first - memory two:: one ΐ memory, in a trustworthy manner, in the first - The memory cell is stored in the shell; the bucket's memory is obtained when the second memory cell loses the data. [Embodiment] The present invention has been described in detail and hereinafter, in the following embodiments, a preferred embodiment is limited thereto. Figure (a), which is a memory array device of the preferred embodiment of the present invention = schematic view. The memory disconnected 3G includes - memory break 36, a road. The memory array 36 includes a -first-differential circuit; In the third diagram (4), the first circuit and the first knife are similar to the bias circuit 32 and the unipolar circuit 34. The first in-tr memory breaks 36, the ____36 operation causes the memory to be in the second row: _car 36, for 201246212, see the third figure (b), which is the first branch 361 of the present case Circuit diagram in the first mode. In the third diagram (4), the circuit 37 in which the first subsection 361 operates in the first mode includes a control logic 31, a bipolar bias circuit 32, and a first subsection 361. In the third diagram (b), the bipolar bias circuit 32 includes a bit line decoder 311, a word line decoder and driver 312, and a source line control unit 313. The first subsection 361 includes a plurality of memory cells: memory cell 36 ιι, memory cell 3612, memory cell 3613, memory cell 3614, transistor 320, transistor 322, transistor 324, transistor 326, bit line 32 bit line 323, word line 325, word line 327, and source lines 328, 29. Each memory cell that is torn by the first segment is once programmable or multi-programmable. The bipolar bias circuit 32 in the third diagram can perform programmatic or erase control for different memory cells in the first subsection 361, for example, for a first time period. 3611 is programmed by the third partial secret, and the source line control unit 313 decodes to the source line 328 and provides 4 volts to 328, the bit line solution 311 decodes to the bit line 321 and provides the 〇 volts in the bit 兀Line 321 and word line decoder and driver 312 are decoded to word line 325 and provide gate voltage vg3. The memory cell 3613 is erased by the fourth bias operation during the second period, and the source line control unit 313 decodes to the source line 328 and provides the source line 328 and the bit line decoding 311 311. Decoded to bit 321 and provides 4 volts to bit line 32 and word line decoder and driver f decoded to word line 327 for gate electric dust Vg4, and so on. It is worth noting that the design of the bipolar bias circuit 32 (4) should be in the design of the bipolar mode of operation (Γ first f-type) whose source lines 328, 329 must be separately connected to the source i, and the control unit το 313, ® This design is more versatile, and the area occupied is larger than 201246212, but the age of her is lost due to the reverberation. "Oh, ignorance of temperature, please refer to the third picture (C), which is: • Circuit diagram under the formula. In the third diagram (c); =:== the circuit 38 in the second mode contains the control logic 3', the modulo-module section. In the third pottery, unipolar tilt = word: line decoder and _ 312, and source line: = first knife. p 362 includes a plurality of memory cells: a memory cell (10) an electrical body 344, a transistor 346, a bit line 34 bit line secret, a word line 345, a word line 347, and a source line 348. Each of the memory cells of the second segment is programmable multiple times. The unipolar bias circuit 34 in the third _) can perform programmatic or erase control for different memory cells in the second sub-section 362, for example, in the third period of time, the chronograph 3621 The first-prediction is stylized, the source line 348 is grounded, the bit line decoder 311 is decoded to the bit line 341 and provides 4 volts to the bit line 341, and the word line decoder and driver 312 decodes to The sub-line 345 also provides a gate voltage vgl. The memory cell 3623 is erased by the second biasing operation during a fourth period, the source line 348 is grounded, the bit line decoder 311 is decoded to the bit line 341 and 4 volts is provided to the bit line 341, And the word line decoder and driver 312 decodes to word line 347 and provides the idle voltage Vg2, and so on. It should be noted that the design of the unipolar bias circuit 34 is responsive to the design of the unipolar mode of operation (ie, the second mode). The source lines 348 can be connected together, and thus are relatively simple in design. The area is also small,
1J 201246212 且在操作上則更為快速，製造成本亦較低。 在本案所提第一分部361以及第二分部362中的記憶胞都 具有相同的記憶胞結構’且具有相同的材料，主要的差別則在 於雙極偏壓電路32與單極偏壓電路34的差異及第—分部划 與第二分部362中的陣列電路(源極線)設計不同，因此就製程 上峨點來看並不會有額外的成本與工程。在設計上可設計成 第-分部361佔所有記憶胞的小部分.，例如2%，而第二分部 362佔所有記憶胞的大部分，例如98%，這樣的設計可以^小 的面積(或體積)得到較大的記憶體容量，但也可以是任意的比 例關係，依使用者的需求而定。 〜 f社’例如在量產的雜中，重要㈣料(例如開機 碼)可先燒錄於本案所提的記憶體陣列裝置3〇的第一分部如 中，然後將記憶體陣列裝置30焊接或打件於電路板^然後 在該記憶體陣列裝置3〇接通錢後的初始_中，重要的資 料從第一分部361被解壓或載入到第二分部362，以用於後續 的直接執行。當重要的資料被解壓縮到該第二分部362時，所 要資料被驗證’錄用者需求而定。當然使用者亦 可將資料寫入第二分部362，亦依照使用者 由於焊接時所產生的高溫不會影響到第—分部361中的 記憶胞而造成龍遺失，故記髓陣顺置Μ且有可 資料保存能力。由於開機後資料儲存於第二分部尬可祕直 因此記憶體陣繼具有高速操作及低製造成本 上述重要㈣料包純編_馬，這匈_是特定資 12 201246212 料、複數J[接可執行程式媽、具有複數自我解壓縮碼的複數壓 縮程式碼、或其任意組合。 凊參閱第四@ ’其為本案記憶辦膽置3G的操作方法 的流程圖。記憶體陣列裝置30包含第一分部361及第二分部 362該方法包含下列步驟··施加一雙極操作於該第一分部 361(步驟S401);及施加一單極操作於該第二分部娜步驟 S402)。在焊接記憶體陣列裝置3〇至電路板上之前，經由施加 一雙極操作於該第-分部361，使資料以一種可信賴的方式先 儲存到第一分部36卜然後待焊接完畢後，於第一次通電時， 、”里由施力σ單極操作於該第二分部脱，使該資料從該第一分 部361載入至該第二分部362。 »月參閱第五圖’其為本案另一實施例記憶體陣列裝置30 的操作方法的流程圖，該方法包含下列步驟：區分一記憶體陣 列為一第一種記憶胞及一第二種記憶胞(步驟S501);及以一可 信賴方式，於該第-種記憶胞儲存一資料，俾當該第二種記憶 胞需要該資料時’自該第一觀憶胞提供該資料給該第二種記 憶胞(步驟S502)。 ° 。4參閱第六圖’其為本案另_實施例記紐陣列裝置％ 的操作方法的流程圖，該方法包含下列步驟：區分一記憶體陣 列為一第一種記憶胞及一第二種記憶胞(步驟S601);及以-可 信=方式’於該第一種記憶胞儲存一資料，俾當該第二種記憶 月已机失該資料時，自該第一種記憶胞取得該資料(步驟s⑼2)。 紅上所述，本發明的說明與實施例已揭露於上，然其非用 來限制本發明，凡習知此技藝者，在不脫離本發明的精神與範 201246212 蓋範^之^领麵更轴修飾，其仍制在本制專利的涵 【圖式簡單說明】 irr(a): f知記憶胞解較址電路的示意圖； (b).早極操作τ_極電壓的波形圖； ΚΊ知記憶胞解極纽電路的示意圖，· 圖(d) ·單極操作下的難麵的波形圓； =圖⑻：習知記憶胞與雙極定址電路的示意圖；1J 201246212 is also faster in operation and lower in manufacturing costs. The memory cells in the first sub-section 361 and the second sub-section 362 of the present invention all have the same memory cell structure' and have the same material, the main difference being the bipolar bias circuit 32 and the unipolar bias. The difference and the first division of the circuit 34 are different from the array circuit (source line) design in the second portion 362, so there is no additional cost and engineering in terms of process. It can be designed such that the first-division 361 occupies a small portion of all memory cells, for example 2%, while the second sub-section 362 occupies most of all memory cells, for example 98%, such a design can be a small area (or volume) to get a larger memory capacity, but can also be any proportional relationship, depending on the needs of the user. ~ f社' For example, in mass production, the important (four) material (such as the boot code) can be first burned in the first part of the memory array device 3 of the present case, and then the memory array device 30 Soldering or marking the board to the board ^ and then in the initial _ after the memory array device 3 is turned on, the important data is decompressed from the first portion 361 or loaded into the second portion 362 for use in Subsequent direct execution. When important data is decompressed to the second branch 362, the desired information is verified by the user's needs. Of course, the user can also write the data into the second branch 362, and the dragon is lost according to the user's high temperature generated during welding, which does not affect the memory cells in the first branch 361. And there is data storage capacity. Since the data is stored in the second branch after booting, it can be secret. Therefore, the memory array has high-speed operation and low manufacturing cost. The above-mentioned important (four) material package is purely _ horse, this Hungarian _ is a specific capital 12 201246212 material, plural J [ An executable program, a complex compressed code having a plurality of self-decompressing codes, or any combination thereof.凊 Refer to the fourth @ ’ ” flowchart for the operation method of the 3G operation. The memory array device 30 includes a first sub-section 361 and a second sub-section 362. The method includes the following steps: applying a bipolar operation to the first sub-section 361 (step S401); and applying a unipolar operation to the Divided into steps S402). Before soldering the memory array device 3 to the circuit board, the bi-polar operation is applied to the first sub-portion 361, so that the data is first stored in the first sub-section 36 in a reliable manner and then after being soldered. When the first power is turned on, "the unipolar operation of the unipolar operation is performed on the second branch, so that the data is loaded from the first branch 361 to the second branch 362. FIG. 5 is a flowchart of a method for operating the memory array device 30 of another embodiment of the present invention, the method comprising the steps of: distinguishing a memory array into a first memory cell and a second memory cell (step S501) And storing, in a trustworthy manner, a data in the first memory cell, and when the second memory cell requires the data, 'providing the data from the first memory cell to the second memory cell (Step S502). 4 Refer to the sixth figure, which is a flowchart of the operation method of the embodiment of the present invention. The method comprises the following steps: distinguishing a memory array into a first type of memory cell. And a second type of memory cell (step S601); and in - trusted = way 'Storing a data in the first type of memory cell, and when the second memory month has lost the data, the data is obtained from the first type of memory cell (step s(9) 2). The red is described above, the present invention The description and examples have been disclosed above, but are not intended to limit the invention, and those skilled in the art will be able to make further modifications without departing from the spirit of the invention and the scope of the model 201246212. The stipulations of this patent [simplified description] irr (a): f know the schematic diagram of the memory cell solution; (b) the waveform of the τ_pole voltage of the early pole operation; the knowing the memory cell Schematic diagram, · (d) · Difficult waveform circle under unipolar operation; = Figure (8): Schematic diagram of a conventional memory cell and bipolar addressing circuit;
Kb) ··雙極操作下的_電壓的波形圖； 第二圖(〇:習知記憶胞與雙極定址電路的示意圖； 第二圖(d) :雙極操作下的間極電壓的波形圖； 第三圖⑻：本案較佳實施例記鐘_裝置的示意圖. =圖阶本案第—分部操作於該第—模式下的電路圖； -圖(c).本案第二分部操作於該第二模式下的電路圖； 第四圖本案記憶辦列裝置輯作方法的流程圖；Kb) · waveform diagram of _ voltage under bipolar operation; second diagram (〇: schematic diagram of conventional memory cell and bipolar addressing circuit; second diagram (d): waveform of interpole voltage under bipolar operation Figure 3; Figure 3 (8): The clock of the preferred embodiment of the present invention - the schematic diagram of the device. = Figure 1: The circuit of the first part of the case operates in the first mode; - Figure (c). The second part of the case operates on The circuit diagram in the second mode; the fourth diagram is a flowchart of the method for compiling the memory device;
第五圖：本案另一實施例記憶體陣列裝置的操作方法的 圖；以及 "IL 第六圖：本案另一實施例記憶體陣列裝置的操作方法的流轾 圖。 刀 【主要元件符號說明】 10, 11 :習知記憶胞與單極偏壓101，201:記憶胞 電路 1011 :第一電極 1012:第二電極 1013, 2013 :記憶材料 102,112 :單極定址電路 201246212 103,203:電晶體 105,205:字元線 20 :習知記憶胞與雙極偏壓電 路 2012 :第四電極 30 :記憶體陣列裝置 32 :雙極偏壓電路 36 :記憶體陣列 362:第二分部 38 ::第二分部操作於該第二模 式下的電路 321，323, 341，343 :位元線 104, 204 :位元線 107,207:源極線 2011••第三電極 202,212:雙極定址電.路 31 :控制邏輯 34 :單極偏壓電路 361·.第一分部 37 :第一分部操作於該第一模 式下的電路 3611， 3612， 3613， 3614， 3621， 3622, 3623,3624:記憶胞 325, 327, 345, 347 :字元線 320, 322, 324, 326, 340, 342, 311:位元線解碼器 344,346:電晶體 312 :字元線解碼器與驅動器 313 :源極線控制單元 15Figure 5 is a diagram showing the operation method of the memory array device of another embodiment of the present invention; and <IL Figure 6: Flow chart of the operation method of the memory array device of another embodiment of the present invention. Knife [Main component symbol description] 10, 11 : conventional memory cell and unipolar bias 101, 201: memory cell circuit 1011: first electrode 1012: second electrode 1013, 2013: memory material 102, 112: unipolar address circuit 201246212 103, 203: transistor 105, 205: word line 20: conventional memory cell and bipolar bias circuit 2012: fourth electrode 30: memory array device 32: bipolar bias circuit 36: memory array 362: second Division 38: The second division operates in the second mode of circuits 321, 323, 341, 343: bit line 104, 204: bit line 107, 207: source line 2011 • • third electrode 202, 212: double Polar Addressing Circuit 31: Control Logic 34: Unipolar Bias Circuit 361.. First Division 37: The first branch operates in the first mode of circuits 3611, 3612, 3613, 3614, 3621, 3622 , 3623, 3624: Memory Cell 325, 327, 345, 347: Word Lines 320, 322, 324, 326, 340, 342, 311: Bit Line Decoder 344, 346: Transistor 312: Word Line Decoder and Driver 313: source line control unit 15