TWI490859B - Memory array device and method of operating the same - Google Patents

Description

Memory array device and method of operating same

This case relates to a memory array device, and more particularly to a memory array device that is not affected by temperature.

The conventional phase change memory operates in a unipolar mode, which means that the direction of the set current and the set current are the same. The state of the memory is defined by the phase of the phase change material, which contains an amorphous phase for use as a high resistance state and a crystalline phase for use as a low resistance state. The memory cells operating in the unipolar mode have a small size memory cell array, a good data retention capability in a low temperature range (below 85 degrees Celsius), and an advantage of being operable at high speed.

Please refer to the first figure (a), which is a schematic diagram of a conventional memory cell and unipolar addressing circuit 10. The memory cell 101 includes a first electrode 1011, a second electrode 1012, and a memory material 1013 between the first electrode 1011 and the second electrode 1012. The unipolar addressing circuit 102 includes a transistor 103, a bit line 104, a word line 105, and a source line 107.

Please refer to the first diagram (b), which is a waveform diagram of the gate voltage under unipolar operation. The horizontal axis represents time in nanoseconds and the vertical axis represents voltage in volts. The waveform of the voltage V _g1 represents a first waveform WF1 view (b) is applied to the gate electric crystal 103, is equal to the voltage V _g1 is applied to the word line voltage V _WL1 105 is. The memory cell 101 in the first diagram (a) is subjected to a first bias operation of the addressing circuit 102, which can cause the memory cell 101 to be programmed into a high resistance state. The first biasing operation includes applying a voltage V _BL1 = 4 volts to the bit line 104, applying a voltage V _WL1 to the word line 105, applying a voltage Vsub = 0 volt to the substrate B of the transistor 103, and applying a voltage V _SL1 =0 volts on source line 107.

In the first diagram (b), the rising period, the wave width, and the falling period of the waveform WF1 are 19 nanoseconds, 70 nanoseconds, and 2 nanoseconds, respectively, when the voltage V _WL1 rises from 0 volts during the rise of 19 nanoseconds. After rapidly rising to 2.4 volts, the voltage V _{WL1 is} maintained at 2.4 nanoseconds at 2.4 volts, at which time the current through the memory cell 101 is a relatively high current I1 = 600 microamperes (as shown in the first diagram (a)), The voltage V _WL1 then quickly drops from 2.4 volts down to 0 volts during a 2 nanosecond drop. The high current and rapid descent process formed by the waveform WF1 causes the memory material 1013 to form an amorphous phase which will form a high resistance state of the memory material 1013.

Please refer to the first figure (c), which is a schematic diagram of a conventional memory cell and a unipolar addressing circuit. The difference between the unipolar addressing circuit 112 in the first diagram (c) and the unipolar addressing circuit 102 in the first diagram (a) is the voltage V _WL2 applied to the word line 105. Please refer to the first diagram (d), which is a waveform diagram of the gate voltage under unipolar operation. The horizontal axis represents time in nanoseconds and the vertical axis represents voltage in volts. The waveform WF2 in the first diagram (c) represents the waveform of the gate voltage V _g2 applied to the transistor 103, and the gate voltage V _g2 is equal to the voltage V _WL2 applied to the word line 105. The memory cell 101 in the first diagram (d) is subjected to a second bias operation of the monopole addressing circuit 102, which erases the memory cell 101 to a low resistance state. The second biasing operation includes: applying a voltage V _BL1 = 4 volts to the bit line 104, applying a voltage V _WL2 to the word line 105, applying a voltage Vsub = 0 volt to the substrate B of the transistor 103, and applying a voltage V _SL1 =0 volts on source line 107.

In the first diagram (d), the rising period, the wave width, and the falling period of the waveform WF2 are 100 nanoseconds, 400 nanoseconds, and 2000 nanoseconds, respectively, when the voltage V _WL2 rises from 0 volts during the rise of 100 nanoseconds. After rising to 1.2 volts, the voltage V _{WL2 is} maintained at 400 _ns at 1.2 volts, at which time the current through the memory cell 101 is a relatively low current I2 = 350 microamperes (as shown in Figure (c)), then the voltage V _WL2 drops relatively slowly from 1.2 volts to 0 volts during a 2000 nanosecond drop. The low current and slow descent process formed by the waveform WF2 causes the memory material 1013 to form a crystalline phase which causes a low resistance state of the memory material 1013.

Although the memory cell array formed by the memory cell 101 operating in the unipolar mode has a smaller size, a better data retention capability in a low temperature range (less than 85 degrees Celsius), and an advantage of being operable at a high speed, when The memory cell 101 is easily exposed to high temperature in an amorphous state to cause thermal annealing, so that the material is transformed from an amorphous phase to a crystalline phase of a low resistance state, that is, the data stored in the memory cell 101 is subjected to It is erased by the influence of high temperature, which is a disadvantage of the memory cell 101 operating in the unipolar mode.

However, another mode of operation, called the bipolar mode of operation, makes the memory cells less susceptible to temperature. Please refer to the second figure (a), which is a schematic diagram of a conventional memory cell and bipolar addressing circuit 20. The memory cell 201 includes a third electrode 2011, a fourth electrode 2012, and a memory material 2013 between the third electrode 2011 and the fourth electrode 2012. The bipolar addressing circuit 202 includes a transistor 203, a bit line 204, a word line 205, and a source line 207.

Please refer to the second diagram (b), which is a waveform diagram of the gate voltage under bipolar operation. The horizontal axis represents time in nanoseconds and the vertical axis represents voltage in volts. The waveform WF3 in the second diagram (b) represents the waveform of the gate voltage _Vg3 applied to the transistor 203, and the gate voltage _Vg3 is equal to the voltage V _WL3 applied to the word line 205. The memory cell 201 in the second diagram (a) is subjected to a third bias operation of the addressing circuit 202, which can cause the memory cell 201 to be programmed into a high resistance state. The third biasing operation includes applying voltage V _BL2 =0 volts to bit line 204, applying voltage V _WL3 to word line 205, applying voltage Vsub=0 volts to substrate B of transistor 203, and applying voltage V _{SL2 .} = 4 volts on source line 207.

In the second diagram (b), the rising period, the wave width, and the falling period of the waveform WF3 are 100 nanoseconds, 400 nanoseconds, and 2000 nanoseconds, respectively, when the voltage V _WL3 rises from 0 volts during the rise of 100 nanoseconds. After rising to 3.8 volts, the voltage V _{WL3 is} maintained at 400 _ns at 3.8 volts, at which time the current I3 through the memory cell 201 is 400 microamperes (as shown in the second diagram (a)), and then the voltage V _{WL2 is} at 2000 nanoseconds. The falling period drops from 3.8 volts to 0 volts. In the third biasing operation, an electrically insulating substance (not shown) in the memory material 2013 is separated therefrom, resulting in a high resistance state of the memory material 2013.

Please refer to the second figure (c), which is a schematic diagram of a conventional memory cell and a bipolar addressing circuit. The difference between the bipolar addressing circuit 212 in the second diagram (c) and the bipolar addressing circuit 202 in the second diagram (a) is that the voltage V _WL3 applied to the word line 205 is applied to the bit line. the voltage V _BL3 204 = 4 volts, and the source line voltage applied to the _SL3 = 0 V 207 volts.

Please refer to the second diagram (d), which is a waveform diagram of the gate voltage under bipolar operation. The horizontal axis represents time in nanoseconds and the vertical axis represents voltage in volts. The waveform WF4 in the second diagram (d) represents the waveform of the gate voltage V _g4 applied to the transistor 203, and the gate voltage V _g4 is equal to the voltage V _WL4 applied to the word line 205. The memory cell 201 in the second diagram (d) is subjected to a fourth bias operation of the bipolar addressing circuit 212, which erases the memory cell 201 to a low resistance state. The fourth biasing operation includes applying a voltage V _BL3 = 4 volts to the bit line 204, applying a voltage V _WL4 to the word line 205, applying a voltage Vsub = 0 volt to the substrate B of the transistor 203, and applying a voltage V _SL3 =0 volts on source line 207.

In the second diagram (d), the rising period, the wave width, and the falling period of the waveform WF4 are 100 nanoseconds, 400 nanoseconds, and 2000 nanoseconds, respectively, when the voltage V _WL4 rises from 0 volts during the rise of 100 nanoseconds. After rising to 1.2 volts, the voltage V _{WL4 is} maintained at 400 _ns at 1.2 volts, at which time the current through the memory cell 201 is I4 = 350 microamps (as shown in Figure 2 (c)), and then the voltage V _{WL4 is} at 2000 nanoseconds. The falling period drops from 1.2 volts to 0 volts. Since the fourth biasing operation and the third biasing operation are mutually opposite in voltage polarity, at least a portion (not shown) of the electrically insulating material in the memory material 2013 is incorporated therein, resulting in a low memory material 2013. Resistance state.

Although the memory cell 201 under bipolar operation is less susceptible to temperature and the data is erased, the memory cell array formed by the memory cell 201 operating in the bipolar mode has a larger size, and in this mode The lower bias circuit is also more complicated and the operation speed is poor. Therefore, it is an important subject to make the memory cell array have both the advantages of unipolar operation and bipolar operation.

In view of the above disadvantages of the memory array under monopolar operation and the disadvantages of the memory array under bipolar operation, a memory array device is proposed which uses memory cells having the same structure, the only difference being that different The bias circuit is designed to be biased to the memory array without additional cost from a process point of view, and has a small size, high memory capacity, high speed operation, high temperature resistance, High overwrites and highly reliable data retention.

In accordance with the above concept, a memory array device is proposed, the memory array device including a memory array, a first circuit, and a second circuit. The memory array includes a first portion and a second portion, the first portion including a plurality of first memory cells, and the second portion includes a plurality of second memory cells. The first circuit is electrically connected to the memory array for operating the first portion in a first mode. The second circuit is electrically connected to the memory array for operating the second portion in a second mode, the first mode being a bipolar mode of operation and the second mode being a unipolar mode of operation.

According to the above concept, another memory array device is proposed. The memory array device includes a memory array having a plurality of memory cells, the plurality of memory cells operating in a first mode and a second mode, respectively.

In accordance with the above concept, another memory array device is proposed. The memory array device includes a memory array including a first portion and a second portion. The first subsection operates in a first mode of operation and the second subsection operates in a second mode of operation.

In accordance with the above concept, a method of operating a memory array device is disclosed. The memory array device includes a first portion and a second portion. The method includes the steps of applying a bipolar mode of operation to the first portion. unit. A unipolar mode of operation is applied to the second portion.

In accordance with the above concept, another method of operating a memory array device is presented, the method comprising the steps of: in a trusted manner, a user may select to store data in the first portion or the second portion, the method comprising The following steps: applying a bipolar mode of operation to the first segment. A unipolar mode of operation is applied to the second portion.

According to the above concept, another method of operating a memory array device is proposed, the method comprising the steps of: distinguishing a memory array from a first type of memory cell and a second type of memory cell. In a trusted manner, a data is stored in the first type of memory cell, and when the second type of memory cell requires the data, the data is provided from the first type of memory cell to the second type of memory cell.

According to the above concept, another method of operating a memory array device is proposed, the method comprising the steps of: distinguishing a memory array into a first type of memory cell and a second type of memory cell, in a trusted manner, The first type of memory cell stores a data, and when the second type of memory cell loses the data, the data is obtained from the first type of memory cell.

In order to be able to clearly and briefly illustrate the invention, the preferred embodiments are provided in the following embodiments, but are not limited thereto.

Please refer to the third figure (a), which is a schematic diagram of the memory array device 30 of the preferred embodiment of the present invention. The memory array device 30 includes a memory array 36, a first circuit, and a second circuit. The memory array 36 includes a first portion 361 and a second portion 362. In the third diagram (a), the first circuit and the second circuit are a bipolar bias circuit 32 and a unipolar bias circuit 34, respectively. The first circuit is electrically coupled to the memory array 36 for operating the memory array 36 in a first mode. The second circuit is electrically coupled to the memory array 36 for operating the memory array 36 in a second mode.

Please refer to the third figure (b), which is a circuit diagram of the first branch 361 operating in the first mode. In the third diagram (a), the circuit 37 in which the first subsection 361 operates in the first mode includes a control logic 31, a bipolar bias circuit 32, and a first subsection 361. In the third diagram (b), the bipolar bias circuit 32 includes a bit line decoder 311, a word line decoder and driver 312, and a source line control unit 313. The first subsection 361 includes a plurality of memory cells: a memory cell 3611, a memory cell 3612, a memory cell 3613, a memory cell 3614, a transistor 320, a transistor 322, a transistor 324, a transistor 326, a bit line 321, and a bit line. 323, word line 325, word line 327, and source line 328, 329. Each of the memory cells of the first subsection 361 is one-time programmable or multi-programmable.

The bipolar bias circuit 32 in the third diagram (b) can perform programmatic or erase control for different memory cells in the first subsection 361, for example, for a first time period. The cell 3611 is programmed using the third biasing operation, and the source line control unit 313 decodes to the source line 328 and provides 4 volts to the source line 328, the bit line decoder 311 decodes to the bit line 321 and provides 0 volts on bit line 321 and word line decoder and driver 312 are decoded to word line 325 and provide gate voltage _Vg3 . The memory cell 3613 is erased by the fourth bias operation during a second time period, and the source line control unit 313 decodes to the source line 328 and provides 0 volts to the source line 328 and the bit line decoder 311. Decode to bit line 321 and provide 4 volts to bit line 321, and word line decoder and driver 312 decode to word line 327 and provide gate voltage _Vg4 , and so on.

It is worth noting that the design of the bipolar bias circuit 32 is in response to the design of the bipolar mode of operation (ie, the first mode), and the source lines 328, 329 must be separately connected to the source line control unit 313, thus being designed It is more complicated and takes up a larger area. However, this bipolar operation is highly reliable for data storage and is not affected by temperature and causes data loss.

Please refer to the third figure (c), which is a circuit diagram of the second branch 362 operating in the second mode. In the third diagram (c), the circuit 38 operating in the second mode by the second subsection 362 includes control logic 31, a unipolar bias circuit 34, and a second subsection 362. In the third diagram (c), the unipolar bias circuit 34 includes a bit line decoder 311, a word line decoder and driver 312, and a source line control unit 313. The second subsection 362 includes a plurality of memory cells: a memory cell 3621, a memory cell 3622, a memory cell 3623, a memory cell 3624, a transistor 340, a transistor 342, a transistor 344, a transistor 346, a bit line 341, and a bit line. 343, word line 345, word line 347, and source line 348. Each of the memory cells of the second subsection 362 is multi-programmable.

The unipolar bias circuit 34 in the third diagram (c) can perform programmatic or erase control for different memory cells in the second portion 362, for example, for a third period of time. The cell 3621 is programmed using the first biasing operation, the source line 348 is grounded, the bit line decoder 311 is decoded to the bit line 341 and provides 4 volts to the bit line 341, and the word line decoder and driver 312 decodes to word line 345 and provides a gate voltage _Vg1 . The memory cell 3623 is erased by the second biasing operation during a fourth period, the source line 348 is grounded, the bit line decoder 311 is decoded to the bit line 341 and 4 volts is provided to the bit line 341, And the word line decoder and driver 312 decodes to word line 347 and provides gate voltage _Vg2 , and so on. It should be noted that the design of the unipolar bias circuit 34 is designed according to the unipolar operation mode (ie, the second mode), and the source lines 348 can be connected together, so the design is relatively simple and occupies The area is also relatively small, and it is faster in operation and lower in manufacturing cost.

The memory cells in the first sub-section 361 and the second sub-section 362 of the present invention all have the same memory cell structure and have the same material, the main difference being the bipolar bias circuit 32 and the unipolar bias. The difference in circuit 34 and the design of the array circuit (source line) in the first sub-section 361 and the second sub-section 362 are different, so there is no additional cost and engineering from a process point of view. It can be designed such that the first subsection 361 occupies a small portion of all memory cells, for example 2%, while the second subsection 362 occupies a majority of all memory cells, for example 98%, such a design can be smaller ( Or volume) to get a larger memory capacity, but can also be any proportional relationship, depending on the needs of the user.

In application, for example, in the process of mass production, important data (such as boot code) may be first burned into the first portion 361 of the memory array device 30 proposed in the present case, and then the memory array device 30 is soldered. Or writing on the circuit board, and then in the initial stage after the memory array device 30 is powered on, the important data is decompressed from the first subsection 361 or loaded into the second subsection 362 for subsequent use. Direct execution. When important data is decompressed to the second branch 362, the decompressed important data is verified, depending on the needs of the user. Of course, the user can also write the data into the second branch 362, which is also determined according to the needs of the user.

Since the high temperature generated during soldering does not affect the memory cells in the first subsection 361 and the data is lost, the memory array device 30 has a reliable data storage capability. Since the data stored in the second branch 362 after booting can be used for direct execution, the memory array device 30 has advantages such as high speed operation and low manufacturing cost.

The above important information includes plural keys, which are specific data, complex direct executable code, complex compressed code with complex self-decompressed code, or any combination thereof.

Please refer to the fourth figure, which is a flowchart of the operation method of the memory array device 30 of the present invention. The memory array device 30 includes a first sub-section 361 and a second sub-section 362, the method comprising the steps of: applying a bipolar operation to the first sub-section 361 (step S401); and applying a unipolar operation to the The binary portion 362 (step S402). Prior to soldering the memory array device 30 to the circuit board, the first segment 361 is operated by applying a bipolar to cause the data to be first stored in the first portion 361 in a reliable manner. Then, after the welding is completed, the data is loaded from the first portion 361 to the second portion 362 by applying a unipolar operation to the second portion 362 during the first power-on.

Please refer to FIG. 5, which is a flowchart of a method for operating the memory array device 30 according to another embodiment of the present invention. The method includes the following steps: distinguishing a memory array into a first memory cell and a second memory cell. (Step S501); and storing, in a trustworthy manner, a data in the first type of memory cell, and when the second type of memory cell requires the data, providing the data from the first type of memory cell to the second A memory cell (step S502).

Please refer to FIG. 6 , which is a flowchart of a method for operating the memory array device 30 according to another embodiment of the present invention. The method includes the following steps: distinguishing a memory array into a first memory cell and a second memory cell (Step S601); and storing a data in the first type of memory cell in a reliable manner, and when the second type of memory cell loses the data, acquiring the data from the first type of memory cell (step S602) .

In the above, the description and the embodiments of the present invention have been disclosed, and are not intended to limit the present invention, and those skilled in the art can make various changes without departing from the spirit and scope of the present invention. And modifications, which still fall within the scope of the present invention.

10,11. . . Conventional memory cell and unipolar bias circuit

101,201. . . Memory cell

1011. . . First electrode

1012. . . Second electrode

1013, 2013. . . Memory material

102,112. . . Unipolar addressing circuit

103,203. . . Transistor

104,204. . . Bit line

105,205. . . Word line

107,207. . . Source line

20. . . Conventional memory cell and bipolar bias circuit

2011. . . Third electrode

2012. . . Fourth electrode

202,212. . . Bipolar addressing circuit

30. . . Memory array device

31. . . Control logic

32. . . Bipolar bias circuit

34. . . Monopolar bias circuit

36. . . Memory array

361. . . First division

362. . . Second division

37. . . The first branch operates on the circuit in the first mode

38. . . The second branch operates on the circuit in the second mode

3611, 3612, 3613, 3614, 3621, 3622, 3623, 3624. . . Memory cell

321,323,341,343. . . Bit line

325,327,345,347. . . Word line

320,322,324,326,340,342,311. . . Bit line decoder

344,346. . . Transistor

312. . . Word line decoder and driver

313. . . Source line control unit

Figure (a): Schematic diagram of a conventional memory cell and a unipolar addressing circuit;

Figure (b): Waveform diagram of the gate voltage under unipolar operation;

Figure (c): Schematic diagram of a conventional memory cell and a unipolar addressing circuit;

Figure (d): Waveform diagram of the gate voltage under unipolar operation;

Figure 2 (a): Schematic diagram of a conventional memory cell and a bipolar addressing circuit;

Figure 2 (b): Waveform diagram of the gate voltage under bipolar operation;

Figure 2 (c): Schematic diagram of a conventional memory cell and bipolar addressing circuit;

Figure 2 (d): Waveform diagram of the gate voltage under bipolar operation;

Figure 3 (a) is a schematic view of a memory array device of the preferred embodiment of the present invention;

The third figure (b): the circuit diagram of the first part of the case operating in the first mode;

The third figure (c): the circuit diagram of the second part of the case operating in the second mode;

Fourth figure: a flow chart of the operation method of the memory array device of the present invention;

Figure 5 is a flow chart showing a method of operating a memory array device of another embodiment of the present invention;

Figure 6 is a flow chart showing the operation method of the memory array device of another embodiment of the present invention.

30. . . Memory array device

31. . . Control logic

32. . . Bipolar bias circuit

34. . . Monopolar bias circuit

36. . . Memory array

361. . . First division

362. . . Second division

37. . . The first branch operates on the circuit in the first mode

38. . . The second branch operates on the circuit in the second mode

Claims (9)

A memory array device includes: a memory array comprising a first portion and a second portion, the first portion comprising a plurality of first memory cells, the second portion comprising a plurality of second memory cells, wherein Each of the memory cells includes a first electrode, a second electrode, and a memory material between the first electrode and the second electrode; a first circuit electrically connected to the memory array for enabling the first a sub-portion operating in a bipolar mode of operation; and a second circuit electrically coupled to the memory array for operating the second sub-portion in a unipolar mode of operation, wherein the first segment is for storing a first data, the first data comprising a plurality of key codes, the key data being a specific data, a plurality of direct executable code, a complex compressed code having a plurality of self-decompressing codes, or any combination thereof in the memory array During the initial phase after the device is powered up, the compressed code is decompressed from the first portion to the second portion for subsequent direct execution. The device of claim 1, wherein: when the compressed code is decompressed to the second portion, the decompressed code is verified. The device of claim 1, wherein: the first circuit applies a first bias to the first portion, and the second circuit applies a second bias to the second portion. A data access is performed between the first branch and the second branch. The device of claim 1, wherein: the first memory cell is in the bipolar mode of operation, when the memory material of the first memory cell forms an electrically insulating layer, the first memory cell The memory material is in a high resistance state, when at least a portion of the electrically insulating layer is recombined to the memory material, the memory material of the first memory cell is in a low resistance state; and the second memory cell is in the unipolar mode of operation When the memory material of the second memory cell forms an amorphous phase, the memory material of the second memory cell is in a high resistance state, and when the memory material forms a crystalline phase, the memory material of the second memory cell is Low resistance state. The device of claim 1, wherein the first portion comprises a plurality of first source lines each connected to a transistor corresponding to the plurality of first memory cells, the plurality of first source lines respectively Separating; and the second portion includes a plurality of second source lines each connected to a transistor corresponding to the plurality of second memory cells, the plurality of second source lines being connectable to each other. A method of operating a memory array device, the memory array device comprising a first portion and a second portion, the first portion comprising a plurality of first memory cells, the second portion comprising a plurality of second memory cells The method includes the steps of: applying a bipolar mode of operation to the first segment to program or erase the first memory cells; and applying a unipolar mode of operation to the second segment to programmatically Or erasing the second memory cells, wherein the first segment is used to store a first data, the first resource The material includes a plurality of key codes, which are specific data, a plurality of direct executable code, a complex compressed code having a plurality of self-decompressing codes, or any combination thereof, in an initial stage after the memory array device is powered on The compressed code is decompressed from the first portion to the second portion for subsequent direct execution. The method of claim 6, further comprising the step of: applying a first bias voltage to the first portion during a first period of time to cause electrical insulating substances in the first memory cells to Separating the memory material in the first memory cells; applying a second bias to the first portion during a second period of time to incorporate at least a portion of the electrically insulating material in the first memory cells And a first memory cell in the memory material; applying a third bias voltage to the second portion during a third period of time, so that the memory material in the second memory cell forms a high resistance state of the amorphous phase; And applying a fourth bias voltage to the second portion during a fourth period to cause the memory material in the second memory cells to form a low resistance state of the crystalline phase. The method of claim 7, wherein the first sub-section comprises a first transistor, a first bit line, a first word line, and a first source line, the method further comprises The following steps: applying the first bias to the first portion, the applying the first biasing operation: applying a first voltage to the first bit line, applying a second voltage to the first a word line, applying the first voltage to a substrate of the first transistor, And applying a third voltage to the first source line; and applying the second bias to the first portion, the applying the second biasing operation: applying the third voltage to the first bit a line, applying a fourth voltage to the first word line, applying the first voltage to a base of the first transistor, and applying the first voltage to the first source line. The method of claim 7, wherein the second portion further comprises a second transistor, a second bit line, a second word line, a second source line, and other sources. The method further includes the steps of: applying the third bias to the second portion, the applying the third biasing operation: applying a first voltage to the second bit line, applying a first Two voltages on the second word line, applying a third voltage to the base of the second transistor, and applying the third voltage to the second source line; and applying the fourth bias to operate on the second a portion, the applying the fourth biasing operation includes: applying the first voltage to the second bit line, applying a fourth voltage to the second word line, and applying the third voltage to the second a substrate of the crystal, and applying the third voltage to the second source line.