201244027 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路板製造技術，且特別是有關 於一種線路板製造方法及線路板。 【先前技術】 近年來’全球環保意識提升，各電子大廠皆致力於具 有壤保概念的產品開發。以㈣產纽投影機產業為例， 具有節能省電特性之發光二極體燈具及以發光二極體為光 源之投影機儼然已成為各廠商開發的重點。 在照明裳置及投影機中通常會採用發光二極體（light =in“iode，LED)作為其光源。為了提供散熱用來 承ft光其他高熱轉電子讀之祕板大多採 ^ i H 言’在金屬基板上形成介電層及導電 曰以後’將導電層圖案化以形成線路層。接著，將發光二 極體晶片„金屬基板上且電性連接至線路層。 +，π 主思的疋，在圖案化導電層以形成線路層的過程 了槪濕製程’例如顯影、1虫刻及清洗等。因此，為 牵化_屬基板之背面（即相對於導電層的那—面）於圖 1 C過程中受損’會在金屬基板之背面壓合保護 增树路板的ί==壓合上一層保護膜的製程會 【發明内容】 201244027 本發明提供一種線路板製造方法，可製作出線路板。 本舍明k供一種基層線路板，尤其是一種低製作成本 的線路板。 ^本發明提供一種線路板製造方法，其包括下列步驟。 提供兩基板。藉由膠層黏合兩基板，膠層位於兩基板的周 邊以與兩基板形成封閉空間。在藉由膠層黏合兩基板以 後，形成多個定位孔。這些定位孔穿過兩基板及膠層，且 膠體包圍這些定位孔。在藉由膠層黏合兩基板以後，在各 基板上形成線路疊構。在形成兩線路疊構以後，分離兩基 板’使得這些線路疊構分別位於這些基板上。 本發明提供一種基層線路板’其包括兩基板、膠層以 及多個定位孔。膠層黏合兩基板，且位於兩基板的周邊， 以與兩基板黏合後形賴閉空間。S個定位孔穿過兩基板 及膠層，且膠體包圍定位孔。 基於上述，本發明之線路板製造方法是在以膠層黏合 兩基板後’在兩基板上形成兩線路疊構，使得兩線路疊構 =少一部分製程可—併進行。因此，各線路板所需的製 作時間及成本便可有效地減少。 此外本發明之線路板包括以膠層黏合之兩金屬基 巧’且欲製作在兩金屬基板上之線路疊構的至少—部分製 ^可併如了。因此’湘本發明可製作&低成本之 板。 為讓本發明之上述特徵和優點能更 舉實施例，並配合所附圖式作詳細說明如下。 4 201244027 【實施方式】 圖1A至圖1G為本發明一實施例之線路板製造方法 之剖面示意圖。請參照圖1A，首先，提供兩基板120。在 本實施例中，各基板120上可先配置有一介電層132以及 一位於介電層132上的導電層134。 為了提供較佳的散熱效果至所承載的高熱功率電子 元件（例如發光二極體），基板120之材質包括導熱材質， 例如金屬、陶瓷或含有導體填充物的樹脂，其中導體填充 物具有可導電性質或可導熱性質，或同時具有可導電及可 導熱的性質。 在另一未繪示實施例中，當基板120之材質包括導熱 絕緣材質（例如陶瓷或含有導體填充物的樹脂）時，可省 略介電層132而將導電層134直接配置在基板120上。 請參照圖1B，接著，藉由膠層110黏合兩基板120。 詳言之，可先將膠層110塗佈於其中一基板120上，再將 另一基板120壓合於已塗佈膠層110之基板120上，而使 兩基板120黏合在一起。 在本實施例中，膠層110係位於兩基板120的周邊， 以與兩基板120形成封閉空間R。舉例而言，膠層110可 呈框形圖案，此框形圖案與兩基板120之背面120a圍出扁 平狀的封閉空間R。如此一來，在後續的濕製程（例如顯 影、蝕刻、清洗等）中，外物（例如顯影液、蝕刻液、清 洗劑等）便不易穿過膠層110進入封閉空間R，進而對基 板120之背面i2〇a造成損傷。 201244027 此外f層110之寬度w (如圖1B)可依實際的需 纽調整。舉勤言，膠層110之K度W可介於i董米 科^^至30、髮米（mm)之間。膠層u〇之材質包括環氧 树月曰㈣Gxy)、料子料物⑽yme0或防焊材料。 清參照圖ic，在藉由膠層110黏合兩基板120以後， :選，地形成多個定位孔（t〇〇lmg h，定位孔h ! = ί板12G及膠層UG。藉由本實施例之定位孔Η可 :動本貫^列之線路板進行相關製程。值得一提的是，本 =施例之疋位孔Η並未破壞封閉空間R的封雜 例之定位孔H被膠體11〇所包圍。 貝 請參照圖1D，在藉由膠層11〇黏合兩基板12〇以後， 在各基板120上形成線路疊才冓13〇。詳言之，如圖ic及圖 1D所示，在本實_中，细彡成線路4構m的步驟中， 可對已配置在基板12G上的導電層134 (如圖lc)進行圖 案化製程’以使兩導電層134分卿成兩線路層l34a (如201244027 VI. Description of the Invention: [Technical Field] The present invention relates to a circuit board manufacturing technique, and more particularly to a circuit board manufacturing method and a circuit board. [Prior Art] In recent years, the global environmental awareness has increased, and all major electronics companies are committed to product development with the concept of a green insurance. Taking (4) the New Projector industry as an example, a light-emitting diode lamp with energy-saving and power-saving characteristics and a projector with a light-emitting diode as a light source have become the focus of development of various manufacturers. Light-emitting diodes (light = in "iode", LED) are usually used as the light source in lighting and projectors. In order to provide heat dissipation, other high-heat electronic reading boards are used for ft. After the dielectric layer and the conductive germanium are formed on the metal substrate, the conductive layer is patterned to form a wiring layer. Next, the light-emitting diode wafer is electrically connected to the wiring layer. +, π Thoughts of the process, in the process of patterning the conductive layer to form the wiring layer, the process of dampness, such as development, insect engraving and cleaning. Therefore, the back side of the substrate (ie, the surface opposite to the conductive layer) is damaged in the process of FIG. 1C, and the pressure is applied to the back surface of the metal substrate to protect the tree plate. Process for forming a protective film [Invention] 201244027 The present invention provides a method for manufacturing a circuit board, which can produce a circuit board. Ben Sheming k is used for a base layer circuit board, especially a low production cost circuit board. The present invention provides a method of manufacturing a wiring board comprising the following steps. Two substrates are provided. The two substrates are bonded by a glue layer, and the glue layer is located around the two substrates to form a closed space with the two substrates. After the two substrates are bonded by the adhesive layer, a plurality of positioning holes are formed. These positioning holes pass through the two substrates and the glue layer, and the colloid surrounds the positioning holes. After the two substrates are bonded by the adhesive layer, a line stack is formed on each of the substrates. After forming the two-wire stack, the two substrates are separated such that the wiring stacks are respectively located on the substrates. The present invention provides a base layer circuit board which includes two substrates, a glue layer, and a plurality of positioning holes. The adhesive layer is bonded to the two substrates, and is located at the periphery of the two substrates, and is bonded to the two substrates to form a closed space. S positioning holes pass through the two substrates and the glue layer, and the colloid surrounds the positioning holes. Based on the above, the circuit board manufacturing method of the present invention is to form a two-circuit stack on the two substrates after bonding the two substrates with the adhesive layer, so that the two-circuit stack = a part of the process can be performed. Therefore, the manufacturing time and cost required for each board can be effectively reduced. Further, the circuit board of the present invention comprises two metal substrates bonded by a glue layer and at least a part of the circuit stack to be formed on the two metal substrates can be combined. Therefore, the invention of Hunan can produce & low cost boards. The above described features and advantages of the present invention will be described in more detail with reference to the accompanying drawings. 4 201244027 [Embodiment] Figs. 1A to 1G are schematic cross-sectional views showing a method of manufacturing a wiring board according to an embodiment of the present invention. Referring to FIG. 1A, first, two substrates 120 are provided. In this embodiment, a dielectric layer 132 and a conductive layer 134 on the dielectric layer 132 may be disposed on each of the substrates 120. In order to provide a better heat dissipation effect to the carried high-power electronic components (such as light-emitting diodes), the material of the substrate 120 includes a heat-conducting material such as metal, ceramic or a resin containing a conductor filler, wherein the conductor filler has electrical conductivity. Properties or thermally conductive properties, or both electrically and thermally conductive. In another embodiment, when the material of the substrate 120 includes a thermally conductive insulating material (for example, ceramic or a resin containing a conductor filler), the dielectric layer 132 may be omitted and the conductive layer 134 may be directly disposed on the substrate 120. Referring to FIG. 1B, the two substrates 120 are bonded by the adhesive layer 110. In detail, the adhesive layer 110 may be first coated on one of the substrates 120, and the other substrate 120 may be pressed onto the substrate 120 of the coated adhesive layer 110 to bond the two substrates 120 together. In this embodiment, the glue layer 110 is located at the periphery of the two substrates 120 to form a closed space R with the two substrates 120. For example, the glue layer 110 may have a frame-shaped pattern, and the frame pattern and the back surface 120a of the two substrates 120 enclose a flat closed space R. As a result, in a subsequent wet process (such as development, etching, cleaning, etc.), foreign objects (such as developer, etching solution, cleaning agent, etc.) are less likely to pass through the adhesive layer 110 into the closed space R, and thus to the substrate 120. The back i2〇a causes damage. 201244027 In addition, the width w of the f layer 110 (as shown in Fig. 1B) can be adjusted according to the actual needs. As a matter of fact, the K degree W of the glue layer 110 can be between i Dongmi, ^^ to 30, and hair (mm). The material of the adhesive layer includes the epoxy tree (4) Gxy), the material (10) yme0 or the solder resist material. Referring to FIG. ic, after the two substrates 120 are bonded by the adhesive layer 110, a plurality of positioning holes (t〇〇lmg h, positioning holes h! = 板 plate 12G and glue layer UG) are formed. The positioning hole can be: the circuit board of the basic column is subjected to the relevant process. It is worth mentioning that the positioning hole H of the sealing example of the sealing space R of the present embodiment is not destroyed by the colloid 11 Referring to FIG. 1D, after the two substrates 12 are bonded by the adhesive layer 11 , a line stack is formed on each of the substrates 120. In detail, as shown in FIG. 1 and FIG. In the step of finely forming the circuit 4, the conductive layer 134 (such as lc) disposed on the substrate 12G may be patterned to make the two conductive layers 134 separate into two lines. Layer l34a (eg
實施例中，介電層132之材質可採用樹脂材 枓’而導電層m之材質可採用銅,、銅合金、銘 但不以此為限。 I 舉例而言’在圖案化導電層134以形成線路層134a 的步驟+’可先㈣導電層134上職全面性的兩光 質的乾膜。接著’制恤乾驗㈣光、顯f彡而 光阻圖案。之後，以兩光阻圖案為蝕刻罩幕，蝕刻移陕夫 被兩光阻圖案所覆蓋的部分兩導電層134，而形成兩ς 層134a。最後，移除兩光阻乾膜而暴露出線路層13知。 201244027 值得一提的是’在本實施例中，兩基板12〇之背面12〇a 係與膠層110形成封閉空間R。於形成線路疊構13〇的過 程中，各種外物（例如顯影液、蝕刻液或清洗劑等）便不 易穿過膠層11G進人封閉空間R，進而對基板12G之背面 120a造成損傷。因此，在本實施例中，各基板12〇之背面 論不必如習知技術般需壓合上保護膜來保護基板12〇之 背面12Ga。如此-來’本實施例之線路板製造過程中所需 使用之耗材（如倾膜）成本便可減少，進崎低施 例之線路板的製造成本。 此外，在本實施例中，在將兩基板以膠層黏合後，才 進打兩基板120上之線路疊構13〇的製作。因此，兩基板 U0上之線路疊構13〇的部份製程（如顯影、钱刻 同時進行。因此，可縮短單—線路疊構13G的製 進而減少線路板的製作時間與成本。 =1Ε所示，本實_之形成線路疊構⑽的步驟 形成兩防焊層136，其中這兩防焊層136分 別後蓋兩線路層134a的局部與兩介電層132 可避免焊料誤焊於祕層ma ±岭成短^ ~曰 如圖1F所示，本實施例之形成線路 可進-步包括形成兩保護層138，其 ：3:的步驟 別覆蓋兩線路層134a被防焊層136 θ Π8分 被防焊㈣6所暴露出的部分U=4:=r以， 本實施例中，保護請例如為銀=34a不人易破氧化。在 0層_金複合層μ销有機保_，但本發明不以 201244027 此為限。 請參照圖1G，在形成線路疊構13〇卩後分離兩基 板120,於此便完成了本實施例之兩線路板1〇〇。分離兩基 板120的方式有許多種。舉例而言，在本實施例中，可將 膠層110及部分與膠層110重疊之線路疊構13〇及基板12〇 切除，而使兩線路板1〇〇分離。 需特別說明的是，本發明並不限於圖1(3所示之線路 疊構130。在另一實施例中，如圖2所示，各線路疊構13〇, 可包括多個介電層132、132，、多個線路層134a、134a，以 及至少一導電孔135。線路層134a ' 134a，與介電層132、 132父互疊合於對應的基板120上。導電孔135穿過介電 層132以連接二線路層134a、134a’。各線路疊構130,亦 可進一步包括防焊層136以及保護層138。防焊層136分 別覆蓋最外層的線路層134a，的局部與最外層的介電層 132’。保護層138分別覆蓋最外層的線路層n4a，被防焊層 136所暴露出的部分。 請同時參照圖1D與圖2 ’更詳細地說，在另一實施 例中，可於完成如圖1D所示之線路疊構13〇 (即一層介電 層132與—層線路層134a)後，於線路層134a上再形成 介電層132,（繪於圖2)。之後，於介電層132，上形成線 路層134a，及導電孔135 (繪於圖2)，其中線路層n4a， 透過導電孔135而與線路層134a電性連接。然後，形成防 焊層136’防焊層136分別覆蓋最外層的線路層134a，的局 部與最外層的介電層132,。最後，形成保護層138以分別 8 201244027 覆蓋最外層的線路層134a’被防焊層136所暴露出的部分。 請參考圖3，在又一實施例中，相似於圖2之線路疊 構130’，各線路疊構130”可包括多個介電層132、132，、 多個線路層134a、134a’以及至少一導電孔135。這些線路 層134a、134a’與這些介電層132、132,交互疊合於對應的 基板120上。導電孔135穿過介電層132以連接二線路層 134a、134a’。此外，各線路疊構130”更可包括防焊層136 以及保護層138。防焊層136分別覆蓋最外層的線路層 134a’的局部與最外層的介電層132，。保護層138分別覆蓋 最外層的線路層134a’被防焊層136所暴露出的部分。 然而，不同於圖2之線路疊構130,，各線路疊構13〇，， 更可包括至少一導電孔135,。導電孔135,穿過這些介電層 132、132以連接線路層134a’與基板120。此外，各線路 疊構130”更可包括至少一導電孔135”。導電孔135，，穿過 介電層132以連接線路層134a與基板120。 圖1B同時繪示了本發明一實施例之基層線路板。請 參考圖1B，本實施例之線路板半成品1〇〇，包括兩基板12〇 (例如為金屬基板）以及一膠層110。膠層11〇黏合兩基 板120，且位於兩基板120的周邊，以與兩基板12〇形成 封閉空間R。本實施例之基層線路板1〇〇,可進一步包括兩 介電層132及兩導電層134。兩介電層134分別配置在兩 基板120上。兩導電層134分別配置在介電層132上。藉 由本貫施例之基層線路板100’可以較短的製程時間及成本 來製造出較多的線路板。 201244027 综上所述，本發明之線路板製造方法是在以膠層黏舍 兩基板後，在兩基板上形成兩線路疊構，使得兩線路疊構 的至少一部分製程可一併進行。因此，各線路板所需的製 作時間及成本便可有效地減少。 此外，在本發明之線路板製造方法中，兩基板係與膠 層形成封閉空間。因此，於形成線路疊構的過程中，各穆 外物便不易穿過膠層進入封閉空間，進而對基板的背面造 成損傷。從而，各基板之背面不必如習知技術般需壓合上 保遵膜來保護基板的背面。如此—來，在習知線路板製造 過程中所需使用之耗材（如保護膜）成本便可減少，進而 降低線路板的製造成本。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，故本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖1G為本發明一實施例之線路板製造方法 的剖面示意圖。 圖2為本發明另一實施例之線路板的剖面示意圖。 圖3為本發明又一實施例之線路板的剖面示=圖。 201244027 【主要元件符號說明】 100 :線路板 100’ ：基層線路板 110 :膠層 120 :基板 120a :基板背面 130、130’、130” ：線路疊構 132、132’ ：介電層 134 :導電層 135、135’、135” ：導電孔 134a、134a’ ：線路層 136 :防焊層 138 :保護層 R :封閉空間 Η :定位孔In the embodiment, the material of the dielectric layer 132 may be made of a resin material 枓', and the material of the conductive layer m may be copper, copper alloy, but not limited thereto. For example, the step of patterning the conductive layer 134 to form the wiring layer 134a can be preceded by the (four) conductive layer 134 having a comprehensive two-quality dry film. Then, the t-shirt is dry (four) light, and the light pattern is visible. Thereafter, the two photoresist patterns are used as an etch mask to etch a portion of the two conductive layers 134 covered by the two photoresist patterns to form two germanium layers 134a. Finally, the two photoresist dry films are removed to expose the wiring layer 13. 201244027 It is worth mentioning that in the present embodiment, the back surface 12〇a of the two substrates 12〇 forms a closed space R with the glue layer 110. During the formation of the wiring stack 13 各种, various foreign matters (e.g., developer, etching solution, cleaning agent, etc.) are less likely to enter the closed space R through the adhesive layer 11G, thereby causing damage to the back surface 120a of the substrate 12G. Therefore, in the present embodiment, the back surface of each of the substrates 12 is not required to be pressed against the protective film to protect the back surface 12Ga of the substrate 12 as in the prior art. Thus, the cost of the consumables (e.g., the pour film) required for the manufacturing process of the circuit board of the present embodiment can be reduced, and the manufacturing cost of the circuit board of the lower embodiment can be reduced. In addition, in the present embodiment, after the two substrates are bonded by the adhesive layer, the fabrication of the line stack 13 on the two substrates 120 is performed. Therefore, part of the process of the stacking of the two substrates U0 (such as development, money engraving at the same time. Therefore, the single-line stack 13G system can be shortened and the production time and cost of the circuit board can be reduced. The step of forming the circuit stack (10) forms two solder mask layers 136, wherein the two solder resist layers 136 respectively cover the portions of the two circuit layers 134a and the two dielectric layers 132 to prevent the solder from being soldered to the secret layer. As shown in FIG. 1F, the formation of the circuit of this embodiment may further include forming two protective layers 138, the step of: 3: covering the two circuit layers 134a by the solder resist layer 136 θ Π 8 The portion exposed by the solder resist (4) 6 is U=4:=r. In this embodiment, the protection is, for example, silver=34a, which is not easily broken by oxidation. In the 0 layer_gold composite layer, the pin is organically guaranteed _, but The present invention is not limited to 201244027. Referring to FIG. 1G, after the circuit stack 13 is formed, the two substrates 120 are separated, and thus the two circuit boards 1 of the present embodiment are completed. The manner of separating the two substrates 120 is completed. There are many types. For example, in this embodiment, the glue layer 110 and a portion overlapping the glue layer 110 may be The circuit stack 13 and the substrate 12 are cut away to separate the two boards. Specifically, the present invention is not limited to the line stack 130 shown in FIG. 1 (in another embodiment). As shown in FIG. 2, each of the circuit stacks 13A may include a plurality of dielectric layers 132, 132, a plurality of circuit layers 134a, 134a, and at least one conductive via 135. The circuit layer 134a '134a, and the dielectric The layers 132, 132 are superimposed on the corresponding substrate 120. The conductive holes 135 pass through the dielectric layer 132 to connect the two circuit layers 134a, 134a'. Each of the circuit structures 130 may further include a solder resist layer 136 and protection. Layer 138. The solder resist layer 136 covers the outermost outermost dielectric layer 132' of the outermost wiring layer 134a. The protective layer 138 covers the outermost wiring layer n4a, respectively, and is exposed by the solder resist layer 136. Referring to FIG. 1D and FIG. 2 simultaneously, in more detail, in another embodiment, the line stack 13A as shown in FIG. 1D (ie, a dielectric layer 132 and a layer wiring layer 134a) may be completed. Thereafter, a dielectric layer 132 is formed on the wiring layer 134a (shown in FIG. 2). Thereafter, a line is formed on the dielectric layer 132. The circuit layer 134a and the conductive hole 135 (shown in FIG. 2), wherein the circuit layer n4a is electrically connected to the circuit layer 134a through the conductive hole 135. Then, the solder resist layer 136 is formed to cover the outermost layer respectively. The portion of the wiring layer 134a, the outermost outer dielectric layer 132. Finally, the protective layer 138 is formed to cover the portion of the outermost wiring layer 134a' exposed by the solder resist layer 136, respectively, 8 201244027. Referring to FIG. 3, In yet another embodiment, similar to the line stack 130' of FIG. 2, each line stack 130" can include a plurality of dielectric layers 132, 132, a plurality of circuit layers 134a, 134a', and at least one conductive via 135. . These wiring layers 134a, 134a' are superimposed on these dielectric layers 132, 132 on the corresponding substrate 120. The conductive vias 135 pass through the dielectric layer 132 to connect the two wiring layers 134a, 134a'. In addition, each of the line stacks 130" may further include a solder resist layer 136 and a protective layer 138. The solder resist layer 136 covers the partial and outermost dielectric layers 132 of the outermost wiring layer 134a', respectively. The outermost wiring layer 134a' is exposed by the solder resist layer 136. However, unlike the wiring stack 130 of Fig. 2, each of the wiring stacks 13 is further comprised of at least one conductive via 135. The holes 135 pass through the dielectric layers 132, 132 to connect the circuit layer 134a' with the substrate 120. Further, each of the line structures 130" may further include at least one conductive hole 135". The conductive holes 135 pass through the dielectric layer. 132 is connected to the circuit layer 134a and the substrate 120. Fig. 1B also shows a base layer circuit board according to an embodiment of the present invention. Referring to FIG. 1B, the circuit board semi-finished product of the present embodiment includes one substrate 12 〇 (for example, a metal substrate) and a glue layer 110. The glue layer 11 is bonded to the two substrates 120 and located at the periphery of the two substrates 120 to form a closed space R with the two substrates 12A. The base layer circuit board of the embodiment can further The utility model comprises two dielectric layers 132 and two conductive layers 134. The layers 134 are respectively disposed on the two substrates 120. The two conductive layers 134 are respectively disposed on the dielectric layer 132. The base layer circuit board 100' of the present embodiment can manufacture more circuit boards with shorter process time and cost. In view of the above, the circuit board manufacturing method of the present invention is to form a two-circuit stack on two substrates after bonding the two substrates with a glue layer, so that at least a part of the processes of the two-circuit stack can be performed together. The manufacturing time and cost required for each circuit board can be effectively reduced. Further, in the circuit board manufacturing method of the present invention, the two substrate systems form a closed space with the adhesive layer. Therefore, in the process of forming the circuit stack, Each of the external objects is not easy to pass through the adhesive layer and enters the closed space, thereby causing damage to the back surface of the substrate. Therefore, the back surface of each substrate does not need to be pressed against the film to protect the back surface of the substrate as in the prior art. The cost of the consumables (such as protective film) required for the conventional circuit board manufacturing process can be reduced, thereby reducing the manufacturing cost of the circuit board. Although the invention has been disclosed by way of example However, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1G are schematic cross-sectional views showing a method of manufacturing a circuit board according to an embodiment of the present invention. FIG. 2 is a circuit board according to another embodiment of the present invention. Fig. 3 is a cross-sectional view of a circuit board according to still another embodiment of the present invention. 201244027 [Description of main components] 100: circuit board 100': base layer circuit board 110: glue layer 120: substrate 120a: back surface of substrate 130 130', 130': line stack 132, 132': dielectric layer 134: conductive layer 135, 135', 135": conductive holes 134a, 134a': circuit layer 136: solder resist layer 138: protective layer R: Closed space Η : positioning hole