CN107622953A - Method for manufacturing package-on-package structure - Google Patents

Abstract

A method for fabricating a package-on-package structure includes providing a first coreless package substrate, wherein one side of the first coreless package substrate has a plurality of first conductive elements and the other side of the first coreless package substrate is coupled to a carrier; then, the first coreless layer type packaging substrate is combined to a second coreless layer type packaging substrate through a first conductive element of the first coreless layer type packaging substrate, and at least one electronic element is arranged on the second coreless layer type packaging substrate; then, a package layer is formed between the first coreless package substrate and the second coreless package substrate, and the carrier is removed. By stacking two coreless packaging substrates, the thickness of the packaging stack structure is reduced.

Description

Manufacturing method of package stack structure

technical field

The invention relates to a semiconductor packaging process, in particular to a method for manufacturing a package stack structure.

Background technique

With the evolution of semiconductor packaging technology, different packaging types have been developed for semiconductor devices. In order to improve electrical functions and save packaging space, the industry has developed a stacked package structure to form a package stack structure. (Package on Package, POP) packaging type, this type of packaging can take advantage of the heterogeneous integration characteristics of the system package (SiP), and can integrate electronic components with different functions, such as: memory, central processing unit, graphics processor, Image application processors, etc., achieve system integration through stacking design, and are suitable for various thin, light, short and small electronic products.

FIG. 1 is a schematic cross-sectional view of a known package stack structure 1 . As shown in FIG. 1 , the packaging stack structure 1 includes a first semiconductor element 10 , a first packaging substrate 11 , a second packaging substrate 12 , a plurality of solder balls 13 , a second semiconductor element 14 and an encapsulant 15 . The first package substrate 11 has a core layer 110 and a plurality of circuit layers 111 , and the second package substrate 12 has a core layer 120 and a plurality of circuit layers 121 . The first semiconductor device 10 is disposed on the first packaging substrate 11 in a flip-chip manner, and the second semiconductor device 14 is also disposed on the second packaging substrate 12 in a flip-chip manner. The solder balls 13 are used to connect and electrically couple the first package substrate 11 and the second package substrate 12 . The encapsulant 15 covers the solder balls 13 and the first semiconductor device 10 . Optionally, a primer 16 is formed between the first semiconductor device 10 and the first packaging substrate 11 .

However, in the aforementioned known package stack structure 1, both the first package substrate 11 and the second package substrate 12 have core layers 110, 120, resulting in high manufacturing costs, and the thickness H of the package stack structure 1 is about 620 microns, which is inconsistent with current The demand for thinner and smaller products.

Therefore, how to overcome the problems in the known technology has become an urgent problem to be solved at present.

Contents of the invention

In view of the lack of the above-mentioned known technologies, the present invention provides a method for manufacturing a package stack structure, which reduces the thickness of the package stack structure by stacking two coreless layer package substrates.

The manufacturing method of the packaging stack structure of the present invention includes: providing a first core-less packaging substrate and a second core-free packaging substrate, wherein one side of the second core-free packaging substrate is provided with at least An electronic component; combining the first coreless packaging substrate with a plurality of first conductive elements to the second coreless packaging substrate on one side of the electronic component; and forming a packaging layer on the first between the coreless packaging substrate and the second coreless packaging substrate, so that the packaging layer covers the first conductive components and the electronic components.

In the aforementioned manufacturing method of the package stack structure, the first coreless package substrate further includes a first dielectric layer, and a substrate embedded in the first dielectric layer and electrically connected to the first conductive elements. first line layer. In addition, the first coreless packaging substrate further includes a plurality of first conductive pillars embedded in the first dielectric layer and formed on the first circuit layer, so that the first conductive elements are The first conductive column is electrically connected to the first circuit layer.

In the aforementioned manufacturing method of the package stack structure, the other side of the first coreless package substrate is combined with a carrier plate, for example, the first coreless package substrate is combined with the carrier plate through the first insulating layer. It also includes removing the carrier board after forming the encapsulation layer. After removing the carrier board, a plurality of first openings are formed on the first insulating layer.

In the aforementioned manufacturing method of the package stack structure, a primer is formed between the second coreless package substrate and the electronic component.

In the aforementioned manufacturing method of the package stack structure, the second coreless package substrate includes a circuit build-up structure, so that the first conductive element and the electronic component are electrically connected to the circuit build-up structure. For example, the second coreless package substrate further includes a plurality of second conductive elements formed on the circuit build-up structure and electrically connected to the circuit build-up structure, so that the second conductive elements are combined with the first conductive The component and the electronic component, and the encapsulation layer also covers the second conductive components. Alternatively, the second coreless package substrate further includes a second insulating layer formed on the circuit build-up structure, so that the second coreless package substrate The layered package substrate combines another carrier board with its second insulating layer, and after forming the encapsulation layer, the other carrier board is removed, so after removing the other carrier board, a plurality of second openings can be formed. The hole is on the second insulating layer.

In the aforementioned manufacturing method of the packaging stack structure, after forming the packaging layer, disposing another electronic component on the first core-less packaging substrate. For example, an encapsulation material is formed on the first coreless packaging substrate, so that the encapsulation material covers the other electronic component.

In addition, in the aforementioned manufacturing method of the package stack structure, the first conductive elements are firstly disposed on one side of the first coreless package substrate, and then the first coreless package substrate is bonded to the first coreless package substrate. Two coreless package on the substrate. Alternatively, the first conductive elements are firstly disposed on one side of the second coreless packaging substrate, and then the first coreless packaging substrate is bonded to the second coreless packaging substrate.

It can be seen from the above that the manufacturing method of the packaging stack structure of the present invention is by stacking two core-less packaging substrates without core layers, so compared with the known technology, not only can omit the material and process of the core layer to reduce the production cost cost, and can greatly reduce the thickness of the package stack structure.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a known package stack structure;

2A to 2B are cross-sectional schematic diagrams of the method for manufacturing the first core-less packaging substrate of the present invention;

Fig. 2B ' is another embodiment schematic diagram of Fig. 2B;

3A to 3C are schematic cross-sectional views of the second method of manufacturing the core-less packaging substrate of the present invention;

4A to 4C are schematic cross-sectional views of the manufacturing method of the package stack structure of the present invention;

Fig. 4A' to Fig. 4B' are the schematic diagrams of another embodiment of Fig. 4A to Fig. 4B;

Fig. 4C' is a schematic diagram of another embodiment of Fig. 4C;

5A to 5C are schematic cross-sectional views of another embodiment of the method for manufacturing the second core-less packaging substrate of the present invention; and

6A to 6C are schematic cross-sectional views of still another embodiment of the manufacturing method of the second coreless packaging substrate of the present invention.

Symbol Description

1,4,4' package stack structure 10 first semiconductor components

11 First package substrate 110,120 core layer

111,121 Circuit layer 12 Second packaging substrate

13,42 Solder balls 14 Second semiconductor component

15 Encapsulant 16 Primer

2,2’ The first coreless package substrate

20,30 Carrier plate 21,21’ First insulating layer

210 First opening 22,22’ First dielectric layer

23 The first circuit layer 24 The first conductive column

25 first conductive element

3,3’,3” second coreless package substrate

3a,5a,6a Line build-up structure 31 Second insulating layer

310 Second opening 32,52,62 Second dielectric layer

32’,52’ solder mask layer 33,53,63 second circuit layer

34,54,64 Second conductive post 35 Second conductive element

40,44 Electronic components 40a Active surface

40b Non-active side 400 Electrode pad

41 Encapsulation Layer 41’ Primer

43 Solder material 50,60 Carrier

500 release layer 501,601 metal layer

H,T thickness 45 packaging material.

detailed description

The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for the understanding and reading of those familiar with this technology, and are not used to limit the implementation of the present invention Therefore, it has no technical substantive meaning. Any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of this invention without affecting the effect and purpose of the present invention. The technical content disclosed by the invention must be within the scope covered. At the same time, terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall also be regarded as the implementable scope of the present invention without substantive change in the technical content.

2A to 2B are schematic cross-sectional views of the manufacturing method of the first coreless packaging substrate 2 of the present invention.

As shown in FIG. 2A , a first insulating layer 21 is formed on a carrier board 20 .

In this embodiment, the carrier plate 20 is a metal plate, a semiconductor wafer or a glass plate.

In addition, the material forming the first insulating layer 21 is selected from solder mask such as green paint, polyimide (PI for short), polyamide-imide (PAI for short), or polybenzimidazole (polybenzimidazole). , referred to as PBI).

As shown in FIG. 2B, a first dielectric layer 22 is formed on the first insulating layer 21, and a first circuit layer 23 and multiple circuits formed on the first circuit layer 23 are embedded in the first dielectric layer 22. a first conductive post 24, and the first conductive post 24 is exposed on the first dielectric layer 22. Next, a plurality of first conductive elements 25 are formed on the first dielectric layer 22 (that is, the first conductive pillars 24 ) and are electrically connected to the first circuit layer 23 through the first conductive pillars 24 .

In this embodiment, there is no special limitation on the arrangement sequence of the first dielectric layer 22 , the first circuit layer 23 and the first conductive pillar 24 . For example, the first circuit layer 23 is first formed on the first insulating layer 21, and the first conductive column 24 is formed on a part of the first circuit layer 23, and then a dielectric material is formed on the first insulating layer 21, so that The first circuit layers 23 and the first conductive pillars 24 are embedded in the first dielectric layer 22 .

In addition, there is no special limitation on the material for forming the first dielectric layer 22 , such as prepreg, molding compound or photosensitive dielectric layer. In addition, the material for forming the first dielectric layer 22 can also be the same material as that of the first insulating layer 21 .

Also, the first conductive element 25 is a copper column, a solder ball or a solder ball with a core copper ball (Cu coreball), etc., and its shape is not particularly limited, and it can be a cylinder, an elliptical cylinder or a polygon. Any cylinder is acceptable.

In addition, in the first coreless package substrate 2' shown in FIG. 2B', the first conductive pillar 24 can be omitted, so that the first conductive element 25 is arranged on the first circuit layer 23 and directly electrically connected The first wiring layer 23 is connected, and the first dielectric layer 22' can be a solder resist layer such as green paint. Specifically, a first insulating layer 21' such as a dielectric material can be selectively formed on a carrier board 20. For example, when the carrier board 20 is made of copper, when the carrier board 20 is subsequently removed, The first insulating layer 21' can prevent over etch from damaging the first circuit layer 23; if the carrier board 20 and the first circuit layer 23 are made of different materials, the formation of the first insulating layer can be omitted twenty one'.

3A to 3C are cross-sectional schematic diagrams of the manufacturing method of the second coreless package substrate 3 of the present invention.

As shown in FIG. 3A to FIG. 3C , a carrier board 30 having a second insulating layer 31 is provided, and then a circuit build-up structure 3 a is formed on the second insulating layer 31 . Next, a plurality of second conductive elements 35 are formed on the circuit build-up structure 3a and electrically connected to the circuit build-up structure 3a.

In this embodiment, the carrier plate 30 is a metal plate, a semiconductor wafer or a glass plate.

In addition, the material forming the second insulating layer 31 is selected from a solder mask such as green paint, polyimide (PI for short), polyamide-imide (PAI for short), or polybenzimidazole (polybenzimidazole). , referred to as PBI).

Moreover, the circuit build-up structure 3a includes a plurality of second dielectric layers 32, a second circuit layer 33 disposed on the second dielectric layer 32, and embedded in the second dielectric layer 32 to provide electrical A plurality of second conductive pillars 34 connected to the second circuit layer 33 . Specifically, the material forming the second dielectric layer 32 such as prepreg, molding compound or photosensitive dielectric layer, but not limited thereto, and the second dielectric layer 32, the second The arrangement order of the circuit layer 33 and the second conductive pillar 34 is not particularly limited. For example, the second conductive pillars 34 are first formed on the second circuit layer 33, and then the second dielectric layer 32 is formed on the second insulating layer 31 to cover the second circuit layers 33 and the second conductive pillars 34. , and on the outermost second dielectric layer 32 and the second circuit layer 33, a solder resist layer 32' like green paint is formed, so that part of the surface of the outermost second circuit layer 33 is exposed to the solder resist layer 32'.

In addition, the second conductive element 35 is a copper column, a solder ball (solder ball) or a solder ball with a core copper ball (Cu coreball), etc., and is not particularly limited, and it is arranged on the second circuit layer 33 and directly Electrically connected to the second circuit layer 33 .

4A to 4C are schematic cross-sectional views of the manufacturing method of the package stack structure 4 of the present invention.

As shown in FIG. 4A , the structure shown in FIG. 3C is provided, and an electronic element 40 is disposed on a part of the second conductive element 35 of the second coreless package substrate 3 .

In this embodiment, the electronic component 40 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 40 is a semiconductor chip, which has an opposite active surface 40a and a non-active surface 40b, the active surface 40a has a plurality of electrode pads 400, and the electrode pads 400 are flip-chip by the The second conductive elements 35 are electrically connected to the second circuit layer 33 . In another embodiment, the second conductive element 35 is formed on the electrode pad 400 first, and then the electronic element 40 is bonded to the second circuit layer 33 by the second conductive element 35 .

As shown in FIG. 4B, the structure shown in FIG. 2B is provided, and the first conductive element 25 of the first coreless packaging substrate 2 is combined with part of the second conductive element 35 of the second coreless packaging substrate 3, so that The first coreless packaging substrate 2 is stacked on the second coreless packaging substrate 3 . Next, an encapsulation layer 41 is formed between the first core-free packaging substrate 2 and the second core-free packaging substrate 3, so that the encapsulation layer 41 covers the electronic component 40, the first conductive The element 25 and the second conductive elements 35 .

In this embodiment, the encapsulation layer 41 is an insulating material, such as epoxy resin encapsulant.

In addition, before combining the first coreless packaging substrate 2 and the second coreless packaging substrate 3, a primer (not shown) may be formed on the electronic component 40 and the second coreless packaging substrate. Between the substrates 3.

It should be understood that the structure shown in FIG. 2B' can also be replaced by the structure shown in FIG. 2B for stacking.

Moreover, in other embodiments, as shown in FIG. 4A' and FIG. 4B', the first conductive elements 25 can be firstly provided on one side of the second coreless package substrate 3, and part of the second conductive elements The component 35 is disposed on the first coreless packaging substrate 2 , and then the first coreless packaging substrate 2 is bonded to the second coreless packaging substrate 3 .

As shown in FIG. 4C , the carrier plates 20, 30 are removed, and then a plurality of first openings 210 and a plurality of second openings 310 are respectively formed on the first insulating layer 21 and the second insulating layer 31, The first circuit layers 23 are exposed in the first openings 210 , and the second circuit layers 33 are exposed in the second openings 310 , so as to form the package stack structure 4 .

In this embodiment, the thickness T of the package stack structure 4 is about 440 microns.

In addition, if stacking is performed with the structure shown in FIG. 2B', when there is the first insulating layer 21', a plurality of first openings 210 can be formed on the first insulating layer 21'; When the insulating layer 21' is used, the first circuit layers 23 are exposed on the first dielectric layer 22'.

In another embodiment, as shown in FIG. 4C', solder balls 42 can be combined on the second circuit layer 33 in the second opening 310 to be connected to an electronic device such as a circuit board (not shown). And the first circuit layer 23 in the first opening 210 can be combined with solder material 43 to join another electronic component 44 such as a chip, and then form a packaging material 45 to cover the electronic component 44, so that the packaging can be stacked The structure 4' becomes a Package on Package (POP for short).

It should be understood that a package or an electronic device such as a circuit board may also be combined on the first circuit layer 23 in the first opening 210 .

It should be understood that, as shown in FIG. 4C', a primer 41' may be formed between the second coreless package substrate 3 and the electronic component 40 to cover part of the second conductive component 35, and make the package Layer 41 covers the primer 41'.

The manufacturing method of the present invention reduces the thickness of the upper and lower packaging substrates by stacking the first coreless packaging substrate 2, 2' and the second coreless packaging substrate 3, so compared with conventional The known technology can not only omit the material and process of the core layer to reduce the production cost, but also can greatly reduce the overall thickness of the package stack structure 4, 4' to meet the trend of light, thin and short electronic products.

5A to 5C are schematic cross-sectional views of another embodiment of the manufacturing method of the second core-less packaging substrate 3' of the present invention. The difference between this embodiment and the embodiment shown in FIGS. 3A to 3C lies in the manufacturing process of the circuit build-up structure 5a.

As shown in FIG. 5A , a carrier 50 is provided, on which a release layer 500 and a metal layer 501 are formed. Next, a second circuit layer 53 is formed on the metal layer 501 .

As shown in FIG. 5B , a plurality of second dielectric layers 52 are formed on the metal layer 501 , a second circuit layer 53 disposed on the second dielectric layer 52 and an electrical circuit in the second dielectric layer 52 are formed. A plurality of second conductive pillars 54 (that is, conductive blind holes) that are electrically connected to the second circuit layer 53 .

In this embodiment, the second dielectric layer 52 is formed first, and then the second circuit layer 53 is formed on the second dielectric layer 52 , and the second conductive pillar 54 is formed in the second dielectric layer 52 .

As shown in FIG. 5C , the carrier 50 is removed through the release layer 500 , and then the metal layer 501 is removed by etching. Next, solder resist layers 32', 52' are respectively formed on the second dielectric layer 52 on opposite sides, and the second circuit layer 53 is exposed to the solder resist layers 32', 52', so as to complete the circuit augmentation. Layer structure 5a. After that, a plurality of second conductive elements 35 are formed on at least one side of the second circuit layer 53 and electrically connected to the second circuit layer 53 .

Therefore, the second coreless packaging substrate 3' can replace the second coreless packaging substrate 3 shown in FIG. 4C. For example, the second conductive elements 35 are combined with the electronic element 40 and the first conductive element 25 .

6A to 6C are cross-sectional schematic diagrams of another embodiment of the manufacturing method of the second core-free packaging substrate 3" of the present invention. The difference between this embodiment and the embodiment of FIGS. 3A to 3C lies in the circuit build-up layer Fabrication of structure 6a.

As shown in FIG. 6A, a carrier 60 is provided with a metal layer 601 on its upper and lower sides, and then a second dielectric layer 62 and a second circuit layer are formed on the metal layer 601 according to the process shown in FIGS. 3A to 3B. 63 and the second conductive pillar 64. Next, the carrier plate 30 and the second insulating layer 31 are formed (eg, laminated) on the outermost second dielectric layer 62 and the second circuit layer 63 .

As shown in FIG. 6B , the carrier 60 and the metal layer 601 are removed to expose the second dielectric layer 62 and the second circuit layer 63 .

As shown in FIG. 6C , a solder resist layer 32' is formed on the outermost second dielectric layer 62 and the second circuit layer 63, and part of the second circuit layer 63 is exposed on the solder resist layer 32'. Next, a plurality of second conductive elements 35 are formed on the exposed second circuit layer 63 .

Therefore, in the structure shown in FIG. 6C , when the process shown in FIG. 4A is performed, the electronic element 40 will be disposed on a part of the second conductive element 35 of the second coreless packaging substrate 3 ″.

To sum up, the manufacturing method of the packaging stack structure 4,4' of the present invention is mainly by stacking the first coreless layer packaging substrate 2,2' and the second coreless layer packaging substrate 3,3', 3", so as to omit the material and process of the core layer and reduce the thickness of the package stack structure 4,4'.

The above-mentioned embodiments are only used to illustrate the principles and effects of the present invention, but not to limit the present invention. Anyone skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (20)

1. A method for packaging a stacked structure, characterized in that the method comprises: A first coreless packaging substrate and a second coreless packaging substrate are provided, wherein at least one electronic component is provided on one side of the second coreless packaging substrate; bonding the first coreless package substrate to a side of the second coreless package substrate on which the electronic component is disposed with a plurality of first conductive elements; and An encapsulation layer is formed between the first coreless packaging substrate and the second coreless packaging substrate, so that the encapsulation layer covers the first conductive components and the electronic components. 2. The method of manufacturing a package stack structure according to claim 1, wherein the first coreless package substrate further comprises a first dielectric layer, and embedded in the first dielectric layer and The first circuit layers of the first conductive elements are electrically connected. 3. The method for manufacturing a package stack structure according to claim 2, wherein the first coreless package substrate further includes a substrate embedded in the first dielectric layer and formed on the first wiring layer. A plurality of first conductive pillars on the top, so that the first conductive elements are electrically connected to the first circuit layer through the first conductive pillars. 4. The method of manufacturing a package stack structure according to claim 1, wherein a carrier plate is combined with the other side of the first coreless package substrate opposite to the second coreless package substrate . 5 . The method for manufacturing a package stack structure according to claim 4 , further comprising removing the carrier board after forming the package layer. 6 . 6 . The method for manufacturing a package stack structure as claimed in claim 4 , wherein the first coreless package substrate is bonded to the carrier board with a first insulating layer. 7 . 7 . The method for manufacturing a package stack structure according to claim 6 , further comprising removing the carrier board after forming the package layer. 8 . 8 . The method for manufacturing a package stack structure according to claim 7 , further comprising forming a plurality of first openings in the first insulating layer after removing the carrier board. 9 . The method for manufacturing a package stack structure according to claim 1 , wherein a primer is formed between the second coreless package substrate and the electronic component. 10 . 10. The method for manufacturing a package stack structure according to claim 1, wherein the second coreless package substrate includes a circuit build-up structure, and the first conductive element and the electronic component are electrically connected Connect this line build-up structure. 11. The method for manufacturing a package stack structure according to claim 10, wherein the second coreless package substrate further comprises a layer formed on the circuit build-up structure and electrically connected to the circuit build-up structure a plurality of second conductive elements, so that the second conductive elements are combined with the first conductive element and the electronic element. 12 . The method for manufacturing a package stack structure according to claim 11 , wherein the package layer further covers the second conductive elements. 13 . 13. The method of manufacturing a package stack structure according to claim 10, wherein the second coreless package substrate further comprises a second insulating layer formed on the circuit build-up structure. 14. The method of manufacturing a package stack structure according to claim 13, further comprising: before combining the first and second coreless layer package substrates, the second coreless layer package The base plate is combined with another carrier plate through the second insulating layer. 15. The method for manufacturing a package stack structure according to claim 14, further comprising removing the other carrier board after forming the package layer. 16. The method of manufacturing a package stack structure according to claim 15, further comprising forming a plurality of second openings in the second insulating layer after removing the other carrier board . 17 . The method for manufacturing a package stack structure according to claim 1 , further comprising disposing another electronic component on the first coreless layer package substrate after forming the package layer. 18 . 18. The method of manufacturing a package stack structure according to claim 17, further comprising forming a packaging material on the first coreless package substrate, so that the packaging material covers the other an electronic component. 19. The manufacturing method of the package stack structure according to claim 1, wherein the first conductive elements are firstly arranged on one side of the first coreless package substrate, and then the first coreless A layer packaging substrate is bonded to the second coreless layer packaging substrate. 20. The method for manufacturing a package stack structure according to claim 1, wherein the first conductive elements are firstly arranged on one side of the second coreless package substrate, and then the first coreless A layer packaging substrate is bonded to the second coreless layer packaging substrate.