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CN112992837A - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
CN112992837A
CN112992837A CN201911327588.0A CN201911327588A CN112992837A CN 112992837 A CN112992837 A CN 112992837A CN 201911327588 A CN201911327588 A CN 201911327588A CN 112992837 A CN112992837 A CN 112992837A
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CN
China
Prior art keywords
layer
conductive
bearing structure
electronic package
columns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911327588.0A
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Chinese (zh)
Inventor
白裕呈
米轩皞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN112992837A publication Critical patent/CN112992837A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49527—Additional leads the additional leads being a multilayer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention relates to an electronic package and a manufacturing method thereof, which comprises the steps of providing an upper bearing structure provided with a plurality of supporting columns and a lower bearing structure provided with an electronic element, combining the upper bearing structure to the lower bearing structure through the plurality of supporting columns, and forming a packaging layer between the upper bearing structure and the lower bearing structure so as to lead the packaging layer to cover the supporting columns and the electronic element, thereby replacing the existing solder balls through the supporting columns and avoiding the problem of solder ball bridging.

Description

Electronic package and manufacturing method thereof
Technical Field
The present invention relates to a semiconductor packaging process, and more particularly, to a stacked electronic package and a method for fabricating the same.
Background
With the development of Semiconductor packaging technology, Semiconductor devices (Semiconductor devices) have been developed with different Package types, wherein, in order to improve electrical performance and save Package space, a Package type of stacking a plurality of Package structures to form a Package On Package (POP) structure has been developed, which can exert heterogeneous integration characteristics of System In Package (SiP) and can be used to Package electronic devices with different functions, such as: the memory, the central processing unit, the graphic processor, the image application processor and the like achieve the integration of the system through the stacking design, and are suitable for various light, thin, short and small electronic products.
Fig. 1 is a schematic cross-sectional view of a conventional package stack 1. As shown in fig. 1, the package stack 1 includes a first semiconductor device 10, a first package substrate 11, a second package substrate 12, a plurality of solder balls 13, a second semiconductor device 14, and a molding compound 15. The first package substrate 11 has a core layer 110 and a plurality of circuit layers 111, and the second package substrate 12 has a core layer 120 and a plurality of circuit layers 121. The first semiconductor device 10 is disposed on the first package substrate 11 in a flip-chip manner, and the second semiconductor device 14 is also disposed on the second package substrate 12 in a flip-chip manner. The solder balls 13 are used to connect and electrically couple the first package substrate 11 and the second package substrate 12. The encapsulant 15 encapsulates the solder balls 13 and the first semiconductor device 10. Optionally, an underfill 16 is formed between the first semiconductor device 10 and the first package substrate 11.
However, in the manufacturing method of the conventional package stack structure 1, since the solder balls 13 are used as supporting and electrically connecting elements between the first package substrate 11 and the second package substrate 12, and the solder balls 13 have a certain width, as the number of contacts (I/O) of the electronic product increases, the spacing between the solder balls 13 needs to be reduced under the condition that the size of the package is not changed, so that bridging (bridge) is likely to occur, which causes the problems of low yield and poor reliability of the product, i.e., the solder balls 13 cannot meet the requirement of fine pitch (fine pitch).
In addition, the solder balls 13 are formed on the first package substrate 11 by ball-planting or screen printing (screen printing), and the volume and height tolerance after reflow is large, which not only causes defects in the contacts and poor electrical connection quality, but also causes poor coplanarity (coplanarity) in the grid array (grid array) formed by the solder balls 13, which causes unbalanced contact stress (stress) and easily causes the first package substrate 11 and the second package substrate 12 to be obliquely connected, and even causes the contact offset.
Therefore, how to overcome the above problems of the prior art has become a problem to be overcome in the industry.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package and a method for fabricating the same, so as to avoid the problem of solder ball bridging.
An electronic package of the present invention includes: a lower load bearing structure; an upper bearing structure provided with a plurality of conductive posts; a plurality of support pillars, disposed on the plurality of conductive pillars, for combining the upper carrying structure with the lower carrying structure via the plurality of support pillars; the packaging layer is arranged on the lower bearing structure to coat the plurality of support columns; and a coating layer formed between the packaging layer and the upper bearing structure to coat the plurality of conductive columns.
The invention also provides a manufacturing method of the electronic packaging piece, which comprises the following steps: providing an upper bearing structure and a lower bearing structure which are provided with a plurality of conductive columns, wherein a plurality of supporting columns are respectively formed on the corresponding conductive columns, a coating layer for coating the conductive columns is formed on the upper bearing structure, and the supporting columns are enabled to protrude out of the coating layer; combining the upper bearing structure to the lower bearing structure through the supporting columns; and forming a packaging layer between the coating layer and the lower bearing structure so that the packaging layer coats the plurality of support columns.
In the foregoing method, the process of the support pillar includes: providing a conductive frame which comprises a plate body and a plurality of conductive columns which are separately arranged on the plate body; arranging the conductive frame on the upper bearing structure by the plurality of conductive columns; forming the coating layer between the upper bearing structure and the plate body to coat the plurality of conductive columns; and removing part of the material of the plate body to enable the remaining material of the plate body to serve as a plurality of supporting columns. Further, before forming the supporting pillars, a resist layer is formed on the board body to remove a portion of the material of the board body not covered by the resist layer.
In the foregoing manufacturing method, the encapsulation layer is formed by injection molding or dispensing.
In the electronic package and the method for manufacturing the same, an electronic element is disposed on the lower supporting structure, and the package layer further encapsulates the electronic element.
In the electronic package and the manufacturing method thereof, the supporting pillar and the conductive pillar are integrally formed.
In the electronic package and the method for manufacturing the same, the materials of the package layer and the encapsulation layer may be the same or different.
The electronic package and the method for manufacturing the same further include disposing an electronic component on the upper supporting structure.
In an embodiment, the upper carrier structure is configured with a first ground plane, and the lower carrier structure is configured with a second ground plane, so that the first ground plane and the second ground plane are electrically connected to the conductive pillar and the supporting pillar.
In view of the above, the electronic package and the method for manufacturing the same of the present invention mainly replace the existing solder ball by the pillar body formed by the conductive pillar and the support pillar to adjust the spacing between the pillars according to the requirement, so compared with the prior art, the problem of bridging between the pillars does not occur, thereby effectively improving the yield and reliability of the product to meet the requirement of fine spacing.
Drawings
Fig. 1 is a cross-sectional view of a conventional package stack structure.
Fig. 2A to 2F are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to the present invention.
Fig. 3 is a schematic cross-sectional view of another embodiment of an electronic package of the present invention.
Description of the reference numerals
1-package-on-package structure 10 first semiconductor element
11 first package substrate 110,120 core layer
111,121 wiring layer 12 second package substrate
13 solder ball 14 second semiconductor element
15 encapsulant 16 primer
2 electronic package 2a first package module
2b second encapsulation module 20 conductive frame
20 'plate body 20' column
20a first surface 20b second surface
200 support column 201 conductive column
Carrier structure 210 line layer on 21
211 insulating layer 212 Electrical contact pad
22 lower bearing structure of cladding layer 23
230 dielectric layer 231 routing layer
232 electrical connection pad 233 solder material
24,34 active surface of electronic component 24a
24b non-active surface 240 electrode pad
25 conductive bump 26 encapsulation layer
27 conductive element 29 resist
290 open area 3a shield structure
310 first ground plane 330 second ground plane
S, L cutting the path.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, proportions, and dimensions shown in the drawings and described herein are for illustrative purposes only and are not intended to limit the scope of the present invention, which is defined by the claims, but rather by the claims. In addition, the terms "first", "second", "upper" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.
Please refer to fig. 2A to fig. 2F, which are schematic cross-sectional views illustrating a method for manufacturing an electronic package 2 according to the present invention.
As shown in fig. 2A, a conductive frame 20 is coupled to at least one upper supporting structure 21.
In this embodiment, the conductive frame 20 includes a plate 20 ' and a plurality of conductive posts 201 separately disposed on the plate 20 ', wherein the peripheral surface of the conductive posts 201 has an inward concave arc shape with respect to two opposite end surfaces, and the plate 20 ' and the conductive posts 201 are integrally formed. Specifically, a portion of a metal plate, such as a copper plate, is etched, laser-etched, or otherwise removed to form a plurality of spaced conductive pillars 201 on the plate 20'.
In addition, the board body 20 'has a first surface 20a and a second surface 20b opposite to each other, wherein the conductive pillars 201 are formed on the first surface 20a, and a patterned resist layer 29 is formed on the second surface 20b, so that the resist layer 29 has a plurality of opening regions 290, so that a portion of the second surface 20b of the board body 20' is exposed out of the opening regions 290.
In addition, the upper supporting structure 21 is, for example, a singulated package substrate (substrate) having a core layer and a circuit portion or a coreless (wire) singulated package substrate having a circuit portion, the circuit portion has at least one insulating layer 211 and a circuit layer 210 disposed on the insulating layer 211, the circuit layer 210 is, for example, a fan out (fan out) redistribution layer (RDL), and the outermost circuit layer 210 has a plurality of electrical contact pads 212, so as to combine the end surfaces of the conductive pillars 201 to electrically connect the conductive pillars 201 to the circuit layer 210.
The material forming the circuit layer 210 is, for example, copper, and the material forming the insulating layer 211 is, for example, a dielectric material such as Polyoxadiazole (PBO), Polyimide (PI), or Prepreg (PP). It should be understood that the upper supporting structure 21 may also be other supporting units for supporting electronic devices such as chips, for example, lead frame (lead frame) or silicon interposer (silicon interposer), but is not limited thereto.
As shown in fig. 2B, a cladding layer 22 is formed between the first surface 20a of the board body 20' and the upper carrying structure 21, so that the cladding layer 22 wraps the conductive pillars 201 and the side surfaces of the upper carrying structure 21.
In the embodiment, the cladding layer 22 is an insulating material, such as Polyimide (PI), dry film (dry film), and molding compound (molding compound) such as epoxy resin (epoxy). For example, the process of the coating layer 22 can be selected from liquid compound (liquid compound), spraying (injection), pressing (laminating), molding (compression molding), and the like.
As shown in fig. 2C, the plate body 20' is patterned to form a plurality of support posts 200. Thereafter, the resist layer 29 is removed to form a first package module 2a including the upper carrier structure 21, the supporting pillars 200, the conductive pillars 201 and the encapsulating layer 22.
In the present embodiment, the material of the board body 20 'exposed in the opening 290 of the resist layer 29 is removed by etching, and the material of the board body 20' covered by the resist layer 29 is remained to serve as the supporting pillars 200, so that the supporting pillars 200 are correspondingly located on the end surfaces of the conductive pillars 201. For example, the resist layer 29 serves as an etch stop layer, which is a metal material or a conductive material, such as Ni/Au, Ni/Pd/Au or other suitable materials.
In addition, the appearance of the supporting pillar 200 is similar to that of the conductive pillar 201. For example, the circumferential surface of the supporting column 200 is concavely curved with respect to the two end surfaces thereof, so that the width of the two end surfaces of the supporting column 200 is greater than the width of the circumferential surface thereof.
As shown in fig. 2D, a singulation process is performed along the cutting path L shown in fig. 2C to obtain a plurality of first package modules 2a, and the plurality of first package modules 2a are disposed on a second package module 2b by the supporting posts 200 thereof.
In the present embodiment, the second package module 2b includes a lower carrier structure 23 for combining the supporting pillar 200 and at least one electronic component 24 disposed on the lower carrier structure 23.
In addition, the lower carrier structure 23 is a circuit structure in a full-page (panel) form having a core layer or a coreless layer, such as a package substrate, which has a circuit configuration such as a fan-out (fan out) redistribution circuit layer (RDL). For example, the lower carrier structure 23 has at least one dielectric layer 230 and a wiring layer 231 disposed on the dielectric layer 230. Specifically, the dielectric layer 230 is formed of a material such as, but not limited to, prepreg (prepreg), molding compound (molding compound) or photosensitive dielectric material, and the wiring layer 231 has a plurality of electrical connection pads 232, so that the conductive posts 201 are electrically connected to the wiring layer 231 by solder 233 through the resist layer 29 in combination with the support posts 200. It should be understood that the lower supporting structure 23 can also be other boards for supporting chips, such as a lead frame, a wafer (wafer), a silicon interposer, or other substrates with metal wires (routing), and is not limited thereto.
In addition, the electronic component 24 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, and an inductor, or a combination thereof. For example, the electronic component 24 is a semiconductor chip having an active surface 24a and an inactive surface 24b opposite to each other, the active surface 24a has a plurality of electrode pads 240, and the electronic component 24 is disposed on the lower carrier structure 23 through the electrode pads 240 thereof in a flip-chip manner and electrically connected to the wiring layer 231 via a plurality of conductive bumps 25 such as solder material. Alternatively, the electronic device 24 can be electrically connected to the lower supporting structure 23 by wire bonding via a plurality of bonding wires (not shown); alternatively, the electronic component 24 can directly contact the circuit of the lower supporting structure 23, for example, the electronic component 24 is embedded in the lower supporting structure 23. It should be understood that the manner of electrically connecting the electronic components 24 to the lower supporting structure 23 is various and not limited to the above.
As shown in fig. 2E, an encapsulation layer 26 is formed between the lower carrier structure 23 and the encapsulation layer 22, such that the encapsulation layer 26 encapsulates the support pillars 200 and the electronic element 24 (even encapsulates the conductive bumps 25; alternatively, the conductive bumps 25 may be encapsulated by underfill (not shown)).
In the present embodiment, the package layer 26 is an insulating material, such as Polyimide (PI), dry film (dry film), and molding compound (molding compound) such as epoxy resin (epoxy), and can be formed by injection molding or dispensing. It should be understood that the material forming the encapsulation layer 26 may be the same or different than the material of the cladding layer 22.
As shown in fig. 2F, a singulation process is performed along the cutting path S shown in fig. 2E to obtain a plurality of electronic packages 2.
In the present embodiment, a ball-mounting process is performed on the lower side of the lower supporting structure 23 to form a plurality of conductive elements 27, such as solder balls, so that the electronic package 2 can be disposed on a circuit board (not shown) via the conductive elements 27 in a subsequent process.
In addition, another electronic component 34 such as a semiconductor chip or other electronic devices can be disposed on the upper side of the upper supporting structure 21, so that the electronic component 34 is electrically connected to the upper supporting structure 21. For example, the electronic component 34 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, and an inductor, or a combination thereof. It should be understood that the manner for electrically connecting the electronic component 34 to the upper supporting structure 21 is various and is not particularly limited.
In addition, as shown in fig. 3, the upper carrying structure 21 may be configured with a first ground layer 310, and the lower carrying structure 23 may also be configured with a second ground layer 330, so that the first ground layer 310 and the second ground layer 330 are electrically connected to the conductive pillars 201 and the supporting pillars 200 to form a shielding structure 3a, so that the electronic component 24 is prevented from being subjected to external Electromagnetic Interference (EMI) through the design of the shielding structure 3 a.
The manufacturing method of the invention mainly replaces the existing solder ball by the integrally formed column 20 ' formed by the conductive column 201 and the supporting column 200, so the distance between the columns 20 ' can be adjusted according to the requirement, compared with the prior art, the problem of bridging among the columns 20 ' is not easy to occur, thereby effectively improving the yield and the reliability of the product and meeting the requirement of fine pitch.
In addition, since the material and manufacturing cost of the conductive frame 20 are low, the cost of the overall process of the electronic package 2 can be effectively reduced
In addition, since the first package module 2a and the second package module 2b are separately fabricated to independently perform a function test operation, the yield of the electronic device 24 can be detected before the package layer 26 is formed, so as to improve the yield of the electronic package 2.
In addition, the first package module 2a generates a stiffener (stiffener) effect by the design of the cover layer 22, so as to prevent the first package module 2a from warping (warping), and the material and parameters of the cover layer 22 (such as warping parameter after forming the cover layer 22) can be adjusted in real time according to the warping state of the second package module 2 b. It should be understood that the material and parameters of the encapsulation layer 26 may be adjusted according to the warpage state after the first package module 2a and the second package module 2b are stacked.
The present invention also provides an electronic package 2 comprising: the package structure includes an upper carrier structure 21, a plurality of support pillars 200, a covering layer 22, a lower carrier structure 23, and an encapsulation layer 26.
The upper supporting structure 21 is provided with a plurality of conductive pillars 201.
The supporting pillars 200 are disposed on the conductive pillars 201, so that the upper carrying structure 21 is combined with the lower carrying structure 23 through the supporting pillars 200.
The encapsulation layer 26 is disposed on the lower carrier structure 23 to cover the plurality of supporting pillars 200.
The encapsulating layer 22 is formed between the package layer 26 and the upper carrier structure 21 to encapsulate the conductive pillars 201.
In one embodiment, the electronic package 2 further includes an electronic component 24 disposed on the lower supporting structure 23, and the package layer 26 further encapsulates the electronic component 24.
In one embodiment, the supporting pillar 200 and the conductive pillar 201 are integrally formed.
In one embodiment, the materials of the encapsulation layer 26 and the cladding layer 22 are the same or different.
In one embodiment, the electronic package 2 further includes at least one electronic component 34 disposed on the upper supporting structure 21.
In one embodiment, the upper carrying structure 21 is configured with a first grounding layer 310, and the lower carrying structure 23 is configured with a second grounding layer 330, so that the first grounding layer 310 and the second grounding layer 330 are electrically connected to the conductive pillar 201 and the supporting pillar 200 to form a shielding structure 3 a.
In summary, the electronic package and the fabrication method thereof of the present invention mainly adjust the spacing between the support pillars according to the requirement through the pillars formed by the conductive pillars and the support pillars, so that the problem of bridging is not easy to occur, and the yield and reliability of the product can be effectively improved to meet the requirement of fine spacing.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (17)

1.一种电子封装件，其特征在于，包括：1. An electronic package, characterized in that, comprising: 下承载结构；lower bearing structure; 上承载结构，其设有多个导电柱；an upper bearing structure, which is provided with a plurality of conductive columns; 多个支撑柱，其设于该多个导电柱上，以令该上承载结构经由该多个支撑柱结合该下承载结构；a plurality of support columns, which are arranged on the plurality of conductive columns, so that the upper bearing structure is combined with the lower bearing structure through the plurality of support columns; 封装层，其设于该下承载结构上以包覆该多个支撑柱；以及an encapsulation layer disposed on the lower bearing structure to cover the plurality of support columns; and 包覆层，其形成于该封装层与该上承载结构之间，以包覆该多个导电柱。A cladding layer is formed between the encapsulation layer and the upper support structure to encapsulate the plurality of conductive pillars. 2.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括设于该下承载结构上的电子元件，且该封装层还包覆该电子元件。2 . The electronic package of claim 1 , wherein the electronic package further comprises an electronic component disposed on the lower supporting structure, and the packaging layer further covers the electronic component. 3 . 3.根据权利要求1所述的电子封装件，其特征在于，该支撑柱与该导电柱为一体成形。3 . The electronic package of claim 1 , wherein the support column and the conductive column are integrally formed. 4 . 4.根据权利要求1所述的电子封装件，其特征在于，该封装层与该包覆层的材料为相同。4 . The electronic package of claim 1 , wherein the materials of the packaging layer and the cladding layer are the same. 5 . 5.根据权利要求1所述的电子封装件，其特征在于，该封装层与该包覆层的材料为不相同。5 . The electronic package of claim 1 , wherein the materials of the packaging layer and the cladding layer are different. 6 . 6.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括设于该上承载结构上的电子元件。6 . The electronic package of claim 1 , wherein the electronic package further comprises electronic components disposed on the upper support structure. 7 . 7.根据权利要求1所述的电子封装件，其特征在于，该上承载结构配置有第一接地层，且该下承载结构配置有第二接地层，以令该第一接地层与该第二接地层电性连接该导电柱与支撑柱。7 . The electronic package of claim 1 , wherein the upper carrier structure is configured with a first ground layer, and the lower carrier structure is configured with a second ground layer, so that the first ground layer and the first ground layer are configured with the first ground layer. 8 . The two ground layers are electrically connected to the conductive column and the support column. 8.一种电子封装件的制法，其特征在于，该制法包括：8. A manufacturing method of an electronic package, wherein the manufacturing method comprises: 提供一设有多个导电柱的上承载结构及一下承载结构，其中，对应该多个导电柱上分别形成有多个支撑柱，并于该上承载结构形成有一包覆该多个导电柱的包覆层，且令该多个支撑柱凸出该包覆层；Provide an upper bearing structure and a lower bearing structure with a plurality of conductive columns, wherein a plurality of supporting columns are respectively formed on the plurality of conductive columns, and a plurality of conductive columns is formed on the upper bearing structure. a cladding layer, and the plurality of support posts protrude from the cladding layer; 将该上承载结构以该支撑柱结合至该下承载结构上；以及bonding the upper bearing structure to the lower bearing structure with the support column; and 形成封装层于该包覆层与该下承载结构之间，以令该封装层包覆该多个支撑柱。An encapsulation layer is formed between the encapsulation layer and the lower bearing structure, so that the encapsulation layer covers the plurality of support posts. 9.根据权利要求8所述的电子封装件的制法，其特征在于，该支撑柱的制程包含：9. The method for manufacturing an electronic package according to claim 8, wherein the manufacturing process of the support column comprises: 提供一导电架，其包含一板体及分离设于该板体上的该多个导电柱；A conductive frame is provided, which includes a plate body and the plurality of conductive columns separated on the plate body; 将该导电架以该多个导电柱设于该上承载结构上；disposing the conductive frame and the plurality of conductive posts on the upper supporting structure; 于该上承载结构与该板体之间形成该包覆层以包覆该多个导电柱；以及forming the cladding layer between the upper support structure and the board to encapsulate the plurality of conductive pillars; and 移除该板体的部分材料，使该板体的保留材料作为该多个支撑柱。Part of the material of the plate body is removed, so that the remaining material of the plate body serves as the plurality of support columns. 10.根据权利要求9所述的电子封装件的制法，其特征在于，该制法还包括于形成该支撑柱之前，形成阻层于该板体上，以移除未为该阻层所覆盖的该板体的部分材料。10 . The method of claim 9 , wherein the method further comprises forming a resistance layer on the board before forming the support column to remove the resistance layer not covered by the resistance layer. 11 . Covering part of the material of the board. 11.根据权利要求8所述的电子封装件的制法，其特征在于，该制法还包括设置电子元件于该下承载结构上，且该封装层还包覆该电子元件。11 . The method of claim 8 , wherein the method further comprises disposing an electronic component on the lower supporting structure, and the packaging layer further covers the electronic component. 12 . 12.根据权利要求8所述的电子封装件的制法，其特征在于，该支撑柱与该导电柱为一体成形。12 . The method of claim 8 , wherein the support column and the conductive column are integrally formed. 13 . 13.根据权利要求8所述的电子封装件的制法，其特征在于，该封装层与该包覆层的材料为相同。13 . The method of claim 8 , wherein the packaging layer and the cladding layer are made of the same material. 14 . 14.根据权利要求8所述的电子封装件的制法，其特征在于，该封装层与该包覆层的材料为不相同。14 . The method of claim 8 , wherein the materials of the packaging layer and the cladding layer are different. 15 . 15.根据权利要求8所述的电子封装件的制法，其特征在于，该制法还包括设置电子元件于该上承载结构上。15 . The method of claim 8 , wherein the method further comprises disposing electronic components on the upper support structure. 16 . 16.根据权利要求8所述的电子封装件的制法，其特征在于，该上承载结构配置有第一接地层，且该下承载结构配置有第二接地层，以令该第一接地层与该第二接地层电性连接该导电柱与支撑柱。16. The method of claim 8, wherein the upper carrier structure is configured with a first ground layer, and the lower carrier structure is configured with a second ground layer, so that the first ground layer is configured The conductive column and the support column are electrically connected with the second ground layer. 17.根据权利要求8所述的电子封装件的制法，其特征在于，该封装层采用射出成形或点胶方式形成。17 . The method of claim 8 , wherein the packaging layer is formed by injection molding or dispensing. 18 .
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