201232620 六、發明說明： 【發明所屬之技術領域】 本發明係有關具有單軸應變鰭狀部之非平面裝置及其 製作方法。 【先前技術】 諸如微處理器等之微電子積體電路實際包含數以百萬 計的電晶體。積體電路的速度主要依據這些電晶體的性能 。因此’工業上已發展出諸如非平面式電晶體等之特有結 構，及對電晶體內的組件使用應變技術來提高性能。 【發明內容】及【實施方式】 在下面的詳細說明中，參考經由圖解呈現可實行所主 張之標的物之特定實施例的附圖。充分仔細說明這些實施 例，以使熟悉於本技藝之人士能夠實行該標的物。應明白 ，雖然各有不同，但是各種實施例不一定相互排它。例如 ，在不違背所主張之標的物的精神和範疇下，關於一個實 施例之其內所說明之特別特徵、結構、特性可被實施於其 他實施例之內。此外，應明白，在不違背所主張之標的物 的精神和範疇下，可修改各個所揭示的實施例內之個別元 件的位置或配置。因此，下面的詳細說明不以限制的觀點 來進行，而標的物的範圍僅藉由附加的申請專利範圍連同 附加的申請專利範圍所賦予權利之同等物的全部範圍來予 以定義、適當闡釋。在圖式中，相同號碼意指幾個圖式之 -5- 201232620 中相同或類似元件或功能，及其內所描劃的那元件不一定 彼此成比例，反而是可放大或縮小個別元件，以便更加容 易理解本發明說明中的元件。 本說明的實施例係有關於微電子裝置的製造。在至少 一個實施例中，本標的物係有關於在非平面式電晶體的半 導體本體中形成隔離結構。 在諸如三閘電晶體、FinFET、Ω-FET、及雙閘電晶體 等非平面式電晶體的製造中，可使用非平面式半導體本體 來形成具有非常小的閘極長度（例如，小於約3 0 nm )之 能夠完全空乏的電晶體。例如在三閘電晶體中，半導體本 體通常具有形成在塊狀半導體基板或絕緣體上矽晶片基板 上之有著頂表面和兩相對的側壁之鰭狀部形。閘極介電質 可被形成在鰭狀部的頂表面和側壁上，及閘極電極可被形 成在鰭狀部之頂表面上的閘極介電質之上且鄰接鰭狀部的 側壁上之閘極介電質。因此，因爲閘極介電質和閘極電極 鄰接於鰭狀部的三個表面，所以形成三個分開的通道。當 形成有三個分開的通道時，當打開電晶體時，鰭狀部可完 全空乏。 半導體本體通常係由含矽材料所形成，及如同熟悉於 本技藝之人士將明白一般，含矽材料中的感應應變可增加 通道遷移率。通道遷移率增加可產生有利點，包括但不侷 限於電阻縮減，效率提高、電流增加，及增速度加。可藉 由在其結晶結構中具有晶格失配（例如，不同的晶格常數 或尺寸）之材料而在鰭狀部上感應應變。例如，當諸如例 -6- 201232620 如鍺等包括應變感應元素在其內之矽和矽合金（其中，合 金包括矽鍺）被用於分別形成基板和鰭狀部時，矽與矽合 金之間的晶格參數差異可使砂合金被應變。嘉晶生長的應 變矽鍺爲生長在矽基板上之應變膜的一個例子。除此之外 ，可根據諸如例如CVD、PVD、MBE等眾所皆知之方法的 任一者或者任何其他適當的薄膜沈積處理來設置矽鍺膜。 實施例包含任何應變感應元素和可與基板的材料產生 晶格失配之半導體材料的合金。因此，此處所提到之應變 感應”元素”不一定侷限於來自元素的週期表之純元素，而 是可包括當與半導體材料成爲合金時如上述產生晶格失配 之任何材料。例如’當基板由矽製成時，碳和矽可被一起 用來形成由於與矽基板的晶格失配在鰭狀部產生拉伸應變 之SiC合金，與由於矽鍺所引起的壓縮應變相抗衡。根據 與上面有關矽鍺的段落所說明之方法相同的方法，可將 SiC例如設置在基板上。根據本實施例之應變感應元素的 其他實例可包括磷、硼、氮或錫。 圖1爲根據一個實施例之一些電晶體1〇〇的立體圖， 電晶體包括形成在形成於基板上的應變鰭狀部上之一些閘 極。在本發明的實施例中’基板1〇2可以是具有界定其間 的基板主動區106之諸如淺溝槽隔離（STI)區等一對間 隔開的隔離區1 04之單晶矽基板或絕緣體上矽晶片基板。 然而，基板1 〇 2不一定必須是單晶矽基板，及可以是其他 類型的基板’只要選擇基板材料和鰭狀部材料，以便根據 實施例而產生單軸應變組態。基板材料可包含例如鍺、砷 201232620 化鎵、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵、銻化 鎵等等，其可與矽組合之任一者。可藉由在基板102中形 成溝槽，以諸如包括例如Si02的氧化矽等電絕緣材料來 塡充溝槽而形成隔離區104。 被圖示成三閘電晶體之各個電晶體1 00包括界定鰭狀 部112之半導體本體110，半導體本體110被形成鄰接基 板主動區106。鰭狀部112包括延伸在隔離區104的表面 上方之裝置主動部113。裝置主動部113可具有頂表面 1 1 4和一對橫向相對側壁：側壁1 1 6及相對側壁1 1 8。半 導體本體110可由諸如具有與塊狀半導體基板102不同晶 格常數或尺寸之單晶半導體等材料所形成，以便半導體本 體110具有應變感應在其內。在本發明的一個實施例中， 半導體基板102爲單晶矽基板，及半導體本體110爲單晶 矽鍺合金。 如圖1另外所示，至少一閘極1 32可被形成在鰭狀部 112之上。爲了形成三閘裝置，可藉由形成閘極介電層 134在裝置主動部113之頂表面114上或鄰接於頂表面 1 1 4與一對橫向相對的側壁1 1 6、1 1 8上或鄰接於一對橫向 相對的側壁1 1 6、1 1 8，以及形成閘極電極層1 3 6在閘極介 電層134上或鄰接於閘極介電層134來製造閘極132。關 於雙閘裝置（未圖示出），閘極介電層將被形成在裝置主 動部113之一對橫向相對的側壁116、118上或鄰接於一 對橫向相對的側壁1 1 6、1 1 8，同時頂表面1 1 4將被閘極隔 離層所覆蓋，如同熟悉於本技藝之人士所知一般。 -8 - 201232620 閘極介電層1 3 4係可由任何眾所皆知的閘極介電材料 所形成，包括但不侷限於二氧化矽（si〇2 )，氮氧化矽（ SiOxNy )，氮化矽（Si3N4 )，及諸如氧化給、給矽氧化物 、氧化鑭、鑭鋁氧化物、氧化锆、鍩矽氧化物、氧化钽、 氧化鈦、鋇緦鈦氧化物、鋇鈦氧化物、緦鈦氧化物、氧化 釔、氧化鋁、鉛銃鉬氧化物、及鉛鋅鈮酸物等高k介電材 料。閘極介電層1 34係可藉由眾所皆知的技術來予以形成 ，諸如藉由諸如化學氣相沈積（”CVD”）'物理氣相沈積 (”PVD”）、原子層沉積（”ALD”）等沈積閘極電極材料 ，而後以眾所皆知的微影和蝕刻技術來圖案化閘極電極材 料，如同熟悉於本技藝之人士所知一般。 如圖1所示，閘極電極1 3 6可被形成在閘極介電層 134上或鄰接於閘極介電層134。閘極電極136係可藉由 眾所皆知的技術來予以形成，諸如藉由諸如化學氣相沈積 (”CVD”）、物理氣相沈積（”PVD”）、原子層沉積（ ”ALD”）等沈積閘極電極材料，而後以眾所皆知的微影和 蝕刻技術來圖案化閘極電極材料，如同熟悉於本技藝之人 士所知一般。 圖1之各個三閘電晶體的”寬度”等於側壁1 1 6處之裝 置主動部113的高度，加上頂表面114處之裝置主動部 1 1 3的寬度，加上相對側壁1 1 8處之裝置主動部1 1 3的高 度。在本發明的實施中，鰭狀部112在實質上垂直於閘極 132的方向上運作。關於雙閘電晶體（未圖示出），電晶 體的”寬度”將等於各個側壁處之裝置主動部的高度總和。 -9 - 201232620 閘極電極136可由任何適當閘極電極材料所形成。在 本發明的實施例中，閘極電極U6可由包括但不侷限於多 晶矽、鎢、釕、鈀、鉑、鈷、鎳、給、锆、鈦、鉬、鋁、 碳化鈦、碳化锆、碳化鉬、碳化鈴、碳化鋁、其他金屬碳 化物、金屬氮化物、及金屬氧化物之材料所形成。閘極電 極1 3 6可藉由眾所皆知的技術來予以形成，諸如藉由毯覆 式沈積（blanket depositing)閘極電極材料，而後以眾所 皆知的微影和蝕刻技術來圖案化閘極電極材料，如同熟悉 於本技藝之人士所知一般。 仍參考圖1，源極區140和汲極區142可被形成在閘 極電極136的相對側上之鰭狀部的裝置主動部113中。源 極和汲極區係可藉由相同導電型來予以形成，諸如N型或 P型導電等。源極和汲極區可具有均勻的摻雜濃度或可包 括不同濃度的子區或諸如頂端區等摻雜外形（例如，源極 /汲極延長部）。在本發明的實施例之一些實施中，源極 和汲極區可具有實質上相同的摻雜濃度和外形，而在其他 實施例中它們可改變。根據一個實施例，鰭狀部可包括源 極區和汲極區處之材料，其在其晶體結構與基板材料的晶 體結構之間存在晶格失配，此失配大於鰭狀部非源極-汲 極區的結晶結構與基板材料的晶體結構之間的晶格失配。 以此方式’源極和汲極區可存在比鰭狀部的其他區域更高 的應變在鰭狀部中之區域。源極和汲極區的較高晶格失配 可被使用來增加通道中的應變，此更進一步提高通道遷移 率。 -10- 201232620 可以一些不同方式來達成上述的較大晶格失配。例如 ’根據一個實施例’在將設置源極和汲極.區之位置處的鰭 狀部中可界定凹部區。例如，鰭狀部可受到蝕刻技術，以 設置凹部於其內’如同熟悉於本技藝之人士所知一般。可 藉由對準触刻到多閘裝置的閘極電極堆疊和間隔物之源極 /汲極凹α卩’例如以自我對準方式來實現源極汲極凹部的 倉虫刻。之後’用於源極和汲極區之材料可磊晶再生長到凹 部內。用於源極和汲極區之材料例如可包括被摻雜的材料 及/或包括與存在於鰭狀部剩餘部分中之百分比相同的應 變感應元素之百分比的材料。例如，在鰭狀部材料包括矽 鍺合金處’可以被摻雜的矽鍺合金及/或以具有與存在於 鰭狀部剩餘部分中之百分比相同的鍺之百分比的矽鍺合金 來再充塡源極和汲極凹部。矽鍺例如可被摻雜有硼或任何 其他類似的摻雜劑，如同熟悉於本技藝之人士所知一般。 在鰭狀部材料包括SiC處，摻雜劑選擇可包括例如磷，如 同熟悉於本技藝之人士所知一般。 根據另一實施例，經由離子摻雜可佈植更多的應變感 應元素到鰭狀部的材料內，以便給予更多的應變到源極和 汲極區處的鰭狀部，因而避免在源極和汲極區中設置凹部 的需要。在此種實例中，源極和汲極區將展現比鰭狀部之 其他區域更高的摻雜位準。例如，摻雜劑可包括硼或任何 其他類似摻雜劑，如同熟悉於本技藝之人士所知一般。根 據實施例之摻雜劑的例子可包括鍺以增加應變，或硼以提 高電阻，在實施例的範圍內之其他摻雜劑。 -11 - 201232620 接著參考圖2a-2c，根據三個實施例圖示電晶體的橫 剖面。圖2a將半導體本體110圖示成具有基底部111和 鰭狀部1 1 2，其中基底部1 1 1係位在基板1 02與隔離區 104之間，且其中基板具有實質上平坦的上表面103。然 而，並未如此地侷限實施例。例如，如各自圖2 b及2 c所 示，在沒有延伸在基板102上方的基底部之下，半導體本 體1 1 〇可由鰭狀部1 1 2所組成（亦如圖1所示，圖2b爲 沿著線Π-ΙΙ之圖1的橫剖面）。根據一個實施例，基板 102可具有實質上平坦的上表面103，如圖2b所示，或者 在另一選擇中，基板102可包括基板基底部105和從基板 基底部105延伸出的基板鰭狀部107，半導體本體110的 鰭狀部112延伸在基板鰭狀部107的上方。 接著參考圖3，沿著圖2b的線III-III圖示橫剖面， 另外圖示第一ILD (層間介電）層1 5 0、源極和汲極接點 152及154以及閘極接點156。雖然亦圖示源極區140和 汲極區1 42，但是其位置如所示當然能夠交換。在所示之 實施例中，亦圖示頂端區158及160和間隔物162及164 。根據實施例，可如上述有關源極區140和汲極區M2來 設置頂端區。可以眾所皆知的方式來設置間隔物，如同熟 悉於本技藝之人士所知一般。以此方式，可以眾所皆知的 方式，將根據實施例之裝置倂入作爲積體電路的一部分。 裝置例如可以是PMOS裝置。 接著參考圖4、.5 a及5b，將說明根據實施例之裝置的 製造方法。方法實施例包含設置已應變的膜，其然後用作 -12- $ 201232620 爲自此形成應變鰭狀部的基礎，諸如例如經由蝕刻等，但 是從應變膜設置鰭狀部的其他方式係在實施例的範圍內。 如1圖4所見，方塊400中之方法實施例包括設置包括 諸如砂等第一材料之基板。在方塊402中，基板可被設置 包括第一材料。在方塊404中，雙軸應變膜可被設置在基 板上’及在方塊406中，單軸鰭狀部係可藉由蝕刻雙軸應 變膜而自雙軸應變膜所形成。 尤其特別地參考圖5a及5b，下面將說明例示方法實 施例。 首先參考圖5a，首先設置矽基板502，及生長在其上 之雙軸應變SiGe膜550。如上所述，SiGe膜係可使用 CVD、PVD、MBE、或任何其他適當薄膜沈積處理來予以 設置。可例如從約25 nm至約40 nm來形成SiGe膜550 的厚度。較厚的SiGe膜及/或SiGe中較高的鍺百分比通 常會在晶體內產生不想要的差排（dislocation)，其可能使 鰭狀部中的應變變低，而較薄的SiGe會具有相反效果。 通常，在不過度限制SiGe膜之厚度的同時可小心避免差 排。 如圖5b所見，SiGe膜5 5 0可受到微影和蝕刻’以便 產生所示之鰭狀部5 1 2。較佳的是’可使用乾式蝕刻’以 便以習知方式設置諸如例如用於提供淺溝槽隔離區等鰭狀 部。根據所示之實施例的SiGe膜55〇之蝕刻產生維持應 力在電流流動的方向CF上（亦即’在鰭狀部的縱向方向 上），同時實質上釋放應力在垂直於電流流動的方向上’ -13- 201232620 諸如圖5b所示之方向PCF等。 可選擇應變感應元素的百分比，以最佳化電晶體性能 ，如同熟悉於本技藝之人士所知一般。例如，在應變感應 元素包含鍺之處，鰭狀部的材料可以是在約30%與約70% 之間的鍺、及在約40%與約50%之間的鍺較佳。選用地， 鰭狀部的材料遍及延伸在基板與閘極介電質之間的其體積 可具有恆定的應變感應元素百分比。例如，參考圖2 a-2c ，配置在基板102與閘極介電質134之間的鰭狀部之部位 115 (亦即，如圖1及2a-2c所示之部位界定通道135)遍 及其體積可存在恆定的鍺百分比。此外，此恆定的百分比 可應用到遍及鰭狀部的全部體積。 參考下面表1，提供蝕刻含40%鍺的Si Ge膜之前和之 後的測量和模擬應變平均之比較。 藉由Raman (拉曼）所測量 之平均雙軸應變的平均 來自模擬之SiGe中的 平均雙軸應變之平均 蝕刻之前 -1.60% -1.55% 蝕刻之後 -0.85% -0.80% 表1 所測量之平均的平均係藉由將實際和模擬的Raman光 譜用於SiGe膜所獲得。平均的平均係藉由將Raman光譜 測量和有限元素爲基的應力模擬用於SiGe膜所獲得。如 表1的第一行所暗示一般，SiGe膜中的應變在蝕刻之後比 蝕刻之前小。有關雙軸應變SiGe膜的模擬資料之表1的 201232620 第二行與行中的値具有強烈關聯，及暗示雙軸應變釋放到 單軸後蝕刻。 接著參考圖6a，提供沿著電流流動的方向之通道中的 模擬平均應力對SiGe (矽鍺）鰭狀部中之鍺的百分比之標 繪圖。如從圖6a可清楚看出，沿著電流流動的方向之鰭 狀部中的鍺中之應力隨著SiGe鰭狀部材料中的鍺之百分 比增加而增加。因此，根據一些實施例，可藉由增加膜中 的鍺之百分比，或者藉由減少SiGe膜的寬度，或者二者 來獲得不同的想要應力。例如，增加諸如圖4a的SiGe膜 450等SiGe膜中的鍺之百分比的一方式將在於使用氧化來 減少膜的寬度。以此方式，諸如例如二氧化矽等氧化物中 的氧將與SiGe膜中之矽的某一些組合，消耗SiGe膜中之 矽的某一些並且使留在後面的SiGe中之鍺的濃度較高， 及進一步使後面的SiGe膜比氧化之前薄，以此方式在鰭 狀部中產生更多應變。 接著參考圖6b，提供遷移率對具有不同百分比的 SiGe膜之能帶隙及因此不同的單軸應力位準之標繪圖。圓 形表示不同百分比的膜後蝕刻之最後單軸應力。圖示表示 各種不同的遷移率和能帶隙係可藉由精心設計所設置的 SiGe膜之應力和Ge百分比來予以達成。例如，添加預定 百分比的鍺到源極和汲極區及/或使用諸如閘極應變、氮 化物覆蓋層等等其他應變技術可被用於修改具有最初的鍺 百分比之給定SiGe鰭狀部的通道之應力。 圖式和上述說明給予實施例例子。熟悉於本技藝之人 -15- 201232620 士將明白，所說明元件的一或多個可被適當組合成單一功 能元件。另一選擇是’某些元件可分裂成多個功能元件。 來自一個實施例的元件可添加到另一實施例。例如，此處 所說明的處理順序可改變’而不侷限於此處所說明的方式 。而且，不需要以所示之順序來實施任一流程圖的行爲； 也不需要一定執行所有行爲。再者，不依賴其他行爲的那 些行爲可與其他行爲並行執行。實施例的範圍絕不受這些 特定例子限制。無論說明書中是否明確指定，可有諸如結 構、尺寸、及材料使用的不同等許多變化。實施例的範疇 至少廣泛如同下面申請專利範圍所給定的一般。 【圖式簡單說明】 在說明書的最後部分特別指出和清楚申請本發明的標 的物專利範圍。從連同附圖之下面說明和附錄的申請專利 範圍將使本發明的上面和其他特徵更加清楚。應明白附圖 僅用來描劃根據本發明的幾個實施例，及因此不被用來侷 限其範圍。經由使用附圖將能更加具體和詳細說明本發明 ’使得能夠更容易確定本發明的有利點，其中： 圖1爲根據一個實施例之複數個非平面裝置的立體圖 » 圖2a-2c爲根據三個各自的實施例之電晶體的橫剖面 圖； 圖3爲圖示頂端及源極/汲極區之一個實施例的橫剖 面圖： -16- 201232620 圖4爲方法實施例的流程圖； 圖5a及5b爲包括基板和其上的應變膜之組裝的立體 圖； 圖6 a爲根據一例子之沿著電流流動的方向之通道中 的模擬平均應力對Si Ge (矽鍺）鰭狀部中之鍺的百分比之 標繪圖；以及 圖6b爲根據另一例子之遷移率對具有不同百分比的 Si Ge膜之能帶隙及因此不同的單軸應力位準之標繪圖。 【主要元件符號說明】 1〇〇 :電晶體 102 :基板 103 :上表面 104 :隔離區 105 :基板基底部 106 :基板主動區 107 :基板鰭狀部 1 1 0 :半導體本體 1 1 1 :基底部 1 1 2 :鰭狀部 1 1 3 :裝置主動部 1 1 4 :頂表面 1 1 5 :部位 1 1 6 :側壁 -17- 201232620 1 1 8 :相對側壁 1 3 2 :閘極 1 3 4 :閘極介電層 1 3 5 :部位界定通道 1 3 6 :閘極電極 1 4 0 :源極區 1 4 2 :汲極區 1 5 0 :層間介電層 1 5 2 :源極接點 154 :汲極接點 1 5 6 :閘極接點 1 5 8 :頂端區 1 6 0 :頂端區 1 6 2 :間隔物 1 6 4 :間隔物 5 02 :矽基板 5 1 2 :鰭狀部 5 5 0 :雙軸應變矽鍺膜 -18-201232620 VI. Description of the Invention: [Technical Field] The present invention relates to a non-planar device having a uniaxial strain fin and a method of fabricating the same. [Prior Art] A microelectronic integrated circuit such as a microprocessor actually contains millions of transistors. The speed of the integrated circuit is mainly based on the performance of these transistors. Therefore, industrially, unique structures such as non-planar transistors have been developed, and strain techniques have been used for components in the transistors to improve performance. DETAILED DESCRIPTION OF THE INVENTION [Embodiment] In the following detailed description, reference is made to the accompanying drawings, in which FIG. These embodiments are fully described in order to enable those skilled in the art to practice the subject matter. It should be understood that the various embodiments are not necessarily exclusive to each other, although different. For example, the particular features, structures, and characteristics described with respect to one embodiment may be practiced in other embodiments without departing from the spirit and scope of the claimed subject matter. In addition, it is to be understood that the location or configuration of the individual elements of the various disclosed embodiments can be modified without departing from the spirit and scope of the claimed subject matter. Therefore, the following detailed description is not to be taken in a limiting of the scope of the invention, and the scope of the invention is defined by the full scope of the equivalents of the appended claims. In the drawings, the same reference numbers refer to the same or similar elements or functions in the several figures -5 - 201232620, and the elements depicted therein are not necessarily proportional to each other, but the individual elements may be enlarged or reduced. In order to more easily understand the elements of the description of the invention. The embodiments of the present description relate to the fabrication of microelectronic devices. In at least one embodiment, the subject matter is related to forming an isolation structure in a semiconductor body of a non-planar transistor. In the fabrication of non-planar transistors such as tri-gate transistors, FinFETs, Ω-FETs, and dual-gate transistors, non-planar semiconductor bodies can be used to form very small gate lengths (eg, less than about 3) 0 nm) A transistor that is completely depleted. For example, in a tri-gate transistor, the semiconductor body typically has a fin-like shape having a top surface and two opposite sidewalls formed on the bulk semiconductor substrate or on the germanium wafer substrate. A gate dielectric may be formed on a top surface and a sidewall of the fin, and a gate electrode may be formed over the gate dielectric on the top surface of the fin and adjacent to the sidewall of the fin The gate dielectric. Therefore, since the gate dielectric and the gate electrode are adjacent to the three surfaces of the fin, three separate channels are formed. When three separate channels are formed, the fins are completely depleted when the transistor is turned on. The semiconductor body is typically formed of a germanium containing material, and as will be appreciated by those skilled in the art, the induced strain in the germanium containing material increases channel mobility. Increased channel mobility can yield advantages, including but not limited to resistor reduction, efficiency improvement, current increase, and rate increase. The strain can be induced on the fin by a material having a lattice mismatch (e.g., a different lattice constant or size) in its crystalline structure. For example, when a tantalum and niobium alloy (including an alloy including niobium) in which a strain sensing element is included, such as Example-6-201232620, is used to form a substrate and a fin, respectively, between the tantalum and niobium alloys The difference in lattice parameters allows the sand alloy to be strained. The strain of Jiajing growth is an example of a strain film grown on a tantalum substrate. In addition to this, the ruthenium film may be provided according to any of various methods such as CVD, PVD, MBE, or any other suitable thin film deposition process. Embodiments include any strain sensing element and an alloy of semiconductor material that can cause lattice mismatch with the material of the substrate. Accordingly, the strain-sensing "element" referred to herein is not necessarily limited to a pure element from the periodic table of elements, but may include any material that produces a lattice mismatch as described above when alloyed with a semiconductor material. For example, when a substrate is made of tantalum, carbon and tantalum can be used together to form a SiC alloy that produces tensile strain in the fin due to lattice mismatch with the tantalum substrate, and compressive strain due to tantalum. contend. SiC can be disposed, for example, on a substrate in the same manner as described in the paragraph above. Other examples of the strain sensing element according to the present embodiment may include phosphorus, boron, nitrogen or tin. 1 is a perspective view of some of the transistors 1A according to one embodiment, the transistors including some of the gates formed on the strained fins formed on the substrate. In an embodiment of the invention, the substrate 1 2 may be a single crystal germanium substrate or insulator having a pair of spaced apart isolation regions 104 such as shallow trench isolation (STI) regions defining a substrate active region 106 therebetween.矽 Wafer substrate. However, the substrate 1 〇 2 does not necessarily have to be a single crystal germanium substrate, and may be other types of substrates' as long as the substrate material and the fin material are selected to produce a uniaxial strain configuration according to an embodiment. The substrate material may comprise, for example, antimony, arsenic 201232620 gallium, indium antimonide, antimony telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and the like, which may be combined with niobium. The isolation region 104 can be formed by forming a trench in the substrate 102 and filling the trench with an electrically insulating material such as yttria including, for example, SiO 2 . Each of the transistors 100, illustrated as a three-gate transistor, includes a semiconductor body 110 that defines a fin portion 112 that is formed adjacent to the substrate active region 106. The fin 112 includes a device active portion 113 that extends over the surface of the isolation region 104. The device active portion 113 can have a top surface 1 14 and a pair of laterally opposite sidewalls: a side wall 1 16 and an opposite side wall 1 18 . The semiconductor body 110 may be formed of a material such as a single crystal semiconductor having a different lattice constant or size from the bulk semiconductor substrate 102 such that the semiconductor body 110 has strain sensing therein. In one embodiment of the invention, the semiconductor substrate 102 is a single crystal germanium substrate, and the semiconductor body 110 is a single crystal germanium alloy. As further shown in FIG. 1, at least one gate 1 32 can be formed over the fins 112. In order to form a three-gate device, a gate dielectric layer 134 may be formed on the top surface 114 of the device active portion 113 or adjacent to the top surface 112 and a pair of laterally opposite sidewalls 1 16 , 1 1 8 or A gate 132 is fabricated adjacent to a pair of laterally opposite sidewalls 1 16 , 1 1 8 and a gate electrode layer 136 formed on or adjacent to the gate dielectric layer 134. With regard to a dual gate device (not shown), the gate dielectric layer will be formed on one of the laterally opposite sidewalls 116, 118 of the device active portion 113 or adjacent to a pair of laterally opposite sidewalls 1 16 , 1 1 8. At the same time, the top surface 112 will be covered by the gate isolation layer as is known to those skilled in the art. -8 - 201232620 Gate dielectric layer 1 3 4 can be formed by any well-known gate dielectric material, including but not limited to cerium oxide (si〇2), cerium oxynitride (SiOxNy), nitrogen Antimony (Si3N4), and such as oxidizing, giving cerium oxide, cerium oxide, cerium oxide, zirconia, cerium oxide, cerium oxide, titanium oxide, cerium titanium oxide, cerium titanium oxide, cerium High-k dielectric materials such as titanium oxide, cerium oxide, aluminum oxide, lead lanthanum molybdenum oxide, and lead-zinc lanthanum. The gate dielectric layer 134 can be formed by well-known techniques, such as by chemical vapor deposition ("CVD"), physical vapor deposition ("PVD"), atomic layer deposition (" The gate electrode material is deposited, such as ALD", and then the gate electrode material is patterned using well known lithography and etching techniques, as is known to those skilled in the art. As shown in FIG. 1, a gate electrode 136 may be formed on or adjacent to the gate dielectric layer 134. Gate electrode 136 can be formed by well-known techniques, such as by, for example, chemical vapor deposition ("CVD"), physical vapor deposition ("PVD"), atomic layer deposition ("ALD"). The gate electrode material is deposited, and then the gate electrode material is patterned using well known lithography and etching techniques, as is known to those skilled in the art. The "width" of each of the three gate transistors of Figure 1 is equal to the height of the active portion 113 of the device at the side wall 116, plus the width of the active portion of the device at the top surface 114, plus the opposite side walls 1 18 The height of the active portion 1 1 3 of the device. In the practice of the present invention, the fins 112 operate in a direction substantially perpendicular to the gate 132. Regarding the double gate transistor (not shown), the "width" of the transistor will be equal to the sum of the heights of the active portions of the device at each side wall. -9 - 201232620 Gate electrode 136 can be formed from any suitable gate electrode material. In an embodiment of the invention, the gate electrode U6 may include, but is not limited to, polycrystalline germanium, tungsten, germanium, palladium, platinum, cobalt, nickel, donor, zirconium, titanium, molybdenum, aluminum, titanium carbide, zirconium carbide, molybdenum carbide. , carbonized bell, aluminum carbide, other metal carbides, metal nitrides, and metal oxide materials. The gate electrode 136 can be formed by well-known techniques, such as by blanket depositing a gate electrode material, followed by patterning using well-known lithography and etching techniques. The gate electrode material is as known to those skilled in the art. Still referring to FIG. 1, source region 140 and drain region 142 may be formed in device active portion 113 of the fin on the opposite side of gate electrode 136. The source and drain regions can be formed by the same conductivity type, such as N-type or P-type conductivity. The source and drain regions may have a uniform doping concentration or may include sub-regions of different concentrations or doped profiles such as tip regions (e.g., source/drain extensions). In some implementations of embodiments of the invention, the source and drain regions may have substantially the same doping concentration and profile, while in other embodiments they may vary. According to an embodiment, the fin may include a material at the source region and the drain region, which has a lattice mismatch between the crystal structure and the crystal structure of the substrate material, the mismatch being greater than the non-source of the fin a lattice mismatch between the crystalline structure of the drain region and the crystal structure of the substrate material. In this way, the source and drain regions may have a higher strain in the fin region than other regions of the fin. Higher lattice mismatches in the source and drain regions can be used to increase strain in the channel, which further increases channel mobility. -10- 201232620 There are a number of different ways to achieve the above larger lattice mismatch. For example, a recessed region may be defined in the fin portion where the source and drain regions are to be disposed, according to one embodiment. For example, the fins may be subjected to etching techniques to provide recesses therein as is known to those skilled in the art. The stagnation of the source drain recess can be achieved by self-aligning, for example, by aligning the gate electrode stack of the multi-gate device with the source/drain recess α' of the spacer. Subsequent materials for the source and drain regions can be epitaxially regenerated into the recesses. Materials for the source and drain regions may, for example, comprise a material that is doped and/or includes a percentage of the same percentage of strain sensitive elements present in the remainder of the fin. For example, the fin material may be doped with a niobium alloy at the niobium alloy and/or refilled with a niobium alloy having the same percentage as the niobium present in the remainder of the fin. Source and drain recesses. The ruthenium may, for example, be doped with boron or any other similar dopant as is known to those skilled in the art. Where the fin material comprises SiC, the dopant selection can include, for example, phosphorus, as is known to those skilled in the art. According to another embodiment, more strain sensing elements can be implanted into the material of the fin via ion doping to give more strain to the fins at the source and drain regions, thus avoiding the source The need to provide recesses in the pole and bungee zones. In such an example, the source and drain regions will exhibit higher doping levels than other regions of the fin. For example, the dopant can include boron or any other similar dopant as is known to those skilled in the art. Examples of dopants according to embodiments may include germanium to increase strain, or boron to increase electrical resistance, other dopants within the scope of the embodiments. -11 - 201232620 Referring next to Figures 2a-2c, a cross section of a transistor is illustrated in accordance with three embodiments. 2a illustrates the semiconductor body 110 as having a base portion 111 and a fin portion 112, wherein the base portion 112 is between the substrate 102 and the isolation region 104, and wherein the substrate has a substantially flat upper surface 103. However, the embodiments are not so limited. For example, as shown in Figures 2b and 2c, respectively, the semiconductor body 1 1 〇 can be composed of fins 1 1 2 without extending over the substrate portion above the substrate 102 (also shown in Figure 1, Figure 2b) It is a cross section of Figure 1 along the line ΙΙ-ΙΙ. According to one embodiment, the substrate 102 can have a substantially planar upper surface 103, as shown in FIG. 2b, or in another option, the substrate 102 can include a substrate base portion 105 and a substrate fin extending from the substrate base portion 105. In the portion 107, the fin portion 112 of the semiconductor body 110 extends above the substrate fin portion 107. Referring next to FIG. 3, a cross section is illustrated along line III-III of FIG. 2b, and a first ILD (interlayer dielectric) layer 150, source and drain contacts 152 and 154, and a gate contact are illustrated. 156. Although the source region 140 and the drain region 140 are also illustrated, their positions can of course be exchanged as shown. In the illustrated embodiment, the tip regions 158 and 160 and the spacers 162 and 164 are also illustrated. According to an embodiment, the tip end region can be set as described above with respect to the source region 140 and the drain region M2. The spacers can be placed in a manner well known to those skilled in the art. In this manner, the device according to the embodiment is incorporated as part of the integrated circuit in a manner well known. The device can be, for example, a PMOS device. Referring next to Figures 4, 5a and 5b, a method of manufacturing the apparatus according to the embodiment will be explained. Method embodiments include providing a strained film that is then used as a basis for forming a strained fin from -12-$201232620, such as, for example, via etching, etc., but other ways of providing fins from the strained film are implemented Within the scope of the example. As seen in Figure 1, the method embodiment in block 400 includes providing a substrate comprising a first material such as sand. In block 402, the substrate can be configured to include a first material. In block 404, a biaxial strain film can be disposed on the substrate ′ and in block 406, the uniaxial fin portion can be formed from the biaxial strain film by etching the biaxial strain film. With particular reference to Figures 5a and 5b, an illustrative method embodiment will now be described. Referring first to Figure 5a, a tantalum substrate 502, and a biaxially strained SiGe film 550 grown thereon are first disposed. As noted above, the SiGe film can be disposed using CVD, PVD, MBE, or any other suitable thin film deposition process. The thickness of the SiGe film 550 can be formed, for example, from about 25 nm to about 40 nm. The higher percentage of germanium in thicker SiGe films and/or SiGe typically creates unwanted dislocations in the crystal, which may cause strain in the fins to be lower, while thinner SiGe may have the opposite effect. In general, care can be taken to avoid the difference while not excessively limiting the thickness of the SiGe film. As seen in Figure 5b, the SiGe film 550 can be lithographically and etched' to produce the fins 51l shown. Preferably, dry etching can be used to provide fins such as, for example, for providing shallow trench isolation regions in a conventional manner. The etching of the SiGe film 55A according to the illustrated embodiment produces a sustain stress in the direction CF of the current flow (i.e., 'in the longitudinal direction of the fins) while substantially releasing the stress in a direction perpendicular to the flow of the current. ' -13- 201232620 A direction such as PCF shown in Figure 5b. The percentage of strain sensing elements can be selected to optimize transistor performance as is known to those skilled in the art. For example, where the strain sensing element comprises germanium, the material of the fins may be between about 30% and about 70% germanium, and between about 40% and about 50% germanium. Optionally, the material of the fins may have a constant percentage of strain sensing elements throughout its volume extending between the substrate and the gate dielectric. For example, referring to Figures 2a-2c, the portion 115 of the fin disposed between the substrate 102 and the gate dielectric 134 (i.e., the portion defining the channel 135 as shown in Figures 1 and 2a-2c) is throughout There may be a constant percentage of enthalpy in volume. Moreover, this constant percentage can be applied to the entire volume throughout the fin. Referring to Table 1 below, a comparison of measured and simulated strain averaging before and after etching a Si Ge film containing 40% bismuth is provided. The average of the average biaxial strain measured by Raman (from Raman) is from the average biaxial strain in the simulated SiGe before the average etching - 1.60% -1.55% after etching -0.85% -0.80% The average measured in Table 1 The average is obtained by applying the actual and simulated Raman spectra to the SiGe film. The average averaging is obtained by using Raman spectroscopy and finite element-based stress simulation for SiGe films. As indicated by the first row of Table 1, the strain in the SiGe film is smaller after etching than before etching. The second row of 201232620 of Table 1 for the simulation of the biaxial strained SiGe film is strongly correlated with the enthalpy in the row, and implies that the biaxial strain is released to the uniaxial post etch. Referring next to Figure 6a, a plot of the simulated average stress in the channel along the direction of current flow versus the percentage of enthalpy in the SiGe (矽锗) fin is provided. As is clear from Fig. 6a, the stress in the crucible in the fin along the direction of current flow increases as the percentage of germanium in the SiGe fin material increases. Thus, according to some embodiments, different desired stresses can be obtained by increasing the percentage of germanium in the film, or by reducing the width of the SiGe film, or both. For example, one way to increase the percentage of germanium in a SiGe film such as SiGe film 450 of Figure 4a would be to use oxidation to reduce the width of the film. In this way, oxygen in an oxide such as, for example, cerium oxide, will combine with some of the ruthenium in the SiGe film, consuming some of the ruthenium in the SiGe film and making the concentration of ruthenium remaining in the later SiGe higher. And further making the latter SiGe film thinner than before oxidation, in this way producing more strain in the fin. Referring next to Figure 6b, a plot of mobility versus energy band gaps for different percentages of SiGe film and thus different uniaxial stress levels is provided. The circle represents the final uniaxial stress of a different percentage of post-film etching. The illustration shows that various mobility and bandgap can be achieved by carefully designing the stress and Ge percentage of the SiGe film. For example, adding a predetermined percentage of germanium to the source and drain regions and/or using other strain techniques such as gate strain, nitride capping, etc. can be used to modify a given SiGe fin with an initial percentage of germanium. The stress of the channel. The drawings and the above description give examples of embodiments. Those skilled in the art will recognize that one or more of the illustrated components can be combined as a single functional component. Another option is that certain components can be split into multiple functional components. Elements from one embodiment can be added to another embodiment. For example, the order of processing described herein can be changed ' without limitation to the manners set forth herein. Moreover, there is no need to implement the behavior of any of the flowcharts in the order shown; nor do they necessarily perform all the acts. Furthermore, behaviors that do not rely on other behaviors can be performed in parallel with other behaviors. The scope of the embodiments is in no way limited by these specific examples. Many variations, such as structure, size, and material usage, may be made, whether explicitly stated in the specification. The scope of the embodiments is at least broadly as given by the scope of the claims below. BRIEF DESCRIPTION OF THE DRAWINGS In the final part of the specification, the scope of the patent application of the present invention is specifically indicated and clearly indicated. The above and other features of the present invention will be apparent from the appended claims and appended claims. It is to be understood that the appended drawings are not intended to The invention may be more specifically and in detail described by the use of the accompanying drawings in which the advantages of the present invention can be more readily determined, in which: Figure 1 is a perspective view of a plurality of non-planar devices according to one embodiment. Figures 2a-2c are based on three A cross-sectional view of a transistor of a respective embodiment; FIG. 3 is a cross-sectional view showing one embodiment of a top and source/drain regions: -16 - 201232620 FIG. 4 is a flow chart of a method embodiment; 5a and 5b are perspective views of the assembly including the substrate and the strained film thereon; FIG. 6a is a simulated average stress in the channel along the direction of current flow according to an example in the Si Ge (矽锗) fin A plot of the percentage of ruthenium; and Figure 6b is a plot of mobility versus another uniaxial stress level for Si Ge films having different percentages according to mobility. [Main component symbol description] 1 〇〇: transistor 102: substrate 103: upper surface 104: isolation region 105: substrate substrate portion 106: substrate active region 107: substrate fin portion 1 1 0 : semiconductor body 1 1 1 : substrate Part 1 1 2 : Fin 1 1 3 : Device active part 1 1 4 : Top surface 1 1 5 : Part 1 1 6 : Side wall -17- 201232620 1 1 8 : Relative side wall 1 3 2 : Gate 1 3 4 : gate dielectric layer 1 3 5 : site defining channel 1 3 6 : gate electrode 1 4 0 : source region 1 4 2 : drain region 1 5 0 : interlayer dielectric layer 1 5 2 : source contact 154: bungee contact 1 5 6 : gate contact 1 5 8 : tip region 1 6 0 : tip region 1 6 2 : spacer 1 6 4 : spacer 5 02 : 矽 substrate 5 1 2 : fin portion 5 5 0 : Biaxial strain 矽锗 film-18-