TW201338052A - Method for fabricating MOS device - Google Patents

Abstract

A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. A gate stack structure is formed on a substrate. A first spacer is formed at a sidewall of the gate stack structure, and then source and drain extension regions are formed in the substrate beside each sidewall of the gate stack structure. Recesses are formed in the substrate beside the gate stack structure. Semiconductor compound layers are formed in each recess, and source and drain regions are formed in semiconductor compound layers. A second spacer is formed at the sidewall of the gate stack structure. The source and drain regions are formed by in-situ doping during the formation of the semiconductor compound layer instead of performing an ion implantation process after the semiconductor compound layer is formed.

Description

Method for manufacturing MOS semiconductor device

The present invention relates to a method of fabricating a MOS device.

Gold oxide semi-transistors are a basic structure widely used in various semiconductor elements such as memory elements, image sensors, or displays. A typical MOS transistor includes a yttrium oxide dielectric layer, a gate conductive layer, and a heavily doped dopant source/drain contact region. As the line width is reduced, the size of the semiconductor element is reduced, and the typical MOS transistor is reduced in length due to the reduction of the gate width.

As the channel is reduced, mechanical-stress is applied to the channel to effectively change the rate of movement of electrons and holes in the channel. This is a way to increase the operating speed of the transistor. It has been proposed to use materials such as bismuth telluride (SiGe) epitaxy as the main component of the source/deuterium region of the transistor. Taking bismuth telluride as the main component of the source/drain region, compared with the material properties of bismuth, since the ruthenium has a large atomic volume, the channel compressive stress can be applied, so the bismuth telluride is used as the source/汲The main material of the polar region can increase the mobility of the hole (Mobility), thereby improving the performance of the component.

However, in the process of component fabrication, bismuth telluride (SiGe) causes a lattice difference of bismuth due to the subsequent ion implantation process for forming the source and drain regions, so that the stress of the channel is reduced. Affect the performance of components.

The invention provides a method for manufacturing a MOS device, which can reduce the lattice difference of a semiconductor compound through a change in a process, increase the stress effect of a semiconductor compound on a channel, and improve the performance of the device.

The present invention provides a method of fabricating a MOS device, comprising forming a first gate structure on a first active region of a substrate, and then forming a first spacer on a sidewall of the first gate structure. Then, a first source and a drain extension region are respectively formed in the substrate on both sides of the first gate structure. Thereafter, grooves are respectively formed in the substrates on both sides of the first gate structure. Next, a semiconductor compound layer is formed in the above recess. Next, a first source and a drain region are formed in the semiconductor compound layer, and then a second spacer is formed on a sidewall of the first gate structure. The dopants of the first source and drain extension regions and the first source and drain regions are of a first conductivity type, and the first source and drain regions are field doped when forming the semiconductor compound layer After the formation of the semiconductor compound layer, the semiconductor compound layer is not subjected to an ion implantation process.

According to an embodiment of the invention, the first conductivity type comprises a P type.

According to an embodiment of the invention, the semiconductor compound layer comprises bismuth telluride.

According to an embodiment of the invention, the first gate structure is no longer subjected to an ion implantation process on the first gate structure.

According to an embodiment of the invention, the method for fabricating the MOS device further includes forming a mask layer on the substrate, covering the semiconductor compound layer, exposing the upper surface of the first gate structure, and then The mask layer is a mask, and the first ion implantation process is performed on the conductor layer of the first gate structure, and then the mask layer is removed.

According to an embodiment of the present invention, the method for fabricating the MOS device further includes forming a second gate structure on the second active region of the substrate, and then forming the first sidewall on the sidewall of the second gate structure a spacer, and then a second source and drain extension are formed in the substrate on both sides of the second gate structure. Then, forming the second spacer on the sidewall of the second gate structure, and then performing a second ion implantation process to form a second source and the drain in the substrate on both sides of the second gate structure Area. The dopants of the second source and the drain extension region and the second source and drain regions are of a second conductivity type.

According to an embodiment of the invention, the second conductivity type comprises an N-type.

According to an embodiment of the present invention, the method for fabricating the MOS device further includes forming a mask layer on the substrate after forming the second source and the drain region, covering the semiconductor compound layer, and exposing the above The upper surface of the first gate structure, and then the first ion implantation process is performed on the conductor layer of the first gate structure by using the mask layer as a mask, and then the mask layer is removed.

According to an embodiment of the invention, the method for fabricating the MOS device further includes forming a deuterated metal layer on the first source and the drain region, and then forming a dielectric layer on the substrate, and then, A contact window is formed in the dielectric layer.

According to an embodiment of the invention, the method for fabricating the MOS device further includes performing a thermal tempering process before forming the bismuth metal layer.

According to an embodiment of the invention, the first gate structure includes a material layer and a conductor layer, and further includes removing the conductor layer of the first gate structure to form a trench, and then forming a metal in the trench Material layer.

According to an embodiment of the invention, the material layer comprises a layer of high dielectric constant material.

According to an embodiment of the invention, the method for fabricating the MOS device further includes sequentially forming a bottom metal layer, a stop layer, and a work function metal on the material layer in the trench before forming the metal material layer. Floor.

According to an embodiment of the invention, the method for fabricating the MOS device further includes removing the material layer before the conductor layer is removed, exposing the trench to the substrate, and forming a high in the trench Dielectric constant material layer.

According to an embodiment of the invention, the method for fabricating the MOS device further includes sequentially forming a bottom metal layer, a stop layer, and a work function on the high dielectric constant material layer before forming the metal material layer. Metal layer.

The manufacturing method of the MOS device of the present invention can reduce the lattice difference of the semiconductor compound through the change of the process, increase the stress effect of the semiconductor compound on the channel, and improve the performance of the device.

The above described features and advantages of the present invention will be more apparent from the following description.

1A through 1H are schematic cross-sectional views showing a manufacturing process of a MOS device according to a first embodiment of the present invention.

Referring to FIG. 1A, an isolation structure 12 is formed in the substrate 10 to define a first active region 14a and a second active region 14b. The substrate 10 material includes a semiconductor such as germanium. The material of the isolation structure 12 includes an insulating material. The insulating material is, for example, cerium oxide. The method of forming the isolation structure 12 is, for example, a shallow trench isolation structure method.

Next, gate structures 16a and 16b are formed on the first active region 14a and the second active region 14b of the substrate 10, respectively. The gate structures 16a and 16b include a material layer 18, a conductor layer 20, and a cap layer 21, respectively. In one embodiment, the width of the gate structures 16a and 16b is, for example, 24 nm. The material of material layer 18 includes a dielectric layer, a high dielectric constant (K value greater than 4) material or a barrier layer, or a combination thereof. The material of the dielectric layer is, for example, cerium oxide. The high dielectric constant material may be a metal oxide layer such as a rare earth metal oxide layer such as hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO), niobium niobate oxynitride ( Hafnium silicon oxynitride, HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta _{2 )} O ₅ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO ₄ ), or hafnium zirconium oxide (HfZrO), or a combination thereof. The barrier layer is, for example, titanium, tantalum, titanium nitride or tantalum nitride, or a combination thereof. The material of the conductor layer 20 is, for example, a single crystal germanium, an undoped polysilicon, a doped polysilicon, an amorphous germanium, a germanium material, or a combination thereof. The conductor layer 20 can be formed by chemical vapor deposition. If the conductor layer 20 has a dopant, its dopant can be doped in the field during deposition to bring the dopant in the conductor layer 20 to the desired concentration. If the concentration of the dopant of the conductor layer 20 does not meet the requirements, the selective ion implantation process can be performed through a subsequent process to achieve the desired dopant concentration. The thickness of the conductor layer 20 is, for example, 650 angstroms. The material of the cap layer 21 is, for example, tantalum nitride or hafnium oxide, or a combination thereof. The gate structures 16a and 16b may be formed by first forming an insulating material layer, a conductor material layer, and a cap material layer, and then patterning through a photolithography process.

Next, a spacer 24 is formed on the sidewalls of the gate structures 16a and 16b, respectively. The material of the spacers 24 is, for example, tantalum oxide or tantalum nitride or a combination of both. Thereafter, ion implantation processes are respectively performed to form source and drain extension regions 25a and source and drain extension regions 25b in the first active region 14a and the second active region 14b, respectively. In one embodiment, the PMOS device is pre-formed on the first active region 14a, and the dopant in the source and drain extension regions 25a is P-type; the NMOS, source and drain extension regions are predetermined on the second active region 14b. The dopant of 25b is N type. In another embodiment, the first active region 14a is predetermined to form an NMOS device, the dopant in the source and drain extension regions 25a is N-type; the second active region 14b is predetermined to form a PMOS, and the source and the drain are extended. The dopant of the region 25b is P-type. The dopant is P-type such as boron or boron difluoride; the N-type dopant is, for example, phosphorus or arsenic.

Then, a barrier layer 26 is formed on the substrate 10. The material of the barrier layer 26 is, for example, tantalum nitride. Thereafter, a mask layer 28 is formed on the first active region 14a. The material of the mask layer 28 is, for example, a photoresist. After that, the lithography process is performed.

Thereafter, referring to FIG. 1B, the mask layer 28 is used as an etching mask, and an etching process is performed to remove a portion of the barrier layer 26 to form a spacer 30a on the sidewall of the stacking gate 16a on the first active region 14a.

Thereafter, grooves 32 are formed in the substrate 10 on both sides of the spacer 30a. In an embodiment, the depth of the recess 32 is, for example, hundreds of angstroms. The shape of the groove 32 may be diamond-shaped or square, and is not particularly limited. The method of forming the recess 32 may first remove a portion of the substrate 10 in the first active region 14a by dry etching, after which the mask layer 28 is removed, and then the first active region 14a is removed by a wet etching process. Part of the substrate 10.

Then, referring to FIG. 1C, a semiconductor compound layer 33 is formed in each of the grooves 32. The semiconductor compound layer 33 is, for example, a group IV-IV semiconductor compound. The Group IV-IV semiconductor compound may be composed of a first Group IV element and a second Group IV element. The first Group IV element is, for example, ruthenium; the second Group IV element is a non-ruthenium element, such as ruthenium or carbon. That is, the Group IV-IV semiconductor compound is, for example, germanium telluride (SiGe) or tantalum carbide (SiC). In the PMOS device, the material of the semiconductor compound layer 33 is germanium germanium; in the NMOS device, the material of the semiconductor compound layer 33 is tantalum carbide.

In an embodiment, the semiconductor compound layer 33 includes a buffer layer 38, a body layer 34, and a top layer 36. The content of the second group IV element (the amount of cerium or carbon) in the main body layer 34 is higher than the content of the second group IV element of the buffer layer 38 (the amount of cerium or carbon), and the second IV of the buffer layer 38. The content of the group element (containing cerium or carbon content) is higher than the content of the second group IV element of the top layer 36 (containing cerium or carbon). The top layer 36 may also be composed entirely of the first group IV element, that is, the content of the second group IV element (containing cerium or carbon content) may also be zero.

The present invention is field-doped to form the source and drain regions 50a when the semiconductor compound layer 33 is formed. In one embodiment, the PMOS device is predetermined to be formed on the first active region 14a, and the dopant in the source and drain regions 50a is P-type. In another embodiment, the first active region 14a is predetermined to form an NMOS device, and the dopants in the source and drain regions 50a are N-type. The dopant is P-type such as boron or boron difluoride; the N-type dopant is, for example, phosphorus or arsenic. The concentration of the dopant of the buffer layer 38 is zero or lower than the concentration of the dopant of the top layer 36, and the concentration of the dopant of the top layer 36 is lower than the concentration of the dopant in the host layer 34.

In the PMOS device of the 40 nm process, the semiconductor compound layer 33 is germanium germanium. The boron doping amount in the buffer layer 38 is, for example, 0%; the boron doping amount in the bulk layer 34 is, for example, 3 × 10 ²⁰ /cm ² ; and the boron doping amount of the top layer 36 is, for example, 7 × 10 ¹⁹ to 2 × 10 ²⁰ /cm ² .

The buffer layer 38, the main body layer 34 and the top layer 36 may be subjected to an epitaxial growth process in the same reaction chamber by adjusting the ratio between the two gas sources in the reaction gas, for example, the reaction gas of the helium source and the helium source. The ratio between the two sources (or the ratio between the source of the gas and the reaction gas of the carbon source) to form a bismuth telluride (barium carbide) with different cerium content (carbon content), and to carry out on-site mixing during the epitaxial growth process. Miscellaneous to form the source and drain regions 50a.

Thereafter, referring to FIG. 1D, another mask layer 39 is formed on the first active region 14a. Thereafter, the barrier layer 26 on the second active region 14b is etched to form the spacers 30b on the second active region 14b, after which the mask layer 39 is removed, as shown in FIG. 1E.

Thereafter, referring to FIG. 1E, after the mask layer 39 is removed, the spacer material layer 40 and the spacer material layer 42 are formed on the substrate 10. The material of the spacer material layer 40 is different from the material of the spacer material layer 42. In one embodiment, the material of the spacer material layer 40 is, for example, ruthenium oxide, and the material of the spacer material layer 42 is, for example, tantalum nitride.

Thereafter, referring to FIG. 1F, the spacer material layer 40 and the spacer material layer 42 are etched to form the spacers 44 and the spacers 46, respectively. Thereafter, an ion implantation process is performed to implant dopants into the substrate 10 of the second active region 14b to form source and drain regions 50b. In one embodiment, the PMOS device is pre-formed on the first active region 14a, the dopant in the source and drain regions 50a is P-type, and the NMOS, source and drain regions 50b are predetermined on the second active region 14b. The dopant is N type. In another embodiment, the NMOS device is predetermined on the first active region 14a, the dopant in the source and drain regions 50a is N-type, and the PMOS, source and drain regions 50b are predetermined on the second active region 14b. The dopant is P type. The dopant is P-type such as boron or boron difluoride; the N-type dopant is, for example, phosphorus or arsenic.

Since the source and drain regions 50a of the first active region 14a are formed by field doping when the semiconductor compound layer 33 is formed, and the on-site doping, the required concentration of the source and drain regions 50a has been provided. . Therefore, it is no longer necessary to perform the pre-amorphous implantation (PAI) process and the ion implantation process for forming the source and drain regions 50a of the semiconductor compound layer 33 after the formation of the semiconductor compound layer 33.

Thereafter, in an embodiment, if the concentration of the dopant of the conductor layer 20 is not satisfactory, the dopant may be selectively implanted in the conductor layer 20. The method of selectively implanting the dopant in the conductor layer 20 may first remove the cap layer 21 to expose the conductor layer 20. Thereafter, a mask layer 56 is formed on the substrate 10, and the opening 58 of the mask layer 56 exposes the conductor layer 20 of the gate structure 16a of the first active region 14a. Mask layer 56 can be photoresist or other suitable material. Thereafter, an ion implantation process 60 is performed to implant dopants into the conductor layer 20. Thereafter, the mask layer 56 is removed, as shown in FIG.

After that, please refer to FIG. 1G to perform a thermal tempering process. The thermal tempering process can employ either rapid thermal tempering (RTA) or laser-spike annealing (LSA) or a combination of the two. Then, a metal layer 52 is formed on the substrate 10, and the material of the metal layer 52 includes a heat resistant metal such as nickel, titanium, tungsten, cobalt, platinum or palladium. The method of forming the metal layer 52 is, for example, a sputtering method.

Thereafter, referring to FIG. 1H, a heating process is performed to carry out a deuteration reaction, and the metal layer 52 is reacted with germanium in the substrate 10 and germanium in the conductor layer 20 to form deuterated metal layers 54 and 55. The materials of the deuterated metal layers 54 and 55 are, for example, nickel telluride, titanium telluride, tungsten telluride, cobalt telluride, platinum telluride or palladium telluride. In another embodiment (not shown), the conductor layer 20 has a cap layer 21 thereon. When the deuteration reaction is performed, the metal layer 52 does not contact and react with the conductor layer 20 under the cap layer 21, and thus cannot be formed. The metal layer 55 is deuterated.

Thereafter, an etch stop layer 61 and a dielectric layer 62 are formed on the substrate 10. The material of the etch stop layer 61 is different from the material of the dielectric layer 62, such as tantalum nitride, and the formation method is, for example, chemical vapor deposition. The material of the dielectric layer 62 is, for example, ruthenium oxide, a low dielectric constant material, an ultra-low dielectric constant material, an undoped glass or any combination thereof, and the formation method is, for example, a chemical vapor deposition method.

Contact windows 64a and 64b are then formed in dielectric layer 62 and etch stop layer 61. The contact window 64 is formed by, for example, first forming a contact opening in the dielectric layer 62 by lithography and etching, and then filling the contact opening into the conductor layer. The conductor layer can be doped polysilicon or tungsten. After that, the back-end process is performed.

The above-described deuterated metal layer 54 is formed before the dielectric layer 62 is formed. However, the invention is not limited thereto. The deuterated metal layer 54 may also be formed by the above-described process method after the contact opening in the dielectric layer 62 is formed and before the conductor layer has been filled.

2A-2B are schematic cross-sectional views showing a manufacturing process of a MOS device according to a second embodiment of the present invention.

Referring to FIGS. 1D and 1E, in the above embodiment, before forming the spacer material layer 40, the sidewalls of the conductor layer 20 on the first active region 14a form the spacers 24 and the spacers 30a, and the second active regions 14b. The sidewalls of the conductor layer 20 form a spacer 24 and a spacer 30b. However, the present invention is not limited thereto. In another embodiment, referring to FIG. 2A, before forming the spacer material layer 40, the sidewalls of the conductor layer 20 on the first active region 14a and the second active region 14b are also It is possible to form only the spacers 24 without forming the spacers 30a and 30b. After the formation of the structure shown in FIG. 1C, the mask layer 39 of FIG. 1D is not formed according to the first embodiment described above, and the first active region 14a is simultaneously removed by a wet etching process (for example, using phosphoric acid). A spacer 30a has been formed thereon and a barrier layer 26 overlying the second active region 14b. Further, if the material of the cap layer 21 is the same as that of the spacers 30a and the barrier layer 26, some or all of the cap layer 21 may be removed by the way of the wet etching process, as shown in Fig. 2A. Thereafter, the subsequent process is carried out in accordance with the above method, and the resulting structure is as shown in FIG. 2B.

3A-3B are schematic cross-sectional views showing a manufacturing process of a MOS device according to a third embodiment of the present invention. For the sake of clarity, only the oxynitride semiconductor element 16a of the first active region 14a of the substrate 10 will be shown in FIGS. 3A-3B.

Referring to FIG. 3B, the gate structures 16a and 16b may also include a material layer 18 and a metal material layer 80. The material layer 18 is a high-k dielectric layer; the material of the metal material layer 80 is, for example, a titanium aluminum alloy. The method of forming the MOS device can be performed to form the dielectric layer 62 in the manner of the first embodiment described above, but it is not necessary to remove the cap layer 21 (Fig. 3A) before performing the deuteration process. Thereafter, referring to FIG. 3B, a chemical mechanical planarization or etch back process is performed first, and a portion of the dielectric layer 62 and the etch stop layer 61 are removed to expose the cap layer 21 above the conductor layer 20, and then removed. The cap layer 21 and the conductor layer 20 form a trench 66. Then, the trench 66 is filled with a metal material layer 80, and then the metal material layer 80 outside the trench 66 is removed by a chemical mechanical polishing process. In one embodiment, the bottom metal layer 72, the stop layer 74, and the work function metal layer 76 may be formed on the high-k dielectric layer of the material layer 18 prior to filling the metal material layer 80. The material of the bottom metal layer 72 is, for example, titanium nitride. The material of the stop layer 74 is, for example, tantalum nitride. The material of the work function metal layer 76 is, for example, titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (tungsten carbide). Tungsten carbide, WC), or aluminum titanium nitride (TiAlN), but is not limited thereto.

The first to third embodiments described above can be integrated with a high-k first high dielectric dielectric layer (high-k first) process, that is, the material layer 18 is a high-k dielectric layer which is attached to the conductor layer 20. Formed before formation. However, the present invention is not limited thereto, and the present invention can also be integrated with a post-high dielectric constant high-k last process.

4 is a cross-sectional view showing a MOS device in accordance with a fourth embodiment of the present invention.

Referring to FIG. 4, in another embodiment, the gate structures 16a and 16b include a high-k dielectric layer 78 and a metal material layer 80. The method of forming the MOS device may first form the material layer 18 and the conductor layer 20 in accordance with the method of the third embodiment corresponding to FIG. 3A, but the material layer 18 is not a dielectric layer having a high-k dielectric layer (for example, It is a ruthenium dioxide layer), and subsequent processes are continued until the dielectric layer 62 is formed. Then, referring to FIG. 4, a chemical mechanical planarization or etch-etching process removes portions of the dielectric layer 62 and the etch stop layer 61, and then the cap layer 21 is removed. Then, the conductor layer 20 is removed to form the trench 66, and thereafter, before the metal material layer 80, the bottom metal layer 72, the stop layer 74, and the work function metal layer 76 are formed, the material layer 18 at the bottom of the trench 66 is removed. A high-k dielectric layer 78 is formed. Thereafter, a bottom metal layer 72, a stop layer 74, a work function metal layer 76, and a metal material layer 80 are formed in the trench 66 according to the method described in the third embodiment, and the formed structure is as shown in FIG.

In summary, in the present invention, since the source and drain regions of the first active region are formed by field doping when forming the semiconductor compound layer and have a desired concentration, there is no need to The semiconductor compound layer is implanted into the first conductive type dopant ion implantation process, and the prior amorphous implantation process is not required. Therefore, the crystal lattice of the semiconductor compound layer is not damaged by the ion implantation process or the pre-amorphous implantation process, and the phenomenon of the semiconductor compound layer difference can be reduced, so that the stress of the semiconductor compound layer to the channel can be increased. When verified, the present invention can increase the stress of the semiconductor compound layer on the channel, and improve the efficiency of the component by more than 6.3%.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Base

12. . . Isolation structure

14a, 14b. . . Active zone

16a, 16b. . . Gate structure

18. . . Material layer

20. . . Conductor layer

twenty one. . . Roof layer

twenty two. . . Hard mask layer

24, 30a, 30b, 44, 46. . . Clearance wall

25a, 25b. . . Source and drain extension

26. . . Barrier layer

28, 39. . . Mask layer

32. . . Groove

33. . . Semiconductor compound layer

34. . . Main layer

36. . . Top

38. . . The buffer layer

40, 42. . . Gap material layer

50a, 50b. . . Source and bungee area

52. . . Metal layer

54. . . Deuterated metal layer

56. . . Mask layer

58. . . Opening

60. . . Ion implantation process

61. . . Etch stop layer

62. . . Dielectric layer

64a, 64b. . . Contact window

66. . . ditch

72. . . Bottom metal layer

74. . . Stop layer

76. . . Work function metal layer

78. . . High dielectric constant dielectric layer

80. . . Metal material layer

1A through 1H are schematic cross-sectional views showing a manufacturing process of a MOS device according to a first embodiment of the present invention.

2A-2B are schematic cross-sectional views showing a manufacturing process of a MOS device according to a second embodiment of the present invention.

3A-3B are schematic cross-sectional views showing a manufacturing process of a MOS device according to a third embodiment of the present invention.

4 is a cross-sectional view showing a MOS device in accordance with a fourth embodiment of the present invention.

10. . . Base

12. . . Isolation structure

14a, 14b. . . Active zone

16a, 16b. . . Gate structure

18. . . Material layer

20. . . Conductor layer

twenty one. . . Roof layer

24, 30a. . . Clearance wall

25a, 25b. . . Source and drain extension

26. . . Barrier layer

32. . . Groove

33. . . Semiconductor compound layer

34. . . Main layer

36. . . Top

38. . . The buffer layer

50a. . . Source and bungee area

Claims (15)

A method of fabricating a MOS device, comprising: forming a first gate structure on a first active region of a substrate; forming a first spacer on a sidewall of the first gate structure; Forming a first source and a drain extension in the substrate on each side of the pole structure; forming a recess in the substrate on each side of the first gate structure; forming a semiconductor compound in the recesses a first source and a drain region are formed in the semiconductor compound layer; and a second spacer is formed on a sidewall of the first gate structure, wherein the first source and the drain extension region and the The dopant of the first source and the drain region is of a first conductivity type, and the first source and the drain region are doped in situ when the semiconductor compound layer is formed, and after the semiconductor compound layer is formed, The semiconductor compound layer is not subjected to an ion implantation process. The method of manufacturing a MOS device according to claim 1, wherein the first conductivity type comprises a P type. The method of producing a MOS device according to claim 2, wherein the semiconductor compound layer comprises bismuth telluride. The method of fabricating a MOS device according to claim 1, wherein the first gate structure is not subjected to an ion implantation process after the first gate structure. The method for fabricating a MOS device according to claim 1, further comprising: forming a mask layer on the substrate, covering the semiconductor compound layer, exposing the upper surface of the first gate structure; The mask layer is a mask, a first ion implantation process is performed on a conductor layer of the first gate structure; and the mask layer is removed. The method for manufacturing a MOS device according to claim 1, further comprising: forming a second gate structure on a second active region of the substrate; forming the sidewall of the second gate structure a first spacer; a second source and a drain extension are respectively formed in the substrate on both sides of the second gate structure; the second spacer is formed on a sidewall of the second gate structure; and performing a a second ion implantation process to form a second source and drain region in the substrate on both sides of the second gate structure, wherein the second source and the drain extension region and the second source The dopant with the drain region is of the second conductivity type. The method of manufacturing a MOS device according to claim 6, wherein the second conductivity type comprises an N type. The method for fabricating a MOS device according to claim 6, further comprising: forming a mask layer on the substrate to cover the semiconductor compound layer, and exposing after forming the second source and the drain region And forming a first ion implantation process on a conductor layer of the first gate structure; and removing the mask layer. The method for fabricating a MOS device according to claim 1, further comprising: forming a deuterated metal layer on the first source and the drain region; forming a dielectric layer on the substrate; A contact window is formed in the dielectric layer. The method for fabricating a MOS device according to claim 9, further comprising performing a thermal tempering process before forming the bismuth metal layer. The method of fabricating a MOS device according to claim 1, wherein the first gate structure comprises a material layer and a conductor layer, and further comprising: removing the conductor layer of the first gate structure Forming a trench; and forming a layer of metallic material in the trench. The method of fabricating a MOS device according to claim 11, wherein the material layer comprises a high dielectric constant material layer. The method for fabricating a MOS device according to claim 12, further comprising sequentially forming a bottom metal layer, a stop layer, and a layer on the material layer in the trench before forming the metal material layer. Work function metal layer. The method for fabricating a MOS device according to claim 11, further comprising: removing the material layer to expose the trench before exposing the conductor layer; and forming a trench in the trench; High dielectric constant material layer. The method for fabricating a MOS device according to claim 14, further comprising sequentially forming a bottom metal layer, a stop layer, and a layer on the high dielectric constant material layer before forming the metal material layer. Work function metal layer.