TW200525736A - Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making - Google Patents

Abstract

A memory device (100, 600) including a substrate (120, 220, 320, 420, 620, 720), and multiple self-aligned nano-rectifying elements (102, 202, 302, 402) disposed over the substrate. Each nano-rectifying element has multiple first electrode lines (132, 232, 332, 432, 632, 732), and multiple device structures (136, 236, 336, 436, 636) disposed on the multiple first electrode lines forming the multiple self-aligned nano-rectifying elements. Each device structure has at least one lateral dimension less than about 75 nanometers. The memory device also includes multiple nano-storage structures (104, 204, 304, 404) disposed over the device structures and self-aligned in at least one direction with the device structures. In addition, the memory device includes multiple second electrode lines (152, 252, 352, 452 ,652) disposed over, electrically coupled to, and self-aligned to the nano-storage structures, whereby a memory device is formed.

Description

200525736 IX. Description of the invention: [Technical field of inventors' households 3 Field of the invention The present invention relates to a memory device including a majority of self-calibrated nano rectifier elements and a method for manufacturing the same. [PRIOR ART 3 BACKGROUND OF THE INVENTION 10 15 In the past few years, the need for cheaper and lighter portable electronic devices has led to the manufacture of durable, lighter, low-cost circuits, including high-density memory chips. increase. Solid-state memory elements typically have nanosecond-level reads, writes, and reads, and the storage capacity has reached one billion (G) bytes. Conversely, a large number of storage devices usually have rotating media and can store hundreds of capacities, but they only have read and write speeds on the order of milliseconds. The capacity of the storage system in Xihui Valley is typically limited by the need to use movable, movable, or% turn components, which is a slower method than circuit technology. In addition, it is another problem to open the main port and Λ degree. In order to reduce the reading and writing time, these electronic conversion components will be used at the highest speed as possible. And, if it is also used in portable equipment, the impact resistance of the system is typical and limited. Power consumption, overall weight and size, and cost are also restrictions on wealth. Structure j > Shi Xiji 5 Ji Yi device will contain a complex structure using many layers. Therefore, the material layer must be deposited and defined to make the desired structure of the layer. Miscellaneous = will make the semiconductor device higher. the cost of. In addition, these complex structures will cause the number of logic cells per unit area of the financial substrate 20 200525736, resulting in a reduction in the data storage density of a given wafer size. ° In the past 30 years, the capacity of microelectronic components has been almost constant. The addition has resulted in unprecedented advances in computing, messaging, and signal processing capabilities. And 'This increase in complexity has reduced the fine-grained size of integrated circuit components, which typically follows Moore's Law ("More, s LW. However, the fine-grained size of integrated circuits continues to shrink, It has gradually become more difficult in the nanometer range, and may be close to the limit, because of physical and economic reasons. 10 15 The conventional methods to solve the problem of building nanometer-level components are typically divided into two categories ... Called a new patterning technology, another uses a new material with nanometer size ^ Patterning technologies include projection systems that use radiation, and direct writing or scanning probes using particle beams. Some newer ^ higher resolution Refractive projection systems require responsible radiation sources, such as synchrotrons, and other direct-facing, mysterious direct writing systems that typically require-a series of processes when individually writing to each structure-which differs from the use of a projection system—one exposure. Many structures. &Amp; 'The direct writing system will have much lower capacity compared to the projection system' and will increase the manufacturing complexity and / or cost. Recently, semiconductor materials and nanometer scale materials have been used. The combination is made in the nano-pieces. However, after the nano-grade materials are made, they are usually arranged arbitrarily, for example, the _ ends are randomly fixed to a substrate, or both ends are not μ. This Randomness and the difficulty of actually manipulating nano-components will pose a great challenge to the manufacture of repeatable and real nano-components. If these problems continue, the use of electronic 20 200525736 devices in the past few decades will be even greater. The continued growth of cheap, higher speed, higher density, and lower power integrated circuits will not be achieved. [Summary of the Invention] Summary of the Invention 5 The present invention is a memory device, including: a substrate; most self-calibrated A nano rectifier element has: a plurality of first electrode lines provided on the substrate; a plurality of device structures are provided on the first electrode lines to form the majority of the self-calibrated nano rectifier components described above, and each device structure The object has at least one side with a size of less than 75 nanometers; most of the nanometer storage structures are provided on 10 such device structures and are self-aligned with them in at least one direction; and most The second electrode line is arranged on the nano storage structures, and is electrically connected to the nano storage structure and self-aligned to form a memory device. The present invention is also a memory device including: a substrate; A wire is arranged on the substrate in parallel with each other, the rectifying device will automatically align with the wires, and the rectifying device has at least one side with a size less than 75 nm; a device can store a data bit in Among the storage elements, they are overlaid on the first set of wires and aligned with the rectifying device by themselves; and a device can electrically address the storage elements, wherein each storage element is aligned with the electrical addressing device by itself, and A logic cell of a memory structure will be formed at each crossing point 20 of the electrical addressing device and the first group of wires. The present invention is also a method for manufacturing a crossbar device, comprising: nano-printing a device structure layer The first nano printed layer on the device, the device structure layer is provided on a first addressable layer, and the first addressable layer is provided on a substrate; the first addressable layer and the device structure layer Into many self-calibrating 20 0525736 nano rectifier element, each rectifier element has at least-the side dimension is less than 2 nanometers-printed on a conductive layer or a storage medium layer, the second storage medium layer is provided on the nanometers On the rectifier element, and the nanometer storage structure self-calibrated by 10%, 5 at least-the side dimension is less than 75 nanometers. "The structure has a simple illustration. Figure 13 is a perspective view of the memory device of the embodiment of the present invention. = The figure is a wearing view of one element of the memory device of Figure U. 10 Sectional view of the invention-a feasible embodiment of the A cross-sectional view of one element of the memory device is a cross-sectional view of the component of the present invention—a feasible embodiment of the memory device—the fourth figure of the device is a _ ^ 15 cross-sectional view. Figure 5. A manufacturing method for manufacturing a memory device according to an embodiment of the present invention. Figure 6 is a cross-sectional view of a manufacturing process for manufacturing a different embodiment of the present invention using a core M. Figure 20 is a sectional view of a manufacturing process for manufacturing an embodiment of the present invention. Interpretation of different manufacturing processes [implementation method] Detailed description of the preferred embodiment The method of self-calibration of the nanometer-level junction size of the wiring is a method of self-calibration. The present invention also provides a method that can be used to manufacture a variety of memories 200525736

Recall the device; ίτ method! "Memory I ^ ^ Set 3 has a self-aligning rectifying interface provided on the cloth towel, which will be exchanged with storage media components, which can usually be seen in most of the interfering devices. Coupling or latent communication 5 10 15 The storage medium element can be self-aligned to the rectifying interface. Mo Ming also deflects materials and doping degrees to optimize for each layer, and provides a method to optimize the The performance of each layer or structure. Many types of rectifying junctions, such as pn: polar body: polar body, Schottky-polar body, metal / insulator / metal rectification structure, etc., can use the method of the present invention. In addition, 'shirt types' can be stored or cut, such as organic or polymer charge absorbing layers, phase change layers, ferroelectric layers, reversible metal wire layers, and molecular monolayers. Examples of memory or switching layers. Please understand that these drawings are not actual proportions. Also, different parts of these active components are drawn in accordance with each other. A certain mosquito inch will be compared with other sizes to enlarge it, so as to provide more convenience for the invention. Clearly illustrated and understood. In addition, although some embodiments are shown in two dimensions Display, so that different areas have depth and width, but it should be clearly understood that these areas are only a diagram of a part of the crack, and the device is actually a three-dimensional structure. Therefore, these areas should be made When completed in an actual position, it will have three-dimensional dimensions, including length, width, depth, etc. The crossbar memory structure according to an embodiment of the present invention is a three-dimensional illustration in Figure 1a. An electrode or an addressable line 132 is arranged on the substrate 120 and is parallel to each other. A device structure 136 is provided on the first addressable line 132. The device structure 136 and the first electrode line 132 are A self-aligned nano-level rectifying element 102 is formed. The first electrode line 132 and the device structure 136 200525736 have a line width 131 of less than 75 nanometers (nm). In addition, a switching line 142 and the like are provided on the device structure 136. And parallel to each other and perpendicular to the first electrode line 132, etc. Finally, the second electrode line 152 will be laid on and electrically connected to the switching line 142. The line width 151 of the second electrode line 152 and the switching line 142 is less than 75 nm To form a self-aligned 5nm nanometer storage structure 104. Although the first addressable line 132 'switching line 142 and the second electrode line 152 in the figure 1a are shown as straight lines and each have a fixed width, it should be understood that these straight lines are changing in implementation. The examples may also have different curve shapes and variable widths. Moreover, in a variant embodiment, the lines can also intersect at an angle other than 90 ° as shown. 10 A first electrode line Logic cells 101, etc. will be formed at each intersection with a second electrode line. In each cell, the device structure 136 will form a surface with the first electrode line and the second electrode line at the intersection, etc. The ranges are coincident and coplanar. In a feasible embodiment, the second electrode line 152 is electrically connected and provided on a switching element (not shown), the switching element has a line width approximately the same as that of the second electrode line 152, And the length of an element is substantially the same as the width of the first electrode line 132. The crossbar memory structure shown in Figs. 1 and 2 can form a diode by self-alignment to connect a switching element directly provided at the intersection of each electrode line. These self-calibrating diodes can greatly reduce or eliminate the problem of latent paths or collusion. They are usually programmable gate arrays or programmable logic arrays that can be found in all large fields. As shown in the cross-sectional view in FIG. 1b, each logic cell includes a device structure electrically connected to the first electrode line. The interface 138 is formed between the first electrode line 132 and the device structure 136 of the logic cell 101, and has an area smaller than 5625 square nanometers. The nano-rectifying element 102 of the cell 101 can be made of a variety of 200525736, etc.), such as semiconductor junctions (such as pn, p-i_n, or npnp junctions, or bulk junctions (such as Schottky diodes), and metal. /insulation

== Structure, metal / insulator / metal structure, and organic or polymer rectifier structure. In addition, the female, P 5 10 15 -D cell also includes a switching line electrically connected to a first electrode g% formed between the switching between the city line 142 and the device structure Mb. The interface 148 has a diameter of less than 5625 squared. Nano storage structure 104 can be made of various storage materials, such as organic or polymer charge absorption layers, phase change layers, ferroelectric layers, penetrating layers, electromechanical layers, delamination layers, and wire formation (anti-fuse). Layers, magnetic layers (MRAR), and molecular monolayers. The substrate 120 may be any suitable material on which rectifying and switching structures can be formed. Examples of materials include various glasses; ceramics such as oxides, nitrides, carbides, and sapphire; semiconductors such as silicon, gallium arsenide, indium, and germanium; and various polymers such as polyimide , Polyether fluorene, polyetherimide, polyethylene naphthalene, polyethylene terephthalate, and polycarbonate, to name just a few examples of many available materials. Therefore, the present invention is not limited to such devices made of Shixi semiconductor materials, but should include the use of one or more available semiconductor materials and conventional techniques in the field, such as the use of overlays on glass substrates. Devices made of polycrystalline silicon thin film transistor (TFT) technology. In addition, the substrate 120 is not limited to a typical wafer size, 20 and may include processing a polymer sheet or film or a glass substrate, such as a single sheet processed in a form and size different from a conventional wafer or substrate. Wafer or substrate. The actual substrate material used will depend on various factors, such as the maximum processing temperature used, the environment to which the memory device will be subjected, and various components such as the specific rectification structure, switching wires, and electrodes used. 200525736 A feasible embodiment of the present invention using a Schottky barrier diode structure is shown in the sectional view of FIG. 2. In this embodiment, the first addressable line 232 and the clothing structure 236 will form a Schottky barrier rectifying contact at the rectifying interface of the logic cell. The first addressable line 232 and the device structure 236 form a self-aligning rectifying element 202, which has a line width (similar to the line width 131 in FIG. 1a) along the direction of the first electrode line 232 of less than about 75 nm. In addition, each logic cell 70201 includes a switching line 242, and a second electrode line 252 covers the 4 switching line 242. The switching line 242 and the second electrode line 252 are horizontal to each other and orthogonal to the first electrode line 232, similar to that shown in FIG. The 10 first electrode lines 252 and the tangent lines 242 have a line width 251 of less than 75 nm, and form a self-aligned nanometer storage structure 204. In addition, the switching line 242 and the device structure 236 will form a switching interface 248, which can automatically calibrate the structure 236 to the switching line 242 along the direction of the first electrode line 232, and make the structure 236 / σ first electrode The direction of the line 252 is self-aligned to the second electrode line M]. The area of the 15-switching surface 248 is less than 5625 square nanometers. The combination of the self-aligned nano-storage structure 204 of the logic cell 201 and the self-calibrated rectifier element 202. , The device structure 236 can be self-aligned in two mutually perpendicular directions. The substrate 220 in this example is a semiconductor substrate, such as a silicon, germanium, or gallium wafer. To electrically isolate the first electrode line 232 from the doped substrate, an optional dielectric layer 226 is provided as shown in FIG. 2. For example, the substrate 22 may be a lightly doped silicon wafer, and the dielectric layer 226 is a silicon dioxide layer. The first polar line 232 can be a metal, such as magnesium, antimony, aluminum, silver, copper, nickel, pentad, or scuttle, and form a reasonable barrier wall 12 200525736 on the surface of the dioxide, and the device The structure 236 may be a lightly doped n-type polycrystalline silicon or amorphous silicon layer, and the Schottky barrier diode is formed on the rectifying interface 238. In a variant embodiment, a lightly doped p-type layer may be provided on a metal such as gold or platinum silicide, and also forms a Schottky barrier. In still other embodiments, the self-calibrating rectifying element 202 may include a ρ + or η + type epitaxial layer provided on an intrinsic single crystal silicon layer (not shown) to form the addressable line 232. Another lightly doped epitaxial layer, or a layer with a graded doping level and ending on a lightly doped surface, can also be fabricated on the heavily doped layer (not shown). In this embodiment, the device structure 236 may include a thin layer of appropriate 10 metal or metal silicide to form the Schottky barrier contact. In embodiments using a non-conductive substrate, such as a glass, ceramic or polymer substrate, the dielectric layer may be omitted if necessary. For example, when using a glass or polysilicon substrate, the addressable line 232 can be made by directly depositing or making on a base spoon, such as a surface, and the device structure 236 can be adapted to the field. A type of dopant, such as a type 11 dopant, is provided directly on the addressable line 232. Another example of the present invention-a feasible example using an epitaxial semiconductor diode junction is shown in a cross section & I-crystalline film will be used to cause various moon beans to see 322, 20

Lai Luocheng. *. , 4, and the like, and are set using a conventional semiconductor process. The thin addressable layer 332 contains a dopant of the first polarity and has one of the following characteristics: two :: the skin is provided on the substrate 320 and the device structure and the size of the device and ^ And concentration depend on each element, such as the μ case that will be used. The structure I is a polar impurity, which is opposite to that of the first electrode layer 332. In this embodiment, the rectifying interface 338 is formed between the p-type epitaxial layer 323 and the n-type epitaxial layer 324 of the logic cell 301. In this example, the nano rectifier element 302 also includes an optional η + type epitaxial layer 327, which can be used to provide a better electrical connection to the storage medium line 342, which depends on the storage line 342 5 material. In this example, the substrate 320 is a conventional silicon semiconductor wafer, and a dielectric layer 326 of silicon dioxide is disposed between the silicon substrate 320 and the micro-monocrystalline silicon layer 322. In logic cell 301, the first addressable line is made of p-type epitaxial layer 323, and the device structure 336 is formed of 0-type epitaxial layer 324 and optional type epitaxial layer 327. In a variant embodiment, the first 10-addressable line 332 may be made of an n-type material, and the device structure 336 may be made of a P-type material. For example, doped polycrystalline silicon or amorphous silicon may be overlaid on the dielectric layer 326 to form the two layers. Another example may include doped selenium or silicon gallium metal on the dielectric layer 336 as one of the semiconductors used to form the rectifying interface 328. In other embodiments, various other substrate materials as described in the embodiment of FIG. 15 can also be used. In this embodiment, the switching line 342 and the device structure 336 form a switching interface 348 ′, which will automatically align the device structure 3 3 6 in the direction of the second electrode line 3 5 2 with the switching line 342 and the second electrode. Line 352. Each switching line 342 will be parallel to each other and perpendicular to the -addressable line 332, similar to that shown in figure u. The second addressable line 352 in the series 301 in 20 places is overlaid on the switch line, and is also parallel to each other and perpendicular to the first addressable line 332, similar to the figure la. In this embodiment, the two electrodes 352 and the switching line M2 each have a line width 351 smaller than that of Nicong, and they will form a self-calibrating nanometer storage structure 304. The combination of the self-calibrating nanometer storage structure 304 and the self-calibrating integrated flow element 302 enables the device structure 336 to be self-aligned in two mutually perpendicular directions. A possible embodiment of the present invention using a metal / insulator / metal rectifying structure is shown in the sectional view of FIG. In this embodiment, the logic cell 4015 includes a first addressable metal line 432 provided on the substrate 420, and an insulating layer 433 is provided on the first electrode line 432. In this embodiment, the device structure 436 is also a metal layer. In the logic cell 401, the combination of the first addressable metal line 432, the insulating layer 433, and the device structure 436, etc., will form a self-calibrating nanometer rectification structure 402. Modify a line width less than 75nm (similar to the line width 131 shown in Figure la). In addition, the switching line 442 and the device structure 436 in the cell 401 form a switching interface 448, in which the second addressable line 452 is projected on the first addressable line 2 (ie, the switching line 442 and the device) The structure 436) will be aligned with the processing of the intersection of the second addressable line 452 and the first addressable line 432. In the fifteenth embodiment, the switching lines are parallel to each other and perpendicular to the first addressable line, which is similar to that shown in FIG. The second addressable line 452 is disposed on the switching line. In this implementation, these second addressable lines are also parallel to each other and perpendicular to the first addressable line, which is similar to the first la_show. However, in a modified embodiment, the lines may have various curved shapes and variable widths. In addition, in the modified embodiment, these lines can also be crossed at various angles other than 90 degrees. In this example, both the first electrode line 452 and the switching line 442 will have a thin line width 451 of less than 75 to form a self-calibrating nanometer storage structure 404. The combination of the self-calibrating nanometer storage structure and the self-calibrating rectifying element technique will allow the device structure 436 to be automatically calibrated in two mutually perpendicular directions. 15 200525736 FIG. 5 is a flowchart of a method for forming an embodiment of the present invention. Figures 6a to 6n show a process for creating a self-calibrated nano rectifier element and a self-calibrated nano storage structure to make a memory device, which are only shown for a clearer understanding of the invention. Its actual dimensions are not correctly compared to 5 cases, and some feature details will be exaggerated to show these processes more clearly. The rectifying layer manufacturing step 580 is a selective process that can be used to create the first addressable layer 630 and the device structure layer 634, as shown in the cross-sectional view of FIG. 6a. The method used depends on the type of rectifying element and substrate used in the memory device 600. For example, if the rectifying elements are semiconductor junction diodes provided on the semiconductor wafer 10, the addressable layer 630 and the device structure layer 634 can use conventional semiconductor processing equipment, and various epitaxy Technology to make, such as chemical vapor deposition (CVD), including atmospheric pressure (APCVD), low pressure (LPCVD) or plasma enhanced (PECVD) and other methods' atomic layer deposition (ALD) or molecular beam stupid crystals (MBE) are endless. In addition, an amorphous or polycrystalline semiconductor film can also be provided on the substrate 620, and a single crystal or nearly single crystal layer can be formed by a subsequent recrystallization step. The recrystallization step typically uses heat, laser, or electron beam heating of the substrate and the deposition layer to provide the energy to recrystallize the deposited film. In a variant embodiment,-a buried insulator layer may also be used. The doped polycrystalline or amorphous layer 20 can also be used to make the first chirped addressing layer 630 and the device structure layer 634 without having to form an epitaxial layer, depending on the storage material used and the purpose of the crossbar device . For embodiments that use a -metal layer to form a -Schottky barrier contact or a metal / insulator / metal rectification structure, various metal deposition equipment and techniques 200525736 techniques such as PECVD, CVD, metal organic CVD (MOCVD), sputtering Deposition, evaporation, and electrodeposition can also be used. For example, gold, platinum, or Ibano may be sputter deposited on the substrate 620 to form the first addressable layer 630. In another example, the button can be evaporated by an electron beam to form a part of a metal / insulator 5 body / metal rectifier structure. The nano-printing step 582 is used to create a printed layer 66 and emboss a desired structure or feature in the printed layer 660 (see sections 6b to 6dSj). The printed layer can be applied using any suitable technique, such as spin coating, vapor deposition, spray coating, or ink deposition. In one embodiment, the printed layer 66 is a polymethyl 10 acrylate (PMMA) spin-coated on the device structure 634. The printed layer 66 can be any formable material. It can use any material that is flowable or flexible in the first case and more solid and inflexible in the second case. Generally, for polymer printed layers used in a hot stamping process, a low temperature baking process will be used to drive any excess solvent, otherwise it will be applied to the device structure layer at 15 ° C. May remain after 634. Generally, in the embodiment using the "step and flash" method, the transfer layer is first coated on the device structure layer 634, and then a photo-curable layer is formed on the transfer layer. For example, the printed layer 66 may include an organic transfer layer such as HR 100 sold by OLIN Corporation, and the photo-curable layer includes ethylene ^ 20-acrylic acid (3-acryloxypropyl) bis (dimethylamine) Silyl), silane, t-acrylic acid, butanyl, and 2-branzyl-2-methyl-small phenyl-propylammonium]. When curing, it has low survey degree, high curing speed, controlled shrinkage, low evaporation rate, high modulus and good adhesion to the deposited layer, and can be smoothly released from the nano-printer, etc. Is a desired characteristic of the photocurable layer. In another embodiment, the photocurable layer can be made of a material sold by Molecular Imprints under the name s-FIL Monomat AC01. In addition, various other photopolymerizable low viscosity acrylic-based solutions containing an organosilicon compound can also be used to form the printed layer 660. The printed layer 660 is made by embossing using a nanoprinter 5 662 (see Fig. 6c). The nano-printer 662 may be punched or pressed downwardly toward the printed layer 660 when the printed layer is flexible. The printer 662 includes features or structures, etc., and has a shape complementary to the shape required for the printed layer 660. The convex portions 664 and the concave portions 654 and 654, etc., as shown in FIG. 6c, represent the structure required for the nanoprinter 662. Since 10 is complementary, it means that the pattern (see FIG. 6c) formed on the printed layer 660 has a complementary shape whose shape corresponds to the pattern on the nanoprinter 662. That is, the convex portion 664 on the printer will form a concave fine structure 658, and the concave portions 654 and 654 'will form a convex fine structure 656 and 656, respectively, where the concave portion 654' represents being printed at a specific position Changes in structure or feature 15 (ie, if the line width is changed). For example, a print layer made of a photocurable material such as S-FIL Monomat AC01 can be imprinted with a force of 2 Newtons using a printer with a back pressure of 0.25 bar. A photocurable material such as S-FIL Monomat AC01 series can be exposed with a light source, such as -1000w Hg-Xe ultraviolet arc lamp with I-ray radiation (ie, 20 365nm). For illustration purposes only, Figure 6c shows that the nano-printer used can transmit a wavelength of about 250 to 500 nm, so the ultraviolet photon 610 will pass through the nano-printer pressed onto it to light-cure the nano-printer. Meter printed layer 660. In a variant embodiment, the printer 662 can also be removed before the printed layer 660 is photocured. 18 200525736 Another example is heating the PMMA layer above its softening or Lange transition temperature. The specific temperature and pressure used in the hot stamping process will depend on various variables, such as the shape of the fine-grained size to be molded, and the material used for the printed layer. 5 The self-calibrating nano-green flow element manufacturing steps are carried out by the corresponding material layers to make the first-addressable lines and device structures. The nano rectifier component process includes removing the concave fine willows formed during nano printing (see Figure 6c). Removal of the fine texture of the material can be accomplished by wet or dry etching of the specific material of the layer. For example, if it is desired to remove the remaining PMma that forms the recessed fine structure 658 in a hot stamping process, an oxygen reactive ion etching method can be used. In a modified embodiment, if the "Step and flash" manufacturing method of ^^ Monomat material is used, then the reactive layer can be etched with fluorine and the plasma can be etched with oxygen or plasma to remove the transfer layer. . The removal of the recessed fine structure 658 will expose the device structure layer 634 (see figure 15) in the exposed area 657, while the protruding fine structures 656 and 656 'will still retain part of the device structure layer covering other areas 634 on. As for the manufacturing method using other polymer or inorganic printed layers, various wet etching or other reactive ion etching can also be used. An optional hard etch mask manufacturing process can also be used as part of the self-calibrating nano rectifier component process 584 to deposit an optional etch 20 mask. The optional hard etch mask (not shown) is formed by depositing a thin metal or dielectric layer on the nanoprinted layer after the recessed fine structures have been removed. For example, a thin inscription, mesh, rhyme, titanium, or group of layers can be deposited on the nanoprinted surface. In a variant embodiment, the hard etch mask can also be made separately and transferred to the nanoprinted surface. A subsequent high-level 19 200525736 removal method or a remotely selected chemical surname can also be used to remove the protrusions 656 and 656 'of the printed layer (see Fig. 6d), so as to deposit on the protrusions 656 and The hard etch mask material on 656 'can be removed together with the metal deposited in the exposed area 657, and a mask body is reserved for etching the area previously covered by the protruding structure of the 5 temple. The specific selective chemistry | insect engraving it uses will depend on the printing material used and the hard mask material. Tetrahydrobitan (THF) can be used for selective etching of PMMA. Other examples of PMMAs that can be used for selective chemical etching are ethanol-water mixtures, and isopropyl alcohol and methyl ethyl ketone at a ratio of 1 to 25 are used. (: Above. It is best to selectively etch PMMA with acetone in an ultrasonic bath at room temperature, and then rinse with isopropanol. Another example of etching PMMA is dipping with about 2 methane. Minutes, and then shaken and shaken in two gas methane in an ultrasonic cleaning tank. The cleaning procedure of spoon and knife can also be used in addition to the selective pre-etching to further clean the device structure layer 634. The exposed surface area 15 and the surface of the hard etch mask. The optional hard etch mask can be made of any metal or dielectric material, and can provide a suitable method for etching the device structure layer 634 and the first addressable layer 630. Selectivity. Generally, this optional hard etch mask is used in some embodiments, that is, the printed layer may be used in an etching process for etching the device structure layer 634 or the first addressable layer 63. In the case of damage or deterioration, the self-calibrated nanometer rectifier element manufacturing step 584 also includes an etching process for etching the device structure layer 634 and the first addressable layer 63. Bulges 656 and 656, protected by Area, and areas not protected by the optional etch cover described above. The device structure layers 634 and 20 200525736 The first addressable layer 630 can be etched using any wet or dry etch method, or any suitable for specific materials and applications A method of combining doped materials used in an embodiment of a doped semiconductor layer. Depending on the material to be etched and the use of the device, its etching range can also be extended into the substrate 620, as shown in Figure 6e 5 10 15 20 For example, wet etchants available for CMOS include tetramethylammonium hydroxide

(TMAH), potassium hydroxide or sodium hydroxide (KOI ^ NaOH), pyrocatechuic ethylenediamine (EDP). Useful dry etchants include, for example, fluorinated hydrocarbon gas (CFx), xenon difluoride (XeF2), and sulfur hexafluoride (SF6). This etching process will form the first addressable lines 632 and 632, etc. having line widths 631 and 631, respectively. The line widths 631 and 631 'typically have a width of less than 75 nm. The actual line width will depend on various parameters and the components used in the memory device, such as the materials used to make the first addressable layer 630 and the device structure layer 634, and the specific use of the memory device. In addition, the secret processing process will also align the device structure layer 634 to the first addressable lines 632 and 632, etc. along the directions of the lines shown in the detailed diagram, and make device structure lines 635 and 635, etc.

The self-calibrated nano rectifier component manufacturing process 584 can also include a cover removal process to remove the protruding fine structure (and 656 ', etc.) or the optional hard parts described above as shown in 6e # a6f_] Mask (not shown). Generally, the grass removal process can be made of any suitable body material or a dry engraving method for the use of the printed layer 660 (see the embodiment as an etching mask). The method used to remove the dirty 656 from the original materials, such as: gas nail burn, or oxygen electric radon, etc. can also be used in this process. For the use of this optional engraving) Real_'difficulty 'material of Zhu 21 200525736. For example, a wet money engraved with sulfur or sodium hydroxide can be used to engrav a hard surname with a surname. Also, the hood The volume removal process will expose the device structure surface 637, as shown in Figure 6f. The planarization layer manufacturing step 586 (see Figure 6g) will be used to deposit a planarizable dielectric layer 670 on the substrate. The surface of the exposed area of the material and covers the surface of the device structure 637. A variety of inorganic or polymer dielectrics can be used. For example, silicon dioxide deposited using plasma enhanced chemical vapor deposition (PECVD) can be used. Other materials such as silicon nitride, silicon oxynitride, polyimide, phenylbutyrate, and others Inorganic nitrides and oxides can also be used. In addition, other oxide oxide films such as ethyl tetraorthophosphate (TEOS) and its "spin coating, glass, < made by other techniques Glass, etc. can also be used. The planarization process 588 is used to planarize the dielectric layer 67 (see Figure 6h). For example, the dielectric layer planarization process 588 can be mechanically, impedance-etched, Or chemical mechanical method, etc. to form the substance 15 672 (see paragraph _).-'Surface switching layer manufacturing step 590 is used to make the switching layer 64. It is overlaid on the flat surface 672 of the device structure layer 634 and the dielectric layer ㈣. , As shown in Figure ^: Depending on the cross-bar memory device will be used, the switching layer or surplus = media layer _ can be made of a variety of materials, such as organic matter or polymer Change layers such as indium selenide, ferroelectric layers such as piezoelectric ceramics, or materials such as ceramics Polyethylene terephthalate 'silk formation (ie, anti-solubilization) layer, such as the second one = e3' doped polymer layer, such as polycarbonate doped with acceptor or donor molecules 9 'conductive polymer, such as polyethylene Oxygenated polystyrene continued, and two-layer monolayers such as thiol and Shi Xixuan composites are just some examples that can be used to make this = 22 200525736 tenths or switching layers. Depending on the materials used, Various manufacturing methods such as sputtering / youji, CVD, spin coating, langmuir-bio (jgett) deposition, and various methods that can be combined by themselves can be used to make the switching layer 640. The nano-printing step 592 is used to create the second printed layer 661, and 5 prints the desired structure or feature into this layer 661 (see Figures 6i to 61). As shown in FIG. 6i, the second printed layer 661 may be applied by any suitable technique, such as spin coating, vapor deposition, spray coating, or inkjet deposition used for the nano printed layer 582 described above. Please note that Figures 6j ~ 6n are rotated 90 degrees relative to Figures 6a ~ 6i ', but the structure disclosed in these drawings is not limited to these 90 degrees and 10 angles. The through-printing layer may be the same as or similar to that described in the nano-printing layer manufacturing process 582 described above, but other printing layer materials may be used. For example, the first printed layer 661 (see FIG. 6i) may be a spin-coated low-viscosity and photopolymerizable silicone solution. The second printed layer 661 may be any formable material. 15 The second nanoprinting step 592 also includes printing the desired structure or feature into the second print layer 661 (see Figure 6j). The second nano-printer 663 is pressed toward the printed layer 661 when the printed layer is flexible, and the concave fine structures 658 and the convex fine structures 656 and 656 are formed therein. The nanoprinting process and the nanoprinter are similar to those described previously in the nanoprinting process 582. For illustrative purposes only, the recesses 654 and 654, the protruding fine structures 656 and 656 ', the recessed fine structures 658, and the stamper protruding portions 664 are all shown in the same manner as in the & . Please understand that different sizes and shapes can also be used in the second nanoprinting step. For example, a printed layer formed using a photo-curable material such as S-FIL Monomat AcOl can be used with a printer with a back pressure of 23 200525736 0.25bai * with a force of 2 Newtons and an extension time of about 15 seconds. To imprint. The S-FILMonomat AcOl can be cured by exposing a light source of an Hg_x ^ external arc lamp, for example, 1000w with an I-line shot (gp 365nm) for about 30 seconds (as shown in the photon 610 'in FIG. 6j). 5 The self-calibrated nano storage structure manufacturing method step 594 is used to make a second addressable line and a switch line from the corresponding material layer. The process 594 includes removing the recessed fine structure 658 (see FIG. 6j) exposed in the exposed area 659 (see FIG. 敁) of the switching layer 64 when the nanometer is printed. Removal of these recessed fine structures can be accomplished by wet or dry etching of any material suitable for the imprint layer. The φ 10 self-calibrating nanometer storage structure manufacturing step 594 also includes a second addressable layer manufacturing process for making a second addressable layer 65, as shown in FIG. 61. In this embodiment, the second addressable layer 65 also forms a hard etch mask. The second addressable layer 650 is formed by depositing a metal layer on the nano-printed surface after the concave fine structures have been removed. For example, a thin layer of Shaoxing, New Zealand, 15 platinum, chromium, titanium, tungsten, gold or steel can be deposited on the nano-printed surface. Subsequent surface removal methods or selective chemistry | insect engraving can be used to remove The protruding portions 656 and 656 of the printed layer are removed, etc. (see Figures 61 and 6m), so that Shen Chunji is on the protruding portions 656 and 656, and the addressable layer material on the top can be deposited with the exposed area 657. The metals in it are removed together, leaving only the manufactured second addressable line 652 etc. as shown in FIG. 6m. The second addressable lines 652 can also form a cover for etching the area previously covered by the protruding fine structure. The selective chemical etching or high-level removal method used will depend on the printing material and hard etch mask material used. In a variant embodiment, the manufacturing process of the second addressable layer can also be performed after the process of switching the layer 590. In the embodiments such as 24 200525736, the second nano-printing process 661 is fabricated on the second addressable layer 650. 5 10 15 20

The self-calibrating nanometer storage structure manufacturing step 594 also includes an etch switch layer 640 and device structure lines 635 and 635, (see FIG. 6i). This etching process will etch areas that are not protected by the second addressable line 652, as shown in Figures 6 and 6ri. The switching layer 64 and the device structure lines 635 and 635 'can be etched by any wet or dry etching method or a combination method suitable for the material used. Any of the foregoing etching methods are just a few examples of the variety of etching methods available. This etching process will cause the storage medium line to have a line width of 651. This line width is typically less than 75 nm. In addition, the etching process will also form various device clock structures 636, etc., which will automatically align with the storage medium ^ 641 and the first addressing line 652 along the directions of the lines, and keep the self-aligning structure at the first Addressable on line 632. The actual line width will depend on various parameters and the components used in the memory device, such as the materials used to make the second addressable layer 652 and the switching layer 64, and the specific use of the memory device.

A method using an embodiment of the present invention is shown in cross-sections 7a to 7h. In this embodiment, the substrate 720 is a doped Shi Xi wafer, and a buried oxide layer 726 is provided on the Shi Xi wafer. The buried oxide layer 7 2 6 The devices on the wafer are electrically isolated. ^ The Shixi layer 722 is fabricated on top of the buried oxide layer, and then a pupal wormwood layer 723 is grown ′ ′ two regrown η-doped worm crystal cut layers 724. The two stone stone layers 723 and 724 will form a -semiconducting diode brain. In the transformation, the P-doped and η-doped worm crystal layers can also be arranged oppositely. The oxide layer 726, intrinsic stone layer M2, p, etc. embedded in 4 in 25, etc. 25 200525736 stone layer 723, n-doped stupid stone layer 724 have about 100, % ·, LOOrnn, 150mn thickness. The doping concentration and thickness can also be changed to control the electrical characteristics of the layers. Also, in other embodiments, different majority stupid crystal layers may be formed. For example, the -n + 4n ++ doped layer can also be grown on top of the η layer shown in Fig. 5 to enhance the contact characteristics to the switching or storage medium layer (not shown). Another example is a thin-film stack of buried oxide / ρ + worm crystal layer / ρ epitaxial layer / η epitaxial layer / η epitaxial layer, etc., to form a rectifying structure. In addition, various combinations of stepped and different dopant distributions can be used. In this example, various epitaxial techniques such as chemical vapor deposition (cvd) including 10 CVD, LP CVD and PE CVD 'or molecular beam stupid (MBE) can be used to make such stupid layers. . The stop or detection layer 725 will be fabricated on the n-doped stupid evening layer 724, as shown in Fig. 7b. In this example, the broadcast layer is a nitride layer that is deposited on the surface using a conventional chemical vapor deposition device. Any layer b filled with k for endpoint detection can form the broadcast layer 725. A printed resistor 760 is formed on the blocking layer 725. In this embodiment, the resistor 760 is PMMA and is made using spin coating. In alternative embodiments, any of the printing materials or deposition techniques described above may also be used. When the printed resistor 76 is formed, a nano-printer will press the resistor 76 while the resistor is flexible. Similar to the printing method described in Figs. 5 and 6, the printer has a feature texture and the like complementary to the shape to be formed on the impedance object 760. In this embodiment, PMMA will be used as the printed resistive material, and will be baked after acceptance after spin coating, and the excessive solvent will be driven out from the surface of the substrate. The printed mold is set to contact the printed resistor in the nano-printer, and is heated to about 185t for about 20 minutes, while applying a pressure of about 1250 psi. In a variant embodiment, the resistor can be heated to 180-195 ° C for about 10-25 minutes at a pressure of about 1000-1500 psi. Any recessed portion formed in the nanoprinting (see Figure 6 (: figure)) can be removed by any wet or dry method suitable for the printed resistor 760 as described above. In this example, a hard etch mask will be used, which is formed by depositing a thin thermally evaporated chromium layer 767 after the concave texture is removed, as shown in Figure 7c. In a modified embodiment Various deposition processes such as electron beam evaporation or chemical vapor deposition can also be used. A high-level removal method will be used to remove the residue of the printed impedance, including 10 chromium deposited on top of the printed layer, As shown in Figures 7c and 7d. The chrome 767 portion left after the high-level removal process will form a hard etch mask 780 as shown in Figure 7d. A silicon etchant will be used to etch through the silicon nitride barrier. The stop layer 725 and the areas of the η, P, and intrinsic epitaxial layers 724, 723, and 722 that are not covered by the chrome hard etch mask 768 are shown in FIG. 7e. In this example, the last name engraving process is appropriate. 15 Stopped in the buried oxide layer 726, which can be used to electrically isolate the rectification lines or structures made in the etching process. The layers The last name engraving can be performed using any dry or wet etching method or combination of methods suitable for the epitaxial layer material used. In this example, a one or two step dry etching method is used. The first last name engraving procedure is Under the pressure of about 10milliTorr, the Q but VCFVAr / SFdhi 20 compound was used at a flow rate of 30/30/30/10 standard cubic centimeters (sscm). The second-second procedure was also performed at a pressure of about 1 OmilliTorr Next, an Ar / He mixture is used at a flow rate of i0 / i〇sscn ^ 〇. The etching process will form a first addressable line 732 with a line width 731, etc. The line width 731 is typically less than 75nm, and In this example, the line width 731 is about 30 nm. In this example 27 200525736, the n-doped epitaxial silicon layer 724 will form a device structure layer 734, which will align itself to the first addressable address after etching. Line 732, and also has a line width of about 30 nm, as shown in Figure 7e. In this example, the chrome hard etch mask 768 uses a sulfonium ammonium nitride (CeW ^ MCO3) 6) and peroxy acid (HclO4) wet etching 5 agent, and the remaining time of about 40 minutes to remove. In this example, the planarization process includes making two gasified silicon planarizable layers 770 to a thickness on a silicon substrate 72, which is larger than the epitaxial silicon layers and formed in the above-mentioned rice-engraving process. The combined thickness of the nitride stone blocking layer and the like filled in the area between the lines is shown in FIG. 7f. In this example, a low temperature (about 400 ° C) PECVD using a tetra 10 ethyl orthosilicate precursor will be used to form the silicon dioxide layer to a thickness of about 2 microns. After the planarizable layer is deposited, a chemical mechanical planarization (CMP) process is used to form a flat silicon dioxide surface 771 as shown in FIG. 7g. In this example, a reactive ion etching method is used to further etch and remove the upper layer of silicon dioxide and silicon nitride, 15 to form a flat surface 772 on the surface of the device structure layer 734, as shown in the first few figures. The reactive ion etching method is used at a pressure of about 1200 milliTorr.

The mixture of Ar and CF4 achieves a silicon oxide etch rate of about 60 people per second at flow rates of 45 and 50 sccm, respectively. In this example, the storage media line and the second addressable line are fabricated using a method similar to that described previously in FIG. 6. [Brief Description of Drawings] Figure 1a is a perspective view of a memory device according to an embodiment of the present invention. Figure lb is a cross-sectional view of one element of the memory device of Figure 1a. FIG. 2 is a cross-sectional view of a component of a memory device according to a possible embodiment of the present invention. FIG. 3 is a cross-sectional view of a component of a memory device according to a possible embodiment of the present invention. FIG. 4 is a cross-sectional view of a component of a memory device according to a possible embodiment of the present invention. Fig. 5 is a flowchart of a method for manufacturing a memory device according to an embodiment of the present invention. Figures 6a to 6η are cross-sectional views of different processes used to make the embodiments of the present invention. 10 Figures 7a to 7h are cross-sectional views of different processes used to manufacture the embodiments of the present invention. [Description of main component symbols] 148, 248, 348, 448 ... Switching interface 151, 251, 351, 451 to line width 152, 252, 352, 452, 652 ... The second addressable line 226, 326, 670 ... Dielectric layer 322, 323, 324 ... Semiconductor layer 327 ... Worm crystal layer 342, 641 ... Storage medium line 433 ... Insulation layer 580 to 594 ... Each manufacturing step 600 ... Memory device 610 ... Photon 100 ... Crossbar memory structure 101, 201, 301, 401 ... logic cells 102, 202, 302, 402 ... rectifier elements 104, 204, 304, 404 ... storage structures 120, 220, 320, 420, 620, 720 to substrates 131, 631, 731 ... line widths 132, 232, 332, 432, 632, 732 ... · first addressable lines 136, 236 , 336, 436, 635, 636 ... Device structure 138, 238, 338 ... Rectifying interface 142, 242, 342, 442 ... Switching line 29 200525736 630 ... First addressable layer 672,771,772 ... Flat surface 634 , 734 ... Device structure layer 722 ... Intrinsic stone layer 637 ... Device structure surface 723 " ρ epitaxial silicon layer 656 ... Protruding fine structure 724 ... n epitaxial silicon layer 657,659 ... Exposed area 725 ... stop layer 658 ... depressed fine structure 726 ... oxide layer 660, 661 ... Printed layer 760 ... Printed resistors 662, 663 ... Nanoprinter 767 ... Hard etch cover layer 664 ... Protrusion 768 ... Hard etch cover 640 ... Switching layer 770 ... Planarization layer 650 ... · Second addressable layer 654 ··· Recess 30

Claims (1)

200525736 10. Scope of patent application: 1. A memory device, including: a substrate; most self-calibrated nano rectifier elements have: 5 most of the first electrode wires are provided on the substrate; most of the device structure is provided Most of the self-calibrated nano rectifier elements described above are formed on the first electrode lines, and each device structure has at least one side with a size less than 75 nanometers. And a plurality of second electrode wires are arranged on the nano storage structure and electrically connected to and aligned with each other to form a memory device. 2. The memory device according to item 1 of the patent application, wherein the first electrode lines further include a majority of the first semiconductor lines containing a dopant of a first polarity. 15 3. The memory device according to item 2 of the scope of patent application, wherein the device structures further include a majority of semiconductor device structures containing a second-polar Lu dopant, and each semiconductor device structure will interact with the first One of the semiconductor lines forms a semiconductor junction. The semiconductor junction has an area and at least one side has a size smaller than 75 nm. 20 4. The memory device according to item 2 of the scope of patent application, wherein each device structure further comprises: an intrinsic semiconductor structure provided on one of the first semiconductor lines; and a second semiconductor device structure containing The second-polarity dopant 31 200525736 is provided on the intrinsic semiconductor structure, and both the intrinsic semiconductor structure and the second semiconductor device structure have at least one lateral dimension less than 75 nanometers, forming a majority pin diode element. 5. The memory device according to item 1 of the patent application scope, wherein the first electrode 5 wires further include a majority of metal electrode wires, and the device structures further include a majority of semiconductor device structures containing a dopant, and A plurality of Schottky barrier contacts are formed between the metal electrode lines and the semiconductor device structure. Each Schottky barrier contact has an area and at least one side φ has a size less than 75 nm. 10 6. The memory device according to item 1 of the patent application scope, wherein the first electrode lines further include a plurality of metal electrode lines, and each device structure further includes: a dielectric layer disposed on the metal electrode lines; And a metal layer is disposed on the dielectric layer to form a majority of metal / insulator / metal rectifier elements, and each of the elements has at least one side dimension 15 and less than 75 nm. 7. A memory device comprising: repairing a substrate; a rectifying device comprising a first set of wires arranged on the substrate parallel to each other, the rectifying device will automatically align with the wires, and the rectifying device 20 has at least one The size of the side is less than 75 nanometers; a device can store a data bit in each storage element, and it is overlaid on the first set of wires and aligned with the rectifying device by itself; and a device can electrically address these storages Element, wherein each storage element is self-aligned with the electrical addressing device, and a logic cell of a memory structure is formed at each intersection of the electrical addressing device and the first set of 32 200525736 wires. 8. A method of manufacturing a crossbar device, comprising: nano printing a first nano printed layer disposed on a device structural layer, the device structural layer disposed on a first addressable layer, and the The first addressable layer is provided on a substrate; a plurality of self-calibrated nanometer rectifier elements are made from the first addressable layer and the device structure layer. Each rectifier element has at least one side with a size less than 75 nanometers. A tenth nanometer printed layer is printed on a conductive layer or a storage medium layer, and the storage medium layer is provided on the nanometer rectification elements; and most self-calibrated nanometer storage structures are made. Each storage structure has at least one side dimension less than 75 nm. 9. The method according to item 8 of the patent application, wherein the step of printing the first nano-15 printed layer by the nanometer further comprises: a nano-printing device capable of transmitting ultraviolet light in a wavelength range of about 250 to 500nm. Pressing against the first nano-printed layer; and subjecting the first nano-printed layer to predetermined UV radiation exposure. 10. The method according to item 8 of the scope of patent application, further comprising: 20 causing the first addressable layer on the substrate; and causing the device structural layer to be overlaid and electrically connected to the first addressable layer 11. If applying for a patent The method of item 10, wherein causing the first addressable layer further includes causing a first metal layer to be overlaid on the substrate. 33 200525736 12. The method according to item 11 of the scope of patent application further includes forming a dielectric layer on the first metal layer, and causing the device structure layer to include a second metal layer on the dielectric layer. 13. The method according to item 11 of the patent application scope further comprises forming a semiconductor layer having a dopant, and the semiconductor layer is electrically connected to the first metal layer to form a Schottky barrier contact. 14. The method according to item 8 of the patent application, wherein making most of the self-calibrated nano rectifier elements further includes selectively removing some parts of the device structure layer and the? First addressable layer. 10 15. The method according to item 14 of the scope of patent application, further comprising selectively etching the device structure layer and some portions of the first addressable layer to form a majority of logic cells, wherein each nano-unrectified element will Coincident and coplanar with the same range of a first addressable line and a nanometer storage structure. 16. The method of claim 8 in which the majority of the self-calibrated nanometer storage structures are manufactured further comprises the selective removal of these conductive layers, the device structure layer, and some parts of the storage medium layer. · 17. The method according to item 16 of the scope of patent application, further comprising selectively removing certain parts of the conductive layer, device structure layer and storage medium layer to form a majority of logical cells, wherein the nanometer rectifiers The components will be coincident and coplanar with the same range of a first addressable line and a nanometer storage structure. 18. The method according to item 8 of the scope of patent application, further comprising: causing a planarizable dielectric layer to be overlaid on the device structure layer, wherein a top surface of the device structure layer forms a plane; and the dielectric The layer is flattened to the plane of the device structural layer. 34 200525736 19. The method according to item 8 of the patent application, wherein making most of the self-calibrated nano-rectifying elements further comprises etching the device structure layer. 20. The method according to item 8 of the patent application scope, further comprising: causing a storage medium layer to be electrically connected to the device structure layer; and 5 causing a conductive layer to be electrically connected to the storage medium layer. 35