1274401 1248ltwf.d〇c/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體的製造方法’且特別是有 關於一種硫化物記憶胞的製造方法。 【先前技術】 可電寫入及可電抹除的相變(phase change)材料在常 用於記憶體元件中。而硫化物材料可在兩種結構狀態之間 進行電性轉換，此兩種結構狀態為一般結晶狀及_般非結 晶狀的局部秩序。其中，一般結晶狀態係一位相(phase)， 在此一位相中材料的原子及/或電子形成重複的栅狀結 構。反之，一般非結晶狀態的原子及/或電子係隨機分佈。 而此一結構狀態可在一局部秩序之可察覺的結構狀態範圍 中進行轉換，此範圍係在極端完整的結晶狀態及極端完整 的非結晶狀態之間。 現今用於相變記憶體應用上，較佳使用的硫化物材料 典型地包含碲(tellurium)、硒(seienium)、鍺(germanimn)、 銻(stibium)、鉍(bismuth)、鉛(Plumbum)、錫(Stann腿）、砷 (arsenic)、石爪(sulfur)、石夕(silicon)及/或氧(〇xygen)等混合物。 因為結構狀態的範圍，剛沉澱(as_dep〇sited)的一給定化學 計量硫化物材料可具有多變的整體導電性。一般來說，^ 其狀態具有越高結晶狀的局部秩序時，則此材料有越高= 導電性。此外，此一材料的導電性透過一給定電壓及持續 期間的電脈衝可被選擇性地及重複性地建立，稱其為設定 (setting)電壓或是重置(resetting)電壓。此導電性會保持穩 1274401 12481twf.doc/g 定，直到施加另-具可比較規模的設定電壓或重設電壓才 會有所變化。更進-步的說，此材料的導電性似乎在使用 ^疋電壓或重設電壓的情況下進行反轉的變化，且並不依 讀料之前所存在的狀態，換言之，就是缺乏磁滯現象。 來儲發㈣度仏記㈣巾，上述㈣料可被用 末儲存及娜貧訊。當使用不同設定電墨或是重置電壓以 3=導=時，相對應的導電性可由許多不同的方 的材應用—相對較小的電鮮過此記憶胞中 Ϊ ，但並不限於只有此一方法。舉例來說，如 壓或是重置電壓，-記憶胞可以儲 資料中的—位元。因為硫化物材料 在此μ^的導電性，所以記憶胞是非揮發性的，且 ==可被直接過度寫入的意思是，在細： 再。己fe肊中k，並不需要進行資料抹除。 金氧物相變記㈣並不容隸合到互補式 流密度3;;:能因==需要-相對較高的電 減少直接部分的Ϊ::4 Γ部分的截面區域，可 觸窗中的方;的製財式及將硫化物沉積到接 用一介電薄種製奴小接觸窗的方法與使 影制π關例如疋一間隙壁，以更進一步減少為 技術可區Πί國專利第6，iu，264號。此二 品或但疋收縮比(shrinking ratio)卻受到 1274401 12481twf.doc/g 間隙壁厚度的關。舉例來說，如果孔 1刪埃且間瞻的厚度㈣G埃，難祕觀只有^ 而幻的孔/同直#係由微影製程及間隙壁的厚度決定 以，收縮比可被限制。因此，在此情況下，很難縮小硫化 物的，分。如果硫化物的部分不能縮小，Μ需要更大的電 知材料中的狀態改變。而因為需要較大的電流，相對 的舄要較大的功率來操此一類型的記憶胞陣列。 當孔洞的規格縮小時，會出現其他的問題。例如，孔 對孔(p〇re_t〇-P〇re)直徑的一致性會變差。此外，小的孔洞 會受到硫化物的沉積製程的限制，因為要將硫化物材料沉 積到微小的開口中是非常困難的。例如，使用前述章節中 的製程方法所形成的孔洞，間隙壁凸出的部分會部分或是 完全阻擋住孔洞，需更進一步在沉積製程中在可靠度方面 進行女協。另外，如果孔洞的底部受到較差的覆蓋，在其 下方的電極將不會預期性的改變其硫化物部分的位相。當 施加一給定電流時，如果位相不能重複，則記憶胞將不能 可靠地進行資料儲存。 因此’在習知技術的硫化物記憶胞需要一種在相對較 小的電流下，可靠地進行資料儲存的能力。更需要一種電 極的製造方法，以在一相對較小的結面區域中，製造出硫 化物材質的接觸窗。 【發明内容】 有鑑於此，本發明係提出一種硫化物記憶胞的形成方 法’其中硫化物記憶胞之接觸窗係建立在一個非常小的截 1274401 12481twf.doc/g 面區域中。料發明提出之方法賴姑财電極的厚产 及字兀線的寬度’以控織面區域的規格。在本發明 佳實施例法巾，首先在基底上職下電極。接著，在 物記憶體組件。然後，在硫化物記憶體 組件上形成子兀線。 …本發明更揭露-種記憶胞，係利用本發明所提出之方 法形成之。在本發明一較佳實施例中，包括一位元線、一 隔離元件及-下電極。其中，位福係配置在—基底中。 隔離元件佩置於位元線上。下電極佩置於祕元件上 i具有二厚度。在此實關巾，更包括—硫化物記憶體組 及一^元線。其中硫化物記憶體組件係配置於下電極 ^，且字元線具有-寬度。而字元線係配置於硫化物記憶 -、、：件上且^化物s己憶體組件的一戴面區域係由下電極 的厚度及字元線的寬度決定。 夕本發明另一較佳實施例中係提出一種記憶體陣列，包 括^數條位元線、多數條字元線及多數個記憶胞。其中， 位凡線係配置在—參考方向上，财元線配置在與此參考 =向不同的一方向上，且具各字元線具有一寬度。而記憶 胞係位在字元線與位元線的個交界處。而且，各記憶胞包 括一下電極及一硫化物記憶體組件。其中，下電極係配置 於各字元線與各位元線之間所對應的交界處，且具有一厚 度。且硫化物記憶體組件係配置於一記憶胞的下電極與字 A線之間，而硫化物記憶體組件的一截面區域係由下電極 的厚度及字元線的寬度所決定。 1274401 12481twf.doc/g 本發明更提出一種硫化物記憶胞的操作方法，以重置 及设定硫化物記憶胞。其中，重置硫化物記憶胞的方法， 係藉由施加一非結晶狀態電流脈衝到記憶胞，以使得記憶 胞中之硫化物g己憶體組件的溫度上升並高於第一溫度。此 非結晶狀態電流脈衝在第一時間間隔中，更進一步導致硫 化物5己丨思胞的溫度維持南於第二溫度而低於第一溫度。另 一方面’設定硫化物記憶胞的方法，係藉由施加一結晶狀 悲電ML脈衝到§己憶胞，以使硫化物記憶體組件的溫度上升 並高於第二溫度，且在第二時間間隔中硫化物記憶胞的溫 度維持高於第二溫度，且第二時間間隔係大於第一時間間 【實施方式】 ^為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。無論在何處，相同或是相似的部分都可能以有相 同或是相似的數字出現在圖式中及内文中。需要注意的 是，本文中的圖式係簡化圖，而非以精確規格繪製。再本 文所揭露的實施例中，為了方便說明及清楚說明的目的， 會使用一些方向性用語，如頂部、底部、左、右、上、下、 上方上面、下面、接近、後面及前面，以說明相關的圖 式，但是廷些方向性用語並不用以限制本發明之範圍。 雖然^此所揭露的為本發明的實施例，必須了解這些 貫鈀例係貝靶本發明範例中的一些方法，並不用以限制本 發明。下列洋細說明雖然只討論一些示範性的實施例，但 1274401 12481twf.doc/g 真正的意圖在於，包含由申請專利範圍所定義、在不脫離 本發明之精神和範圍内的所有修飾後、替代的及等同的實 施例。而在此所描述關於硫化物記憶體結構的製造步驟， 並非包括所有的製造流程。本發明可和此技術領域中常用 的各種積體電路之技術進行整合，然而其中只有一些製程 步驟是必須提出來，以更容易了解本發明。 首先，請參考圖1，圖1係繪示本發明一較佳實施例 中一部分硫化物記憶胞陣列50的示意圖。在其中所描述的 硫化物記憶胞55包括一硫化物記憶體組件6〇，係電性接 觸於字元線90。在此一實施例中，隔離元件7〇透過下電 極65將硫化物纪憶體組件6〇連接到位元線8〇。請繼續參 考圖1，圖1中繪示了四個硫化物記憶胞以簡化說明，一 個典型的陣列係包括數以千計個記憶胞。在圖1中繪示了 兩條位元線80、81及兩條字元線9〇、91。同樣地，典型 的硫化物記憶體陣列包括大量的字元線及位元線，係連接 以控制電路系統中施加設定電壓及重置電壓到硫化物記憶 胞的能力。例如要操作硫化物記憶胞55，會施加一設定電 壓或是重置電壓在字元線90及位元線80之間，硫化物記 憶胞55係位於字元線90及位元線80的交界處。 接著，圖2係繪示硫化物記憶胞製造流程中之膜層結 構的剖面圖。雖然在此一段落中所描述的是一單一硫化物 記憶胞，但是在隨後所描述的圖中係在單一基底上形成多 數個硫化物記憶胞。在此處所揭露的方法，可用以形成相 對大量的硫化物記憶胞。在另一較佳實施例中，硫化物記 1274401 12481 twf. doc/g 十思胞的製造方法，包括以孰 型基底刚上形❹數歸周知的方法在p 的材質例如是摻雜多晶石夕，舉例來1兒，=θρ型基底100 行摻雜，摻雜的濃度例如是，〜⑽進 接著，在Ρ型基底j 〇〇卜报士 原子方Α刀。 是择雜多日欲與十 型膜層105,其材質例如 f b ΒΒ _ ’舉㈣說’例如是以 摻雜的濃度例如是1GM〜1()16個 原、子進㈣雜， 此〜心+ 原子/立方公分。然後，在 α, 1 , N+型膜層105上形成N-型膜層11〇，j： 10〜10個原子/立方公分。之後，在N-型膜層110上; ίΓ的型^115 ’其材質例如是摻雜多㈣:舉例來說^ =^辰度例如是1Gm〜，個原子/立方公分。在硫化物 。思月巴的-具代表性的實施例中，N+型膜層ι〇5用以 =70線’而P爆型膜層115/11〇係用以形成一 PN二極 -’其作用為作為圖i中的隔離元件7G。這些細節的部 將詳述於下文中。 d後在P+型膜層115上形成一金屬石夕化物層120， 其材質例如是鎢(tungsten)金屬矽化物或鈷(c〇baU)金屬矽 化物。接著，在金屬矽化物層12〇上形成一緩衝層125， 其材貝例如是絕緣材料，如二氧化矽。之後，在緩衝層 上形成一鼠化碎層130。 之後，圖3係繪示在圖2的膜層結構中形成溝渠14〇 的aj面圖。圖3中溝渠140的形成方法，例如是在膜層結 構的上表面塗佈一光阻層（未緣示），並利用微影製程對此 1274401 1248ltwf.d〇c/g 光阻層進行圖案化。而形 案進行-勤i製程。在此材料會以此光阻圖 串的蝕刻製程。例如，進 f作中’例如是進行-連 T層130，其係一選擇性部份氮化 程），此钱刻劍相較於氧化物化:電襞钱刻製 性。接著，進行―第-❹丨⑽化物核肖触刻選擇 係違擇性餘刻製程(例如是帝 打曰⑵，其 劑相較於金屬矽化物， 水蝕刻衣程），此蝕刻1274401 1248ltwf.d〇c/g IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a method for producing a semiconductor, and particularly to a method for producing a sulfide memory cell. [Prior Art] Phase change materials that can be electrically written and electrically erasable are commonly used in memory devices. The sulphide material can be electrically converted between two structural states, which are generally crystalline and _like non-crystallized local order. Among them, the general crystalline state is a single phase in which atoms and/or electrons of a material form a repeating lattice structure. Conversely, atoms and/or electrons in a generally amorphous state are randomly distributed. This structural state can be converted in the range of perceptible structural states of a partial order between an extremely intact crystalline state and an extremely intact amorphous state. The preferred sulfide materials for phase change memory applications today typically include tellurium, seienium, germanimn, stibium, bismuth, plumbum, A mixture of tin (Stann legs), arsenic, sulphur, silicon, and/or oxygen (〇xygen). Because of the range of structural states, a given stoichiometric sulfide material that has just precipitated (as_dep〇sited) can have variable overall conductivity. In general, when the state has a higher degree of crystalline local order, the higher the material = conductivity. In addition, the conductivity of the material can be selectively and repetitively established through a given voltage and electrical pulses during the duration, which is referred to as a setting voltage or a resetting voltage. This conductivity will remain stable at 1274401 12481 twf.doc/g until a different set voltage or reset voltage is applied. Further, the conductivity of this material seems to be reversed with the use of a voltage or reset voltage, and does not depend on the state that existed before the material, in other words, the lack of hysteresis. To store and send (four) degree notes (four) towels, the above (four) materials can be used for the end of storage and Na Naxun. When using different setting inks or resetting voltages to 3 = conduction =, the corresponding conductivity can be applied by many different materials - relatively small electricity is used in the memory cell, but not limited to only This method. For example, if voltage is applied or reset, the memory cell can store the bits in the data. Because the sulfide material is electrically conductive here, the memory cell is non-volatile, and == can be over-written directly, meaning fine: again. It has no need to erase the data. The gold oxide phase change (4) does not fit into the complementary flow density 3;;: energy == need - relatively high electricity reduction direct part of the Ϊ::4 Γ part of the cross-sectional area, can be touched in the window The method of making money and the method of depositing sulfides into a thin contact window for the use of a dielectric thin seed, and making the shadow π off, for example, a gap, to further reduce the number of patents. 6, iu, 264. The shrinkage ratio of the two products or the tantalum is limited by the thickness of the gap of 1274401 12481 twf.doc/g. For example, if the hole 1 has a cut-off thickness and a thickness of (4) G angstroms, it is difficult to see that only the phantom hole/same straight line is determined by the thickness of the lithography process and the spacer, and the shrinkage ratio can be limited. Therefore, in this case, it is difficult to reduce the fraction of sulfide. If the portion of the sulfide cannot be shrunk, the state change in the larger material is required. And because a larger current is required, a relatively large amount of power is required to operate this type of memory cell array. Other problems arise when the hole size is reduced. For example, the uniformity of the diameter of the hole to the hole (p〇re_t〇-P〇re) may be deteriorated. In addition, small holes are limited by the deposition process of the sulfide because it is very difficult to deposit the sulfide material into the tiny openings. For example, using the holes formed by the process method in the previous section, the protruding portion of the spacer partially or completely blocks the hole, and the female association is further required in terms of reliability in the deposition process. In addition, if the bottom of the hole is poorly covered, the electrode below it will not change the phase of its sulfide portion unexpectedly. When a given current is applied, if the phase cannot be repeated, the memory cell will not be able to reliably store the data. Therefore, in the conventional technology, sulfide memory cells require an ability to reliably store data at a relatively small current. There is a further need for a method of fabricating an electrode that produces a contact window of a sulphur material in a relatively small junction area. SUMMARY OF THE INVENTION In view of the above, the present invention proposes a method for forming a sulfide memory cell, wherein the contact window of the sulfide memory cell is established in a very small cross-section of 1274401 12481 twf.doc/g. According to the method proposed by the invention, the thickness of the Lai Gucai electrode and the width of the word line are 'to control the specifications of the weaving surface area. In a preferred embodiment of the invention, the lower electrode is first placed on the substrate. Next, the object memory component. Then, a sub-twist line is formed on the sulfide memory component. The invention further discloses that a memory cell is formed by the method proposed by the present invention. In a preferred embodiment of the invention, a one-dimensional line, an isolation element, and a lower electrode are included. Among them, the Blessed is arranged in the base. The isolation component is placed on the bit line. The lower electrode is placed on the secret element and has two thicknesses. In this case, the cover towel includes a sulphide memory group and a ray line. The sulfide memory component is disposed on the lower electrode ^, and the word line has a width. The word line system is disposed on the sulfide memory, and the wearing area of the component is determined by the thickness of the lower electrode and the width of the word line. In another preferred embodiment of the present invention, a memory array is provided, including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Wherein, the line is arranged in the reference direction, the fiscal line is arranged in a direction different from the reference = direction, and each character line has a width. The memory cell is located at the intersection of the word line and the bit line. Moreover, each memory cell includes a lower electrode and a sulfide memory component. The lower electrode is disposed at a boundary between each of the word lines and the bit lines, and has a thickness. And the sulfide memory component is disposed between the lower electrode of the memory cell and the word A line, and a cross-sectional area of the sulfide memory component is determined by the thickness of the lower electrode and the width of the word line. 1274401 12481twf.doc/g The present invention further provides a method of operating a sulfide memory cell to reset and set a sulfide memory cell. Wherein, the method of resetting the sulfide memory cell is performed by applying a non-crystalline current pulse to the memory cell such that the temperature of the sulfide g-resonance component in the memory cell rises above the first temperature. This amorphous state current pulse, in the first time interval, further causes the temperature of the sulphide 5 丨 丨 cell to remain south to the second temperature and lower than the first temperature. On the other hand, the method of setting a sulfide memory cell is to apply a crystalline sinusoidal ML pulse to the § cell to increase the temperature of the sulfide memory component above the second temperature, and in the second The temperature of the sulfide memory cell is maintained higher than the second temperature in the time interval, and the second time interval is greater than the first time interval. [Embodiment] The above and other objects, features and advantages of the present invention are more apparent and understandable. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same or similar parts may appear in the drawings and in the context of the same or similar. It should be noted that the drawings in this article are simplified diagrams rather than drawn in precise specifications. In the embodiments disclosed herein, for the purpose of convenience of explanation and clarity, some directional terms such as top, bottom, left, right, up, down, top, bottom, bottom, back, and front are used. The related drawings are described, but the directional terms are not intended to limit the scope of the invention. Although the embodiments disclosed herein are disclosed, it is necessary to understand some of the methods of the present invention in the examples of the present invention and are not intended to limit the invention. The following detailed description of the invention is intended to be illustrative of the preferred embodiments of the invention, and the invention is intended to be limited to the scope of the invention, and all modifications and substitutions may be made without departing from the spirit and scope of the invention. And equivalent embodiments. The manufacturing steps described herein with respect to the sulfide memory structure do not include all manufacturing processes. The present invention can be integrated with the techniques of various integrated circuits commonly used in the art, however, only some of the process steps must be presented to make the present invention easier to understand. First, please refer to FIG. 1. FIG. 1 is a schematic diagram showing a portion of a sulfide memory cell array 50 in accordance with a preferred embodiment of the present invention. The sulfide memory cell 55 described therein includes a sulfide memory component 6A electrically contacting the word line 90. In this embodiment, the spacer element 7 is connected to the bit line 8A through the lower electrode 65. Please continue to refer to Figure 1, which depicts four sulfide memory cells for simplicity of illustration. A typical array includes thousands of memory cells. Two bit lines 80, 81 and two word lines 9, 〇, 91 are shown in FIG. Similarly, a typical sulfide memory array includes a large number of word lines and bit lines that are connected to control the ability to apply a set voltage and reset voltage to the sulfide memory cells in the circuitry. For example, to operate the sulfide memory cell 55, a set voltage or a reset voltage is applied between the word line 90 and the bit line 80, and the sulfide memory cell 55 is located at the boundary of the word line 90 and the bit line 80. At the office. Next, Fig. 2 is a cross-sectional view showing the structure of a film layer in a process for producing a sulfide memory cell. Although a single sulfide memory cell is described in this paragraph, in the figures described later, a plurality of sulfide memory cells are formed on a single substrate. The methods disclosed herein can be used to form relatively large amounts of sulfide memory cells. In another preferred embodiment, the sulphide is 127,440, 148, 480 twf. doc/g. The method of manufacturing the smear, including the method of forming the 基底-type substrate just as the number of ❹ is known in the material of p, for example, doped polycrystalline Shi Xi, for example, 1 = θρ-type substrate 100 rows doped, the doping concentration is, for example, ~ (10) and then, in the Ρ-type substrate j 〇〇 报 士 atom atom square Α. It is a multi-day and ten-type film layer 105, and its material is, for example, fb ΒΒ _ 'lifting (four) saying 'for example, the doping concentration is, for example, 1 GM~1 () 16 original, sub-into (four) miscellaneous, this ~ heart + atom / cubic centimeter. Then, an N-type film layer 11 is formed on the α, 1 , N+ type film layer 105, j: 10 to 10 atoms/cm 3 . Thereafter, on the N-type film layer 110; the material of the type ^115' is, for example, doped (4): for example, ^^^ is, for example, 1 Gm~, atom/cm. In sulfides. In a representative embodiment of the model, the N+ type film layer ι〇5 is used for =70 lines' and the P-explosive type film layer 115/11 is used to form a PN diode-' Isolation element 7G in Figure i. The details of these sections will be detailed below. After d, a metal lithium layer 120 is formed on the P+ type film layer 115, and the material thereof is, for example, tungsten (tungsten) metal telluride or cobalt (c〇baU) metal telluride. Next, a buffer layer 125 is formed on the metal telluride layer 12, and the material is, for example, an insulating material such as cerium oxide. Thereafter, a ratified layer 130 is formed on the buffer layer. 3 is a diagram showing the aj of the trench 14 形成 formed in the film structure of FIG. 2 . The method for forming the trench 140 in FIG. 3 is, for example, coating a photoresist layer on the upper surface of the film structure (not shown), and patterning the 1274403 1248 ltwf.d〇c/g photoresist layer by a lithography process. Chemical. And the case is carried out - the process of diligence. In this material, the etching process of the photoresist pattern is used. For example, if the process is carried out, for example, the T-layer 130 is carried out, which is a selective partial nitridation process, and the sword is compared to the oxidization: electricity engraving. Then, the “第-❹丨(10) nucleus nucleation is selected as a process of the lithography process (for example, 帝 曰 (2), which is compared to the metal sulphate, water etching process), this etching
後，進行-制f ^有較高的韻刻選擇性。之 係一選擇性仙制々，甘」 屬夕化物層120，其 有較高_刻選擇性。繼之〜/心抑化物 乾式電魅二T 丁一第四蝕刻製程(例如是 n虫刻製程)移除部份p+型膜層m、队型膜層 +里膜層105及一部分的p型基底1〇〇。 、曰 (hij下來’圖4鱗示在® 3的結構上沉積高密度電漿 一 —ensity Plasma，HDp)氧化物145的剖面圖。其中，此 氧145填滿溝渠14—示於圖3)並覆蓋氮After that, the process-f ^ has a higher rhyme selectivity. A selective sputum, Gan" is an oxime layer 120, which has a higher selectivity. Following the ~ / heart suppressant dry electric charm two T Ding - fourth etching process (for example, n insect engraving process) remove part of the p + type film m, the formation film layer + the inner film layer 105 and a part of the p type The substrate is 1 〇〇. , 曰 (hij down' Figure 4 scale shows a high-density plasma on the structure of the ® 3 - ensity plasma, HDp) 145 section of the oxide. Wherein, the oxygen 145 fills the trench 14 - shown in Figure 3) and covers the nitrogen
㈢〇。再者，圖5係繪示對高密度電漿氧化物145 Γ:、/化學機械研磨製程(chemical mechanical polishing， )後之剖面圖。而此化學機械研磨製程係以氮化矽声 130作為研磨終止層。 繼之，圖6係繪示圖5中之結構選擇性移除氮化矽層 =0及緩衝層125後的剖面圖。在此一移除步驟中，例如 包括至少一個或是連續的多個蝕刻製程。例如，進行一第 J衣程移除氮化石夕層130，其中钱刻劑相較於氧化 12 1274401 12481twf.doc/g 物，對氮化物具有較高的蝕刻選擇性。然後，進行一第二 蝕刻製程移除緩衝層125，其中蝕刻劑相較於金屬矽化 物，對氧化物具有較高的|虫刻選擇性。另一方法是，氮化 矽層130例如是利用熱磷酸進行移除。上述移除步驟的效 果為，使高密度電漿氧化物145延伸於金屬矽化物層12〇 之上。 曰 接者，圖7係、纟會不圖6中之結構曝露出來的上表面上 沉積一導體材料150之薄膜後的剖面圖。其中導體材料丨5〇 覆蓋金屬矽化物層12〇上，因此導體材料15〇形成一較低 的水平部分151。而導體材料150亦沉積在高密度電漿氧 化物145的側壁上，因此導體材料15〇形成一垂直部分 152。而且，其中導體材料15〇的一較高的水平部分153 覆蓋在高密度電漿氧化物145上方。此外，導體材料ι5〇 的垂直β卩勿152及較低的水平部分151在此方法的後續製 程中开>成下電極65,係用於圖1中所繪示的硫化物記憶胞 55。根據另一較佳的實施例，導體材料15〇的材質例如是 鎢(W)、鈕(Ta)、氮化鈦(TiN)、鎢化鈦(TiW)、氮化钽(TaN) 或乳銘化欽(TiAIN) ’且其形成的方法例如是化學氣相沉積 法（chemical vapor deposition，CVD)或物理氣相沉積法 (chemical vapor deposition，PVD)。在另一較佳實施例中， 導體材料150沉積的厚度範圍係在5〇埃〜5〇〇埃之間，在 另^一較么貝施例中，導體材料沉積的厚度約在1〇〇埃。 然後，圖8係繪示在圖7中膜層結構之導體材料15〇 上沉積一氧化層155後之剖面圖。在本發明另一較佳實施 13 1274401 12481 twf.d〇c/g 歹1 ，氧化層155的材質例如是二氧化石夕，其形成方法例 如是化學氣相沉積法。在另一較佳實施例中，氧化層155 ^列如是大體上均勻地形成於此結構曝露出的表面上。接 ，’形成氧化物間紐156(緣示於圖9)，形成的方法例如 疋對圖8中的結構進行一非等向性餘刻。如圖9所緣示， 而此非等向性㈣在表㈣直的方向上移除部份氧化層 155(!會不於圖8)’而留下部分殘存的氧化物間隙壁 ^覆2導體材料150的垂直部分152及部分較低的水 本實闕中，所有水平沉_氧化層155 種侧方法’例如是一反應離子束向下直 =打在基底上。而此㈣方法勤及功率例如是可以 料以垂直加捕等向性侧製財的離子 方向不具有-角度。再者，請參考圖9,在此上， 化，隙壁156具有一圓形或是曲形的外型，二：高密： 電衆氧化物145之間定義出窄的開口。 π;山又 之後，請參考圖10,接著在圖9 !56 圖案化光阻為罩幕進行_烟製程。 步驟例如包括進行一連串的_製程：舉例操作 第-侧製程移除導體材料15G °進订― 其中侧_較於金屬魏物及氧化物， 具有較高的侧獅性。錢，進行—第^ 150 金屬石夕化物層m，其中餘刻劑相較於石夕=程^除 屬石夕化物具有較高_刻選擇性。接下來，繼續 1274401 1248 ltwf.doc/ι 化光阻及氧化物間隙壁156為罩 移，型膜㈣…膜 一部分的P型基底100。 錢層105及 健2述’形成溝渠可建立由N+型膜層形成之自 +準的位7L線106〜1()9。而在另—較佳實施例中，位元 106〜109延伸的方向係與此圖式的平面 a " 入此圖式的平面的方向。 角，例如疋進 =後’請參考圖η，藉由在氧化物間隙壁⑼及較高 、7 "心153上形成南密度電漿氧化物165，並填滿溝 渠二(繪示於圖10)，以對圖1〇中的結構進行修飾。圖η 糸！曰不圖11中之結構進行一化學機械研磨製程後的剖面 ，。其中，在進行此-化學機械研磨製域，係移除部份 同在度甩聚氧化物165、部分氧化物_壁156及導體材 料^0中較局的水平部分153。而在移除導體材料⑼中 較高的水平部分153之後’暴露出導體材料15()中垂直部 为的表面154。其中，暴露的表面154具有一厚度t，其係 由導體材料154的厚度來決定。需要注意的是，厚度t'並 非取决於被影製程中的參數。如上述圖7中所述，厚度t 的範圍例如是在50埃到500埃之間。 之，圖13係繪示在圖12中之元件結構上沉積硫化 物材料層170及字元線材料層175後的剖面圖。在另一較 佳貫施例中’硫化物材料層170的材質例如是由鍺(Ge)、 銻(Sb)及碌(Te)(如Gejbje5)，其形成方法例如是進行一 物理氣相沉積製程，形成的厚度例如在1〇〇埃到1〇〇〇埃之 15 Ι2744081_/§ 間。在另一較佳實施例中，硫化物材料層17〇的厚度約為 500埃。在此一實施例中，字元線材料層175係形成在硫 化物材料層170之上。而此字元線材料層175的材質例如 是鎢(W)、鋁(Α1)、銅(cu)、銅鋁合金或是其它合適之材料， 其形成的方法例如是進行—化學氣相沉積製程 c 1 ，汝匕 字元線材料層175會被圖案化為字元線176(參考圖14)， 其延伸的方向為與圖13的平面平行。(3) 〇. Furthermore, FIG. 5 is a cross-sectional view showing a high-density plasma oxide 145:, / chemical mechanical polishing process. This chemical mechanical polishing process uses a yttrium nitride sound 130 as a polishing stop layer. 6 is a cross-sectional view showing the structure of FIG. 5 after selectively removing the tantalum nitride layer =0 and the buffer layer 125. In this removal step, for example, at least one or a plurality of successive etching processes are included. For example, a J-coating process is performed to remove the nitride layer 130, wherein the money engraving agent has a higher etch selectivity to the nitride than the oxide 12 1274401 12481 twf.doc/g. Then, a second etching process is performed to remove the buffer layer 125, wherein the etchant has a higher etch selectivity to the oxide than the metal ruthenium. Alternatively, the tantalum nitride layer 130 can be removed, for example, using hot phosphoric acid. The effect of the above removal step is to extend the high density plasma oxide 145 over the metal telluride layer 12A. Referring to Fig. 7, Fig. 7 is a cross-sectional view showing a film of a conductor material 150 deposited on the upper surface exposed by the structure of Fig. 6. The conductor material 丨5〇 covers the metal hydride layer 12, so that the conductor material 15 〇 forms a lower horizontal portion 151. Conductor material 150 is also deposited on the sidewalls of high density plasma oxide 145 such that conductor material 15 is formed into a vertical portion 152. Moreover, a higher horizontal portion 153 of the conductor material 15 覆盖 overlies the high density plasma oxide 145. Further, the vertical β 卩 152 of the conductor material ι5 及 and the lower horizontal portion 151 are opened in the subsequent process of the method, and the lower electrode 65 is used for the sulfide memory cell 55 illustrated in Fig. 1. According to another preferred embodiment, the material of the conductor material 15 is, for example, tungsten (W), button (Ta), titanium nitride (TiN), titanium tungsten (TiW), tantalum nitride (TaN) or milk TiAIN's method of forming is, for example, chemical vapor deposition (CVD) or chemical vapor deposition (PVD). In another preferred embodiment, the thickness of the conductive material 150 is between 5 Å and 5 Å, and in the other embodiment, the thickness of the conductive material is about 1 〇〇. Ai. Next, Fig. 8 is a cross-sectional view showing the deposition of an oxide layer 155 on the conductor material 15A of the film structure of Fig. 7. In another preferred embodiment of the present invention, 13 1274401 12481 twf.d〇c/g 歹1, the material of the oxide layer 155 is, for example, a dioxide dioxide, and the formation method is, for example, a chemical vapor deposition method. In another preferred embodiment, the oxide layer 155 is, for example, substantially uniformly formed on the exposed surface of the structure. Then, an oxide inter-junction 156 is formed (the edge is shown in Fig. 9), and a method of forming, for example, 进行 performs an anisotropic residue on the structure in Fig. 8. As shown in Fig. 9, the anisotropy (4) removes the partial oxide layer 155 (! will not be in Fig. 8) in the direction of the table (4) and leaves a portion of the remaining oxide spacers. In the vertical portion 152 of the conductor material 150 and a portion of the lower water body, all of the horizontal _ oxide layer 155 side methods 'e.g., a reactive ion beam down straight = hit on the substrate. And (4) the method and power can be, for example, the ion direction of the vertical trapping isotropic side does not have an angle. Furthermore, please refer to FIG. 9. Here, the gap 156 has a circular or curved shape, and two: high density: a narrow opening is defined between the electric oxides 145. π; After the mountain, please refer to Figure 10, and then in Figure 9!56, the patterned photoresist is used as a mask for the _cigar process. The steps include, for example, performing a series of processes: an example operation of the first side process to remove the conductor material by 15 G ° - which has a higher side lion than the metal material and oxide. The money is carried out - the ^150 metal lithium layer m, wherein the residual agent has a higher selectivity than the shixi = Cheng ^ genus. Next, continue with 1274401 1248 ltwf.doc/ ive photoresist and oxide spacer 156 as a P-type substrate 100 that is part of the mask, film (four)... film. The money layer 105 and the health layer 2 form a trench to establish a self-aligned bit 7L line 106~1()9 formed by the N+ type film layer. In the other preferred embodiment, the direction in which the bits 106 to 109 extend is in the direction of the plane of the pattern a " An angle, such as 疋 = = 'Please refer to Figure η, by forming a south density plasma oxide 165 on the oxide spacer (9) and the upper, 7 " heart 153, and filling the trench 2 (shown in the figure) 10), to modify the structure in Figure 1〇. Figure η 糸!曰The structure in Fig. 11 is subjected to a cross section after a chemical mechanical polishing process. Among them, in the process of performing this-chemical mechanical polishing, the horizontal portion 153 of the partial oxide polyoxide 165, the partial oxide layer 156, and the conductor material ^0 is removed. The surface 154 of the vertical portion of the conductor material 15 () is exposed after the removal of the higher horizontal portion 153 of the conductor material (9). The exposed surface 154 has a thickness t which is determined by the thickness of the conductor material 154. It should be noted that the thickness t' does not depend on the parameters in the process. As described above in Fig. 7, the thickness t ranges, for example, from 50 angstroms to 500 angstroms. 13 is a cross-sectional view showing the deposition of the sulfide material layer 170 and the word line material layer 175 on the element structure of FIG. In another preferred embodiment, the material of the sulfide material layer 170 is, for example, germanium (Ge), antimony (Sb), and tetragon (Te) (such as Gejbje 5), which is formed by, for example, performing a physical vapor deposition. The process is formed to have a thickness of, for example, between 1 〇〇 and 1 〇〇〇 between 15 Ι 2,740,081 _ §. In another preferred embodiment, the layer of sulfide material 17 has a thickness of about 500 angstroms. In this embodiment, the word line material layer 175 is formed over the sulphide material layer 170. The material of the word line material layer 175 is, for example, tungsten (W), aluminum (Α1), copper (cu), copper aluminum alloy or other suitable materials, and the method of forming the method is, for example, performing a chemical vapor deposition process. c 1 , the 汝匕 word line material layer 175 is patterned into word lines 176 (see FIG. 14) extending in a direction parallel to the plane of FIG.
接下來’圖Μ係身示對圖π之結構中之字元線材制 層175進行-钱刻及圖案化製程而成字元線π的剖面 圖。其=:圖14係圖13中沿著剖面線14_14，的剖面圖。 其中’子το線176具有—寬度w，其係由圖案化字元線相 案化製程中的微影製程所決定。在此蝕刻及 ，係包括進行一連串的触刻製程，與前述之 膜層再贅述。此—姓刻步驟，係形成堆疊的 、曰_&：#， 一圖1之硫化物記憶胞55中相關的組件。Next, the figure shows a cross-sectional view of the word line π of the character line layer 175 in the structure of the figure π. == Figure 14 is a cross-sectional view taken along line 14-14 of Figure 13. Where the 'sub-το line 176 has a width w, which is determined by the lithography process in the patterning process of the patterned word line. Etching and etching here includes performing a series of etching processes, which are described in detail with the foregoing film layers. This—the surname step is to form a stacked, 曰_&:#, a related component of the sulfide memory cell 55 of FIG.
喂氧化物ι^5鱗示在圖14中之結構上沉積高密度電 在字元線m 關。其巾，高密度電漿氧化物18( 法例如是進餘的高密度電漿氧化物⑽，移除的方 T化學機械研磨製程。 之後，圖17 α ^ _ 各自獨立的硫化2了^，的結構如何藉由製程形成 之部分結構的抑=胞。表1中係圖1中的組件與圖1: 16 f.doc/g ^ 表1 、 圖1 圖17 一 位元線80 ^ - -——--- 位元線107 隔離元件70 Ρ+/Ν-型膜層115/110及金屬石夕化 物層120 下電極65 — 導體材料150、較低的水平部分 151、垂直部分152及表面154 ^硫化物記憶體組件60 硫化物記憶體組件171、172 ^ 字元線90 字元線176 更明確地說，請參照圖17，位元線80(請參考圖u相 當於字元線107。在一較佳實施例中，隔離元件70(請參考 圖1)係由/N-型膜層110及P+型膜層115所形成。而金屬 矽化物層120係在隔離元件70(請參考圖1)中的p+型膜層 115及下電極65之間，提供電性連接。加上，下電極65(請 參考圖1)係由具有較低的水平部分151、垂直部分152及 ，面154的導體材料丨5〇所形成。此外，硫化物記憶胞6〇(請 參考圖1)相當於位在導體材料150之表面154與字元線 176之間的硫化物記憶體組件171、172之區域。另外，字 愔鹛4相田於子元線9〇(請參考圖1)。然而，硫化物記 171、172之區域規格係相當於圖13中硫化物記 二：;:考區二餘=體材㈣之垂直部 16)所決〜考圖I3及子兀線176的寬度w(請參考圖 豆中乂另—較佳實施例中’此截面區域繪小於4F2, '則技術所能提供元件規格的最小值。 17 1274401 1248 ltwf.doc/g 另一方面，硫化物記憶體組件相當於硫化物記憶體組 件/171。、172 ’係可在字元線與位元線之間施加一合適電壓 進订彳呆作。也就是說，相當於硫化物記憶體組件171的硫 化物記憶體組件可在位元線1〇6與字元線176之間施加一 5適包壓進行钿作。同樣地，相當於硫化物記憶體組件 的硫化物記憶體組件可在位元線108與字元線176之間施 加一合適電壓進行操作。 接下來圖18係緣示設定及重置一硫化物記憶胞之 溫度波形的曲線圖。其中，垂直軸係用以描述溫度，而水 · 平軸係用以描述時間。關於非結晶重置波形2〇〇，在硫化 物纪憶胞中，施加一非結晶狀態電流脈衝以改變硫化物記 十思體組件的溫度，將會使得硫化物記憶胞被重置，意即硫 化物記憶胞會處於非結晶狀態。而非結晶重置波形2〇〇係 使得硫化物記憶體組件的溫度從周遭溫度八所表示的線 條220上升到最高溫度Tm所表示的線條24〇，以及在時間 ti中將溫度維持在中間的溫度Τχ所表示的線條23()之上。 在圖17中，藉由在位元線1〇8及字元線176之間施加一重 壽 置脈衝’以使相當於硫化物記憶體組件172的硫化物記憶 體組件處於非結晶的狀態。 關於結晶設定波形210，施加一結晶狀態電流脈衝以 改變硫化物記憶體組件的溫度，將會使得硫化物記憶胞被 设定’意即硫化物記憶胞會處於結晶狀態。而結晶設定波 形係使得硫化物記憶體組件的溫度從周遭溫度凡所表示 的線條220在時間k中，上升到中間的溫度τχ所表示的線 18 1274401 12481twf.doc/g 條230但低於最高溫度Tm所表示的線條24〇。在圖17中， 藉由在位元線106及字元線176之間施加一設定脈衝，以 使相當於硫化物記憶體組件171的硫化物記憶體組件處於 結晶的狀態。 在另一較佳貫施例中’溫度Ta所表示的線條220、溫 度Τχ所表示的線條230及溫度Tm所表示的線條mo分別 表示的溫度例如是室溫、150°C及63(TC。此外，時間^ 的範圍例如是在0.1ns〜60ns之間’而時間t2的範圍例如是 在60ns〜100ns之間。 φ 由上述實施例，熟習此技術領域者可清楚的了解在一 積體電路中’如何藉由本發明更容易形成硫化物記憶體元 件。雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明。熟習此技術領域者，依據上述實施利可發展 出許多變化後及修飾後的實施例，並不排除在本發明的範 圍之外。此外，上述實施例所揭露的内容，熟習此技術領 域者可清楚知道其它合併、刪除、替代及修飾之後的實施 例。任何熟習此技藝者’在不脫離本發明之精神和範圍内， 籲 田可作些5午之更動與潤飾，因此本發明之保護範圍當視後 附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1係繪不本發明一較佳實施例中硫化物記憶胞陣列 之一部分的示意圖。 圖2-圖6係繪示本發明一較佳實施例中硫化物記憶胞 前期的步驟的製造流程剖面圖。 19 1274401^,oc/g 圖7-圖12係繪示本發明一較佳實施例中形成下電極 的製造流程剖面圖。 圖丨3係繪示在圖12的結構上沉積一硫化物材料層及 一字元線材料層後的剖面圖。 ，14-圖16係緣示形成字元線的製造流程剖面圖。 别面^。7鱗示指出設定及重置硫化物記憶體之位置的 示意^ /8鱗示設定及重置硫化物記憶胞之溫度波形的 【主要元件符號說明】 5 0 :陣列 55 :硫化物記憶胞 65 70 80 90 100 ·· p型基底 105 ·· N+型膜層 106、107、108 110 : N-型膜層 115 : P+型膜層 120 :金屬矽化物層 125 :緩衝層 60、171、172 :硫化物記憶體組件 下電極 隔離元件 81、107 ··位元線 91 :字元線 109 ··位元線 20 1274401 12481twf.doc/g 130 :氮化矽層 140 :溝渠 145 :高密度電漿氧化物 150 :導體材料 151 :較低的水平部分 152 :垂直部分 153 :較高的水平部分 154 :表面 155 ··氧化層 156 :氧化物間隙壁 160 :溝渠 165 :高密度電漿氧化物 170 :硫化物材料層 171、172、硫化物記憶體組件 175 :字元線材料層 176 :字元線 200 :非結晶重置波形 210 :結晶設定波形 220、230、240 :線條 Ta、τχ、Tm :溫度 t =厚度 tl、t2 :時間 w :寬度The feed oxide ι^5 scale is shown to deposit a high density of electricity on the structure of Figure 14 at the word line m. Its towel, high-density plasma oxide 18 (for example, the high-density plasma oxide (10), the removed square T chemical mechanical polishing process. After that, Figure 17 α ^ _ is independently vulcanized 2, The structure of the structure is formed by the partial structure of the cell. Table 1 is the components in Figure 1 and Figure 1: 16 f.doc / g ^ Table 1, Figure 1 Figure 17 A bit line 80 ^ - - ————-- bit line 107 isolation element 70 Ρ+/Ν-type film layer 115/110 and metal lithium layer 120 lower electrode 65 — conductor material 150, lower horizontal portion 151, vertical portion 152 and surface 154 ^ sulfide memory component 60 sulfide memory component 171, 172 ^ word line 90 word line 176 More specifically, please refer to Figure 17, bit line 80 (please refer to Figure u corresponding to word line 107 In a preferred embodiment, the isolation element 70 (please refer to FIG. 1) is formed of the /N-type film layer 110 and the P+ type film layer 115. The metal telluride layer 120 is attached to the isolation element 70 (please refer to An electrical connection is provided between the p+ type film layer 115 and the lower electrode 65 in FIG. 1). In addition, the lower electrode 65 (please refer to FIG. 1) has a lower horizontal portion 151, The straight portion 152 and the conductor material 面5 of the face 154 are formed. Further, the sulfide memory cell 6 (refer to FIG. 1) corresponds to a sulfide located between the surface 154 of the conductor material 150 and the word line 176. The area of the memory modules 171 and 172. In addition, the word 愔鹛4 is in the sub-line 9〇 (please refer to Fig. 1). However, the area specification of the sulfides 171 and 172 is equivalent to the sulfide in FIG. :;: test area 2 = body (four) vertical part 16) decided ~ test picture I3 and the width of the sub-line 176 w (please refer to the figure in the bean - another preferred embodiment - this section area painted less than 4F2 , 'The minimum size of the component can be provided by the technology. 17 1274401 1248 ltwf.doc/g On the other hand, the sulfide memory component is equivalent to the sulfide memory component / 171. The 172 ' can be in the word line and A suitable voltage is applied between the bit lines. That is, the sulfide memory component corresponding to the sulfide memory component 171 can be applied between the bit line 1〇6 and the word line 176. 5 is suitable for pressing and pressing. Similarly, the sulfide memory component corresponding to the sulfide memory component can be A suitable voltage is applied between the bit line 108 and the word line 176. Next, Fig. 18 is a graph showing the setting and resetting of the temperature waveform of the monosulfide memory cell, wherein the vertical axis is used to describe Temperature, while the water flat axis is used to describe the time. Regarding the amorphous reset waveform 2〇〇, in the sulfide smear cell, a non-crystalline current pulse is applied to change the temperature of the sulfide component. This will cause the sulfide memory cells to be reset, meaning that the sulfide memory cells will be in an amorphous state. The non-crystallographic reset waveform 2 causes the temperature of the sulfide memory component to rise from the line 220 indicated by the ambient temperature eight to the line 24 表示 represented by the highest temperature Tm, and maintains the temperature in the middle in time ti Above the line 23() indicated by the temperature 。. In Fig. 17, the sulfide memory component corresponding to the sulfide memory component 172 is in an amorphous state by applying a heavy duty pulse ' between the bit line 1 〇 8 and the word line 176. With respect to the crystal setting waveform 210, applying a crystallized current pulse to change the temperature of the sulfide memory component will cause the sulfide memory cell to be set to mean that the sulfide memory cell will be in a crystalline state. The crystal setting waveform is such that the temperature of the sulfide memory assembly rises from the line 220 of the ambient temperature in time k to the line represented by the intermediate temperature τ 18 18 1274401 12481 twf.doc/g 230 but lower than the highest The line represented by the temperature Tm is 24 〇. In Fig. 17, a set pulse is applied between bit line 106 and word line 176 to cause the sulfide memory component corresponding to sulfide memory component 171 to be in a crystalline state. In another preferred embodiment, the temperatures indicated by the line 220 indicated by the temperature Ta, the line 230 indicated by the temperature 及, and the line mo indicated by the temperature Tm are, for example, room temperature, 150 ° C and 63 (TC). Further, the range of time ^ is, for example, between 0.1 ns and 60 ns' and the range of time t2 is, for example, between 60 ns and 100 ns. φ From the above embodiment, it is clear to those skilled in the art that the integrated circuit can be understood. In the above, it is easier to form a sulfide memory element by the present invention. Although the invention has been disclosed above in the preferred embodiments, it is not intended to limit the invention. Those skilled in the art will develop many The embodiment after the change and the modification is not excluded from the scope of the present invention. Further, the embodiments disclosed in the above embodiments can be clearly understood by those skilled in the art, and other embodiments after the combination, deletion, substitution and modification are known. Anyone skilled in the art will be able to make some 5 noon changes and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is attached to the application. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram showing a portion of a sulfide memory cell array in accordance with a preferred embodiment of the present invention. Figures 2-6 illustrate a preferred embodiment of the present invention. A cross-sectional view showing the manufacturing process of the step of the pre-vulcanization of the sulfide memory in the embodiment. 19 1274401^, oc/g FIG. 7 to FIG. 12 are cross-sectional views showing the manufacturing process for forming the lower electrode in a preferred embodiment of the present invention. 3 is a cross-sectional view showing a layer of a sulfide material and a layer of a word line material deposited on the structure of Fig. 12. Fig. 14 is a cross-sectional view showing the manufacturing process for forming a word line. The 7 scale indicates the setting and resetting of the position of the sulfide memory. The setting of the / / 8 scale setting and resetting the temperature waveform of the sulfide memory cell [Main component symbol description] 5 0 : Array 55 : sulfide memory cell 65 70 80 90 100 ·· p-type substrate 105 ·· N+ type film layers 106, 107, 108 110 : N-type film layer 115 : P + type film layer 120 : metal telluride layer 125 : buffer layer 60 , 171 , 172 : Sulfide memory component lower electrode isolation element 81, 107 ··bit line 91: word line 109 ·· Elementary line 20 1274401 12481twf.doc/g 130: tantalum nitride layer 140: trench 145: high density plasma oxide 150: conductor material 151: lower horizontal portion 152: vertical portion 153: higher horizontal portion 154: Surface 155 · · Oxide layer 156 : oxide spacer 160 : trench 165 : high density plasma oxide 170 : sulfide material layer 171 , 172 , sulfide memory component 175 : word line material layer 176 : word line 200: amorphous reset waveform 210: crystallization set waveform 220, 230, 240: line Ta, τ χ, Tm: temperature t = thickness tl, t2: time w: width