TWI382454B - Self-aligned cross-point memory fabrication - Google Patents

Description

Self-calibrating cross-point memory manufacturing technology Cross-reference to related applications

This application claims the benefit of priority to the U.S. Provisional Application Serial No. 60/952,996, filed on July 31, 2007, and to the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the present invention. The entire contents of both of the applications are hereby incorporated by reference in their entirety.

Field of invention

The field of the invention relates generally to semiconductor fabrication techniques. In particular, the present invention is directed to fabricating a cross point memory array.

Background of the invention

Nanofabrication techniques involve, for example, very small structural fabrication techniques with features on the nanometer scale or less. One area that has had a considerable impact in nanofabrication technology is the process of integrated circuits. Nano manufacturing technology is becoming more and more important as the semiconductor process industry continues to strive for higher throughput while increasing the number of circuits per unit area formed on a substrate. Nanofabrication technology provides greater process control while allowing the minimum feature size of the resulting structure to shrink. Other areas of development in which nanotechnology has been used include biotechnology, optical technology, mechanical systems, and the like.

An exemplary nanofabrication technique generally refers to compression molding lithography. Exemplary compression lithography processes are described in detail in a number of publications, such as U.S. Patent Application Publication Nos. 2004/0065976 and 2004/0065252, and U.S. Patents. In case No. 6,936,194, these are incorporated herein by reference.

The stamper lithography technique disclosed in each of the above-mentioned U.S. Patent Application Publications and U.S. Patent includes the formation of a relief pattern in an polymerizable layer and a pattern transfer corresponding to the relief pattern. To the base below. The substrate can be positioned on a platform to achieve a desired location to facilitate its patterning. The mold is separated from the substrate by forming a liquid that is present between a mold and the substrate. The liquid is cured to form a patterned layer having a pattern recorded therein that conforms to the shape of the surface of the mold in contact with the liquid. The mold is then separated from the patterned layer whereby the mold is separated from the substrate. The substrate and the patterned layer then undergo a process of transferring a relief image corresponding to one of the patterned layers to the substrate.

Summary of invention

According to an embodiment of the present invention, a process for fabricating a cross-point memory element of a memory array is specifically provided, comprising the steps of: a composite multilayer comprising a substrate and a first resist material layer The structure applies a first lithography step whereby a pattern of the plurality of first channels is formed in the first layer of resist material; applying a first series of etching and deposition steps to be within the first channels Forming a plurality of first conductors on a region of the substrate; applying a series of deposition steps to fill the plurality of first vias with a dielectric material and forming a second resist material layer on the dielectric material to form a modified a composite multilayer structure; applying a second lithography step to the modified composite multilayer structure, whereby a pattern of a plurality of second channels disposed on the plurality of first channels and orthogonal thereto In the first Formed in a second resist material; applying a second series of etching and deposition steps to form the plurality of second vias and electrically interconnecting portions of the plurality of first conductors exposed in the second vias And a third series of etching and deposition steps to form a plurality of second conductors connecting the connectors in the plurality of second channels.

Simple illustration

1 is a cross-sectional view of a stacked material layer in an embodiment; FIGS. 2-3 are cross-sectional views after patterning and etching the layers of FIG. 1; FIGS. 4-7 are second A cross-sectional view of the structure of the structure after depositing a dielectric layer; FIGS. 8-11 are top and cross-sectional views of a multilayer structure according to an embodiment; and FIGS. 12-16 are a multilayer structure according to an embodiment. Top view and cross-sectional view; FIGS. 17-21 illustrate a top view of a multilayer structure according to an embodiment; FIG. 22A illustrates a multilayer structure according to another embodiment; and FIG. 22B is a view of the embodiment of FIG. 22A a top view of the multilayer structure; Fig. 23 is a cross-sectional view of the multilayer structure as shown in Fig. 22B taken along section line M _{1 -} M ₁ '; and Figs. 24-25 illustrate A further embodiment of a conductor strip; Figures 26-27 illustrate yet another embodiment for forming a lower conductor; Figures 28-29 illustrate a further process of the structure in accordance with an embodiment; Figures 30-32 show a A top view and a cross-sectional view of a multilayer structure of an embodiment; FIGS. 33-35 Various views of a multilayer structure after further processing in accordance with an embodiment; Figures 36-40 illustrate various views of a multilayer structure after further processing in accordance with an embodiment; FIGS. 41-45 illustrate an embodiment according to an embodiment Various views of a multilayer structure after further processing; Figures 46-50 show various views of a multilayer structure after further processing in accordance with an embodiment; Figures 51-55 show after further processing according to an embodiment Various views of a multi-layer structure; Figures 56-60 show various views of a multilayer structure after further processing in accordance with an embodiment; and Figures 61-62 are cross-sections that can be fabricated by the embodiments herein A view of the point memory structure.

Detailed description of the preferred embodiment

The cross-point memory structure can be fabricated through three lithography steps including an intermediate lithography step to form a cylinder (connector) connecting the two conductors. The two steps (connector and second conductor) in these lithography steps require sub-resolution overlap. There is also a desire for a cross-point memory device that utilizes self-assembling molecular switching elements. The invention discloses a manufacturing intersection device, wherein the three materials (the first and second conductors and the connecting material) Standard 矽 processing techniques are used for deposition and calibration.

In the present invention, an integration scheme is described in which only two lithography steps are sufficient to produce the intersection structure. For this purpose, this precise (sub-resolution) overlap condition may not exist and the intersection is naturally formed at the intersection of the two conductor layers.

Referring to Figures 61 and 62, the focus of the present invention is to fabricate a cross-point structure using a two-stage lithography process and a self-aligning process, wherein the connector material is formed between the two conductor layers 168 and 124 as a memory component. 148 is formed at the intersection of the two conductors that are generally orthogonal to one another. For one embodiment herein, the lower conductors 124 and the connectors 148 can be fabricated from materials that can be etched using a dry etch (reactive ion etch (RIE)) process and thereby can be removed in an erased manner. In an embodiment, they are manufactured from tantalum. In an exemplary configuration, the lower conductors 124 are aluminum, titanium or other metallic conductors and the connectors 148 are polysilicon. The connectors 148 may also be other materials that act as reversible switches, such as a phase change material, for example, Microelectronics Engineering, Vol. 84, No. 1, January 2007, pages 21-24, Yang et al. The GST material described in "Patterning of Ge ₂ Sb ₂ Te ₅ phase change material using UV nano-imprint lithography" is herein incorporated by reference. The bottom conductor 124 can also be formed by a highly doped germanium instead of a metal. The top conductor 168 can be formed from a variety of etchable metals including, but not limited to, aluminum and copper.

Figure 1 is a cross-sectional view of a multilayer structure 10 suitable for fabricating a cross-point memory structure. The multilayer structure 10 includes a substrate 12, a first conductive layer 14, and a connector or switch material stack layer 16. The substrate 12 can be made up of Material formation includes, but is not limited to, tantalum, gallium arsenide, quartz, fused yttrium, sapphire, organic polymers, siloxane polymers, borosilicate glass, fluorocarbon polymers, or combinations of the foregoing. The first conductive layer 14 may be formed of tungsten. Switching material layer 16 may be formed from a combination of materials including, but not limited to, polycrystalline germanium, chalcogenide, GST, or a material structure (eg, a PN junction) that is combined into a diode.

2 and 3 illustrate a plan view and a cross-sectional view of the multilayer structure 10. The multilayer structure 10 has a pattern formed by etching the first conductive layer 14 and the via or the switching layer 16 to define the multilayer structure 110. Figure 3 is a cross-sectional view of the structure 110 taken along section line A ₁ -A ₁ '. In this view, the pattern is displayed as a series of parallel channels along the direction D ₁ by etching the first conductive material layer 14 and a switch 16 formed by stacking layers 19, 18 to define the grid. The pattern can be formed by using a lithography step in the multilayer structure 110 followed by an etch step that stops at the substrate 12. For the lithography step, any conventional technique, such as photolithography (including G-line, I-line, 248 nm, 193 nm, 157 nm, and 13.2-13.4 nm wavelengths), contact lithography, Electron beam lithography, X-ray lithography, ion beam lithography, atomic beam lithography, and compression lithography can be used. Compression lithography is described in U.S. Patent No. 6,932,934, U.S. Patent Application Publication No. 2004/0124566, U.S. Patent Application Publication No. 2004/0188381, and U.S. Patent Application Publication No. 2004/0211754, all of which are incorporated herein by reference. Into this article.

The etching step for etching the conductive layer 14 in Figures 2 and 3 can use a process as described in J. Electrochem. Soc. 136, 2050 (1989). Oehrlein et al., "Surface Modifications of Electronic Materials induced by Plasma Etching"; Sixth Meeting of the Electrochemical Society Conference Record, Plasma Processing, ECS Proceedings, vol. 87-6, 173 (1987), Saia et al. "Plasma Etching Methods for the Formation of Planarized Tungsten Plugs used in Multilevel VLSI Metallizations"; J. Electrochem. Soc. 135, 2016 (1988) by Balooch et al. "The Kinetics of Tungsten and Tungsten Silicide Films by Chlorine Atoms"; and Springer, "Dry Etching for VLSI" by Van Roosmalen, pp. 121-125 (1991), all of which are incorporated herein by reference.

The etching step used to etch the connector layer 16 in FIGS. 2 and 3 can be performed using a process described in European Patent No. 337,562 and Springer No. 113 by Van Arendonk et al. entitled "Method of Manufacturing a Semiconductor Device". This is described in "Dry Etching for VLSI" by Van Roosmalen, page (1991), all of which is incorporated herein by reference.

4-7 illustrate top and cross-sectional views of the multilayer structure 110 defining a multilayer structure 210 after deposition of a dielectric material 20. Figure 4 is a top plan view showing the channels 19 filled with dielectric material 20 and the various cross-sectional lines. Fig. 5 is a cross-sectional view taken along a section line A _{2 -} A ₂ ' orthogonal to the grid 18. In this view, the channels 19 are filled to the surface 24 of the grid 18 by a dielectric material 20. ₂ FIG. 6 is a cross-sectional view taken along section line B ₂ -B ', wherein only the base body 12 and the dielectric 20 is visible. Fig. 7 is a cross-sectional view taken along section line C ₂ - C ₂ '. In this view, the lower or first conductor 14, base 12 and connector material 16 are visible. Dielectric material 20 can be deposited on multilayer structure 210 by, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputter deposition, spin coating, and dispersion of a liquid. Dielectric material 20 may comprise yttria or any low-k dielectric material. Dielectric material 20 may undergo a chemical mechanical polishing (CMP) process to produce a multilayer structure 210 having a crowned surface 22. Crowned surface 22 is defined by an exposed surface 24 of each grid 18 and an upper surface 27 of dielectric material 20. Portions of dielectric material 20 may be removed using an etching process to form crown surface 22, which is described by Coburn et al., "Some Chemical Aspects of" by IBM J. Res. Develop. 23, 33 (1979). "The Fluorocarbon Plasma Etching of Silicon and its Compounds"; Solid State Technol. 22 (4), 117, (1979) "Some chemical Aspects of the Fluorocarbon Plasma Etching of Silicon and it's Compounds" by Coburn et al.; "Dry Etching for VLSI" by van Roosmalen, page 107 (1991), which is incorporated herein by reference.

8-11 are top and cross-sectional views of the multilayer structure 210 defining a multilayer structure 310 after a second or upper conductive layer 26 has been deposited on the crown surface 22. Fig. 8 is a plan view showing only the conductive layer 26 and various cross-sectional lines. Figure 9 is a cross-sectional view showing the material layers of Figure 5 and the conductive material layer 26 taken along section line A ₃ -A ₃ '. FIG 10 is a cross-sectional view through ₃ -B ₃ of the dielectric layer along section line B 'taken. In this view, only conductive layer 26, dielectric layer 20, and substrate 12 are visible. Figure 11 is a cross section along line C ₃ -C ₃ 'having a cross-sectional view taken through the various layers of material of the channel 18. In this view, the second or upper conductor 26, the connector or switch layer 16, the lower conductor 14 and the substrate are visible. The second conductive layer 26 may be formed of various conductive materials (eg, tungsten). Depending on its composition, the second conductive layer 26 can be deposited on the multilayer structure 210 by processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputter deposition, spin coating, and Spread a liquid.

12-16 are top and cross-sectional views of the multilayer structure 310 defining the multilayer structure 410 after removing a pattern of portions of the upper conductor 26 having a plurality of strips 28 orthogonal to the channels 18. The removed material defines an open channel 29. Figure 12 is a top plan view showing the various cross-sectional lines, strips 28 and lower conductors 14 of the upper conductors 26, and the exposed portions of the dielectric 20. Figure 13 is a cross-sectional view through one of the conductive strips 28 taken along section line A ₄ -A ₄ '. In this view, the substrate 12, the dielectric strip 20, and the channels 18 filled by the connector 16 and the lower conductor 14 are visible. Figure 14 is a cross-sectional view through the channel 18 and the exposed portion of the dielectric strip 20 taken along section line D _{4 -} D ₄ '. Due to the background of the upper conductor strip 28, this view shows the same layers as in Fig. 13. Figure 15 is a sectional view taken along section line B 'taken ₄ -B ₄ through the dielectric strip 20. In this view, the substrate 12, the strips 28 of electrically conductive material 26, and portions of the dielectric material 20 are shown. FIG 16 is a C ₄ -C ₄ 'cross-sectional view taken through the lower conductive paths 18 along section line. In this view, the stack of materials that intersect perpendicularly to form the upper conductor 26, the connector 16, and the lower conductor 14 of a memory component are visible. The pattern formed in the second conductive layer 26 and the switch or connector material stack layer 16 defines the strips or grids 28. The grid 28 extends along a second direction D _{2 that is} orthogonal to the first direction D ₁ shown in FIG. ₂ . The pattern formed in the multilayer structure 410 can be formed using a lithography step followed by an etching step that stops at the first conductive layer 16. The lithography step and the etching steps can be selected from the processes mentioned above with respect to Figures 1-11. A cross-sectional view of the multilayer structure 410 taken along section line A ₄ -A ₄ ' shows that the orthogonal overlap of the first and second conductive layers 14 and 26 is connected by a switch or connector material stack layer 16 to form a memory element.

17-21 illustrate top and cross-sectional views of the multilayer structure 410 defining the multilayer structure 510 after depositing the dielectric material 20 to fill the open channels 29. Figure 18 is a cross-sectional view taken along section line A ₅ -A ₅ '. Because the open channel 29 is not visible in this view, filling the channel 29 with the dielectric material 20 is not shown to be different than the view in FIG. Figure 19 is taken along line D ₅ -D ₅ ', taken through a cross-sectional view of the filling channel 29 of the dielectric 20. In this view, only the dielectric 20, the lower conductor 14, and the substrate 20 are visible. Figure 20 is a cross-sectional view through the dielectric layer taken along section line B ₅ -B ₅ '. The dielectric layer 20 blocks everything except the upper conductor 26 and the cross section of the substrate 12. Figure 21 is a cross-sectional view through the passage 18 and the lower conductor 14 taken along section line C ₅ - C ₅ '. In this view, the orthogonal overlap of the first and second conductive layers 14 and 26 is visible by the switch material stack layer 16 being joined to form a memory device, wherein the open channels 29 are filled with the dielectric material 20 The top of the conductor 26. The multilayer structure 510 shows a top surface 30 having lines of a second conductive layer 26 separated by a dielectric material 20. Figure 21 shows the upper conductors exposed to the surface. In many applications, it may be desirable to cover the surface with a dielectric layer prior to further processing.

Another embodiment for fabricating a cross-point memory structure in a self-calibration process through two lithography steps is described with respect to Figures 22A-60. 22A illustrates a substrate 112 (eg, Si), a first dielectric layer 114 (eg, SiO ₂ or a low dielectric material), an etch stop layer 116 (eg, SiN, SiC, or Si(O)N) and a A multilayer structure of the second dielectric layer 118 (e.g., SiO ₂ ).

Figure 22B is a top plan view of the multilayer structure 100. Fig. 23 is a cross-sectional view of the channel 122 having been etched taken along the section line M _{1 -} M ₁ ' as shown in Fig. 22B. The base 112 may be formed of a material substantially the same as the above-described base 12 and FIG. The channels can be etched through the layers on top of the substrate 112 through appropriate masking and multiple etching steps.

The multilayer structure 100 after a pattern formation is displayed using the first lithography step. A pattern is etched through the first dielectric layer 114, etch stop layer 116 and the second dielectric layer 118 and the grill 120 and V ₁ defines a groove 122 along a first direction of the display section 22B in FIG. The pattern can be formed in the multilayer structure 100 using a first lithography step to define the trenches 122, followed by an etching step selected to stop at the substrate 112. The lithography step and the etching steps can be selected from any of the processes disclosed above with respect to the embodiments described in Figures 1-11.

Figures 24 and 25 illustrate a further embodiment for making the lower conductor strip 124. Fig. 25 is a cross-sectional view taken along the section line M _{2 -} M ₂ ' as shown in Fig. 24. In this embodiment of Fig. 25, in the region of the channel 122, the germanium matrix 112 is first doped to N+ (124). Next, the channel 122 region is doped to a P-type material (126). In this manner, a diode PN junction is formed if it is desired to have the junction memory only allow conduction in one direction when the connector is conductive.

Figures 26 and 27 illustrate yet another embodiment for forming the lower conductor 124. 26 and FIG. 24 is similar to FIG, having along line M ₃ -M ₃ a cross sectional view 'taken. In this embodiment, a material such as aluminum or tungsten may be deposited in the trenches 122 and then subjected to an etching process to form a first conductive layer 124 having a height that does not exceed the height of the etch mask layer 116. Figure 27 shows that the etch stop is removed in the region of the trench 122.

Figures 28 and 29 illustrate views of a further process of the structure of Figure 23 in which multiple layers are deposited to form a multilayer structure 1100. Figure 29 is a plan view and FIG. 28 is ₁ -N ₁ 'is a cross-sectional view taken along line N. First, a dielectric material is used to fill the trenches 122. More specifically, a dielectric material 128 is deposited within the trenches 122 to form a continuous dielectric layer with the first dielectric layer 114 and the second dielectric layer 118, both of which are shown in FIG. Dielectric layer 128 may comprise substantially the same material as first and second dielectric layers 114 and 118 described above with respect to FIG. Hereinafter, this dielectric layer may be referred to as layers 114 and 118 or simply as a single layer 128. A resist layer 130 is then deposited over the dielectric layer 128. Layer 130 may comprise an organic material such as an amorphous carbon or a polymeric resist material. A hard mask layer 132 is then deposited over the resist layer 130. The hard mask layer 132 can comprise materials including, but not limited to, spin-on glass, SiN, and SiC. Another resist layer 134 is then deposited on the hard mask layer 132.

Figure 27 shows that once the lower conductor discussed in Figure 22B-26 is formed The structure 100. As shown in FIG. 29, the dielectric material 128 is deposited within the trenches 122 and over the dielectric stack. At this stage, this dielectric 128 is planarized using one of the processes such as chemical mechanical polishing (CMP). An organic material such as an amorphous carbon or a polymeric resist material is deposited on the dielectric stack including dielectric 128 and etch stop 116. Next, a hard mask film 132 is deposited on layer 130. The hard mask 132 can be a spin-on glass (SOG), SiN, SiC, or the like. The hard mask may also include a double top hard mask that includes a thinner hard mask 134 (e.g., SiN) on top of a thicker hard mask 132 (e.g., SOG). The SiN layer 134 can be made thin enough to facilitate pattern transfer in a lithography process such as compression molding, photolithography, etc., and the lower SOG is made thick enough to allow pattern transfer at least through the A deep amorphous carbon layer 130. A high resolution lithography such as 193 nm or 193 nm immersion or compression lithography or EUV can be used to create a pattern on top of the hard mask (or double top hard mask).

The organic layer 130, the hard mask layer 132, and the resist layer 134 may be deposited to form the multilayer structure 1100 by, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputter deposition, Spin coating and spreading a liquid.

FIGS. 30-32 show a top view and a cross-sectional view of the multilayer structure 1200 after the multilayer structure 1100 is formed in a resist pattern 134 orthogonal to the channel 122. Figure 31 is a view taken along line N ₂ -N ₂ ', and Figure 32 is a cross-sectional view taken along line O ₂ -O ₂ '. The pattern formed in resist layer 134 defines a grid defined by lines 136 and trenches 138. The grids extend in a direction V ₂ orthogonal to the direction V1 shown in Fig. 22. After a first etching step, the trenches 138 may extend only down to the hard mask layer 132. In an embodiment, the pattern 132 can be formed using a stamper mold wherein the resist layer 134 is a formable layer. Therefore, this first step would require removal of the resist layer in the pattern channel 132 and further etching up to the hard mask 132. Figure 32 is a cross-sectional view showing all of the layers of structure 1200 visible. This view of Fig. 32 shows the resist layer 134 removed until the hard mask 132.

Figures 33-35 show various cross-sectional views of the multilayer structure 1300 in which the multilayer structure 1200 is removed after the pattern of the channels 138 is formed in the mask layer 132. Figure 34 along line ₃ -N ₃ 'sectional view taken, along line of FIG. 35 O ₃ -O _3' N-sectional view taken. The pattern formed in the resist layer 132 defines a grid with lines 140 and grooves 142. Line 140 extends in a direction V ₂ that is orthogonal to the direction V1 of channel 122 shown in FIG. After a second etching step, the trenches 142 may extend only down to the organic layer 130. Figure 34 shows a view of all of the layers of structure 1300 being visible. Figure 35 shows the resist layer 134 removed to the organic layer 130.

36-40 show various views of the multilayer structure 1300 in the case where the pattern of the trenches 142 has been etched in the multilayer structure 1300 and the resist layer 132 is removed. 36 is a top plan view of the structure 1300 defining the multilayer structure 1400 with the resist 130 removed after the pattern of the etch trenches 142 is removed through the dielectric layers 114 and 128 in regions that are not blocked by the etch stop layer 116. Figure 37 is a cross-sectional view through the organic layer 130 along the section line N ₄ -N ₄ '. Because this view is through the entire layered structure, all of the layers and the openings through the layer 116 are visible. Figure 38 is a cross-sectional view showing the dielectric 128 removed to the lower conductor 124 along section line P ₄ -P ₄ '. However, all of the layers down to the back of the via 144 of the lower conductor 124 are visible. In this view, the interlayer edge is different from the via 144 itself. Figure 39 is a cross-sectional view along line O ₄ -O ₄ ' showing the lateral grooves 146 down to a side view of the lower conductor 124. Ditch 146 provides the channel to an upper conductor (not shown). In this view, dielectric layer 114 and mask 116 are shown in the background. Fig. 40 is a cross-sectional view of a portion passing through the layer 116 along the section line Q _{4 -} Q ₄ '. Figure 40 provides another view of the trench 146 in which the lower conductor 124 is invisible because it is blocked by the dielectric 128.

The multilayer structure 1400 has a channel 146 and a via 144 adapted to receive a switch or connector material having features suitable for forming a read/write memory component. The connector material is so named because it provides a switchable connection between an upper conductor (not shown) and the lower conductor 124. Figure 41 is a top plan view of the foundation of the multilayer structure 1400 after depositing a connector layer 148 to form the multilayer structure 1500. In this view, the connector material 148 is shown filled over the exposed portion of layer 116 (see Figure 36) and through the channel 146 down to the via 144 of the lower conductor 124. Figure 42 is a cross-sectional view orthogonal to the lower conductor 124 along the section line N ₅ -N ₅ '. Because this view passes through the entire layered structure, all remaining layers and openings through the layer 116 are visible. FIG 43 is a ₅ 'through the passage cross-sectional view taken along section line P ₅ -P 146, and the linker material 148 just deposited. The connector material 148 is shown extending to the surface of the structure and down to the lower conductor 124. Figure 44 is a cross-sectional view through the lower conductor 124 taken along line O ₅ -O ₅ '. In this view, the connector material 148 is shown extending to the surface of the structure 1500 and down into the via 144 of the lower conductor 124. Cross sections of the organic layer 130 and the dielectric layer 128 on each side of the channels 146 having the connector material 148 are also visible. FIG 45 is a sectional view of the layers of such lower conductor 124 along a line ₅ -Q ₅ 'spaced taken through section line Q. In this view, the via 144 down to the lower conductor 124 is blocked by the cross-section of layers 116 and 128 and is not visible. This portion of the connector material 148 that is in the channel 146 and that extends to the surface of the structure 1500 is also visible. The connector layer 148 can be deposited on the multilayer structure 1400 by processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputter deposition, spin coating, and dispersion of a liquid.

Figure 46 is a top plan view of the multilayer structure 1500 after defining portions of the interconnect layer 148 after undergoing an etch chemistry to define the multilayer structure 1600. In this view, the connector material 148 has been etched away except in all places except the via 144 of the lower conductor 124. Figure 47 is a cross-sectional view orthogonal to the lower conductor 124 along the section line N ₆ -N ₆ '. Since this view is through the entire layered structure, all remaining layers and openings through the layer 116 are visible and the same layers as in Figure 42 are shown. FIG 48 is a cross section along line P ₆ -P ₆ 'show the connection of the dielectric material 148 is filled up to the next cross-sectional view of the conductor layer 124 via the lower 144. In this view, all of the layers down to the dielectric layer 144 of the lower conductor 124 are visible, and the interlayer edges are different from the filled via 144 itself. Figure 49 is' a view taken along line O ₆ -O _6. In this view, the connector material 148 fills the via to the surface of the etch stop layer 116. The dielectric layers 128 and layers 130 separating the channels 146 are also visible in this view. FIG 50 is a sectional view of the layers of such lower conductor 124 along line ₆ -Q ₆ 'spaced taken through section line Q. In this view, the cross-section of layers 116 and 128 blocks the view of the connector material 148 that fills down the via 144 of the lower conductor 124. Portions of the connector material 148 can be removed to form a crowned surface 150 as shown in FIG. The crowned surface 150 in FIG. 48 is defined by an exposed surface 152 of the etch stop layer 116 and an upper surface 154 of the connector material 148.

Figure 51 is a top plan view of the multilayer structure 1600 defining a multilayer structure 1700 after an upper conductor 168 is deposited over the channel 146 orthogonal to the lower conductor 124. In this view, the upper conductor 168 fills the channel 146 substantially to the surface of the organic layer 130. Figure 52 is a cross-sectional view of the layers passing through the spaced channels 146 along section line N ₇ -N ₇ '. Figure 53 is a cross-sectional view through the upper conductor 168 taken along section line P ₇ -P ₇ '. In this view, the upper conductor 168 is blocked from seeing the layers separating the channels 146. Figure 54 is a cross-sectional view through the lower conductor 124 taken along line O ₇ -O ₇ '. In this view, the upper conductor from the connector material 148 to the top of the organic layer 130 is visible. FIG 55 is a cross sectional view of the layers of such lower conductor 124 along a ₇ -Q ₇ 'spaced taken through section line Q. In this view, the portion of the upper conductor 168 that extends into the top of layer 130 in channel 146 is visible. The lower conductor 124 and the connector material 148 are blocked from view. The upper or second conductive layer 168 can comprise copper and can be deposited on the multilayer structure 1700 by, for example, but not limited to, electroplating.

Figure 56 is a top plan view of the multilayer structure 1700 after the plurality of structures 1700 have been ground through a CMP process to remove portions of the organic layer 130 and the conductor layer 168. Figure 57 is a cross-sectional view of the cross section of the layer passing through the spaced channel 146 along section line N ₈ -N ₈ '. Figure 58 is a cross-sectional view through the upper conductor 168 taken along section line P ₈ -P ₈ '. In this view, the upper conductor 168 is blocked from seeing the layers separating the channels 146. Figure 59 is a cross-sectional view through the lower conductor 124 taken along section line Q ₈ -Q ₈ '. In this view, the upper conductor from the connector material 148 to the top of the organic layer 148 is visible. Figure 60 is a cross section along line Q ₈ -Q ₈ 'cross-sectional view taken through the lower section of the layers in these separated conductor 124. In this view, the portion of the upper conductor that extends into the top of layer 128 in channel 146 is visible. The lower conductor 124 and the connector material 148 are blocked from view. Portions of the second conductive layer 168 and the organic layer 130 can be removed, whereby a crowned surface 158 can be defined, as shown in Figures 59 and 60. The crowned surface 158 can be defined by an exposed surface 160 of the dielectric layer 128 and an upper surface 162 of the second conductive layer 148.

The disclosed method essentially creates a connector 148 where they intersect when they overlap orthogonally between the top and bottom conductors (168 and 124, respectively). Thus, if the two conductor layers have regions that need to be isolated from each other, for example, the conductor layers are connected to regions of other portions of the memory circuit, these regions may need to be processed in different ways. For example, on a direction axis (eg, the X axis), the lower conductors may not extend beyond the intersection area, and on another orthogonal axis (eg, the Y axis), the upper conductors may not extend. In this way, the two conductor layers can be isolated for further processing.

The embodiments of the invention described above are examples. Many variations and modifications can be made to the disclosures listed above, while still being within the scope of the present invention. Inside. Therefore, the scope of the invention should not be construed as being limited by the scope of the appended claims.

10‧‧‧Multilayer structure

12‧‧‧ base

14‧‧‧First conductive layer, lower conductor

16‧‧‧Connector or switch material stack

18‧‧‧Grill, passage

19‧‧‧ parallel channel

20‧‧‧Dielectric material, dielectric strip

22‧‧‧ crown surface

24‧‧‧ exposed surface

26‧‧‧Second or upper conductive layer, upper conductor, conductive material layer

27‧‧‧ upper surface

28‧‧‧Articles, conductive strips, grilles

30‧‧‧ top surface

100‧‧‧Multilayer structure

110‧‧‧Multilayer structure

112‧‧‧ base

114‧‧‧First dielectric layer

116‧‧‧etch stop layer, etch mask layer

118‧‧‧Second dielectric layer

120‧‧‧ grille

122‧‧‧ditch, passage

124‧‧‧lower conductor and conductor layer

128‧‧‧Dielectric materials

130‧‧‧resist layer, amorphous carbon layer, organic layer

132‧‧‧Hard mask, hard mask

134‧‧‧resist layer, thin hard mask, SiN layer

136‧‧‧ line

138‧‧‧ditch, passage

140‧‧‧ line

142‧‧‧ditch

144‧‧ ‧ layer

146‧‧‧ lateral grooves, passages

148‧‧‧Connector materials

150‧‧‧ crown surface

152‧‧‧ exposed surface

154‧‧‧ upper surface

158‧‧‧ crown surface

160‧‧‧ exposed surface

162‧‧‧ upper surface

168‧‧‧Upper conductor and conductor layer

210‧‧‧Multilayer structure

310‧‧‧Multilayer structure

410‧‧‧Multilayer structure

510‧‧‧Multilayer structure

1100‧‧‧Multilayer structure

1200‧‧‧Multilayer structure

1300‧‧‧Multilayer structure

1400‧‧‧Multilayer structure

1500‧‧‧Multilayer structure

1600‧‧‧Multilayer structure

1700‧‧‧Multilayer structure

1 is a cross-sectional view of a stacked material layer in an embodiment; FIGS. 2-3 are cross-sectional views after patterning and etching the layers of FIG. 1; FIGS. 4-7 are second A cross-sectional view of the structure of the structure after depositing a dielectric layer; FIGS. 8-11 are top and cross-sectional views of a multilayer structure according to an embodiment; and FIGS. 12-16 are a multilayer structure according to an embodiment. Top view and cross-sectional view; FIGS. 17-21 illustrate a top view of a multilayer structure according to an embodiment; FIG. 22A illustrates a multilayer structure according to another embodiment; and FIG. 22B is a view of the embodiment of FIG. 22A A top view of the multilayer structure; Fig. 23 is a cross-sectional view of the multilayer structure as shown in Fig. 22B taken along section line M ₁ -M ₁ '.

Figures 24-25 illustrate a further embodiment of the manufacture of the lower conductor strip in accordance with an embodiment; Figures 26-27 illustrate yet another embodiment for forming the lower conductor; and Figures 28-29 illustrate the structure in accordance with an embodiment. a further process view; FIGS. 30-32 show a top view and a cross-sectional view of a multilayer structure in accordance with an embodiment; Figures 33-35 show various views of a multilayer structure after further processing in accordance with an embodiment; Figures 36-40 show various views of a multilayer structure after further processing in accordance with an embodiment; The drawings show various views of a multilayer structure after further processing in accordance with an embodiment; Figures 46-50 show various views of a multilayer structure after further processing in accordance with an embodiment; Figures 51-55 show Embodiments Various views of a multilayer structure after further processing; Figures 56-60 show various views of a multilayer structure after further processing according to an embodiment; and Figures 61-62 are perforations permissible herein A view of a cross-point memory structure manufactured by way of example.

10‧‧‧Multilayer structure

12‧‧‧ base

14‧‧‧First conductive layer

16‧‧‧Connector or switch material stack

Claims (7)

A process for fabricating a cross-point memory component of a memory array, the method comprising the steps of: applying a first lithography step to a composite multilayer structure comprising a substrate and a first resist material layer, Forming a pattern of the plurality of first channels in the first resist material layer; applying a first series of etching and deposition steps to form a plurality of regions on a region of the substrate in the first channels a conductor; applying a series of deposition steps to fill the plurality of first channels with a dielectric material and forming a second layer of resist material on the dielectric material to form a modified composite multilayer structure; The composite multilayer structure applies a second lithography step whereby a pattern of a plurality of second channels disposed over the plurality of first channels and orthogonal thereto is formed in the second resist material Applying a second series of etching and deposition steps to form the plurality of second vias and a plurality of interconnects electrically interconnecting portions of the plurality of first conductors exposed in the second vias; and applying one third a column etching and deposition step to form a plurality of second conductors connecting the connectors in the plurality of second channels, wherein the second resist material layer is a composite of multiple resist layers, comprising: a first layer of organic resist material over the dielectric material filling the plurality of first channels; a second layer of hard mask material disposed over the first layer of organic resist material; A third layer of resist material disposed over the second layer of hard mask material. The process of claim 1, wherein the second lithography step forms the second channel in the third layer of resist material disposed over the second layer of hard mask material. pattern. The process of claim 2, wherein the second series of etching and depositing steps comprises: etching the pattern of the second channels through a first etching step of the third layer of resist material; etching the Waiting for the pattern of the second channel to pass through a second etching step of the second resist material layer; etching away one of the remaining third layer of resist material; a third etching step; etching the pattern of the second channel a fourth etching step of the first resist material layer; etching the first conductor in the second channel in the region of the dielectric material until an etch stop layer is removed and stopping at the etch stop layer a fifth etching step of one of the etch stop materials in the remaining region, wherein the unpatterned portion of the first resist material layer is retained on the surface of the dielectric material layer; in the plurality of second channels Depositing a connector material; and etching away any residual linker material present on the first layer of resist material and excess linker material in the plurality of second channels to isolate through the etch stop layer Extended to A sixth step of the one of the connector materials of the first conductor. A process for fabricating a cross-point memory component of a memory array, the method comprising the steps of: applying a first lithography step to a composite multilayer structure comprising a substrate and a first resist material layer, Forming a pattern of the plurality of first channels in the first resist material layer; applying a first series of etching and deposition steps to form a plurality of regions on a region of the substrate in the first channels a conductor; applying a series of deposition steps to fill the plurality of first channels with a dielectric material, removing a grinding step of any of the conductive material extending over the dielectric material, and forming a second on the dielectric material a layer of resist material to form a modified composite multilayer structure; applying a second lithography step to the modified composite multilayer structure, thereby being disposed over and orthogonal to the plurality of first channels a pattern of the plurality of second channels is formed in the second resist material; applying a second series of etching and deposition steps to form the plurality of second channels and causing the plurality of first conductors a plurality of connectors electrically connected to the portions of the second channels; and applying a third series of etching and deposition steps to form a plurality of second conductors connecting the connectors in the plurality of second channels The third series of etching and deposition steps includes: depositing a layer of conductive material to fill the plurality of second vias substantially to a surface of the first resist material layer; and removing an etch of the first resist material step. A cross-point memory component for fabricating a memory array The process includes the steps of: applying a first lithography step to a composite multilayer structure including a substrate and a first resist material layer, wherein a pattern of the plurality of first channels is in the first resist Forming a layer of material; applying a first series of etching and deposition steps to form a plurality of first conductors on a region of the substrate in the first channels; applying a series of deposition steps to fill the materials with a dielectric material a plurality of first channels, and forming a second resist material layer on the dielectric material to form a modified composite multilayer structure; applying a second lithography step to the modified composite multilayer structure A pattern of a plurality of second channels disposed over and orthogonal to the plurality of first channels is formed in the second resist material; applying a second series of etching and deposition steps to form the plurality of a second channel and a plurality of connectors electrically interconnecting portions of the plurality of first conductors exposed in the second channels; and applying a third series of etching and deposition steps to the plurality of second Forming inside the channel a plurality of second conductors connected to the connecting body, wherein the composite multilayer structure comprises: a substrate; a first dielectric layer disposed on the substrate; an etch stop layer disposed on the first dielectric layer; a second dielectric layer on the etch stop layer; and the first resist material layer disposed on the second dielectric layer; and wherein the modified composite multilayer structure comprises: a substrate; a plurality of first conductors formed on the substrate; a connector material on each of the plurality of first conductors; and the first dielectric layer deposited on the plurality of first channels; Depositing a second layer of conductor material on a surface of one of the first dielectric material and one surface of the connector material; and the second layer of resist material; and wherein the second series of etching and deposition steps comprises: etching the a pattern of the second pass through the first etching step of the second resist material layer; and etching the pattern of the second channels through the second etching step of the second layer of conductor material; and And depositing a dielectric in the plurality of second channels to isolate one of the plurality of second conductor deposition steps. A process for fabricating a cross-point memory component of a memory array, the method comprising the steps of: applying a first lithography step to a composite multilayer structure comprising a substrate and a first resist material layer, Forming a pattern of the plurality of first channels in the first resist material layer; applying a first series of etching and deposition steps to form a plurality of regions on a region of the substrate in the first channels a conductor; applying a series of deposition steps to fill the plurality of first channels with a dielectric material, and forming a second layer of resist material on the dielectric material to form a modified composite multilayer structure; Applying a second lithography step to the modified composite multilayer structure, whereby a pattern of the plurality of second channels disposed above and orthogonal to the plurality of first channels is at the second Formed in the etched material; applying a second series of etching and deposition steps to form the plurality of second vias and a plurality of connections electrically interconnecting portions of the plurality of first conductors exposed in the second vias And applying a third series of etching and deposition steps to form a plurality of second conductors connecting the connectors in the plurality of second channels, wherein the composite multilayer structure comprises: a substrate; disposed on the substrate a first dielectric layer; an etch stop layer disposed on the first dielectric layer; a second dielectric layer disposed on the etch stop layer; and the first resist disposed on the second dielectric layer a material layer; and wherein the modified composite multilayer structure comprises: the substrate; a plurality of first conductors formed on the substrate; and a connecting body material on each of the plurality of first conductors; The deposition on the first channel a dielectric layer; a second layer of conductor material deposited on a surface of one of the first dielectric material and a surface of the connector material; and the second resist material layer; and wherein the third series of etching and deposition The step includes: depositing a material to fill the plurality of second channels substantially to the a deposition step of one surface of the second layer of conductor material; and an etching step of removing any residual dielectric material on the second layer of conductor material. The process of claim 6, further comprising a step of polishing a surface of the plurality of second conductors and the dielectric material separating the plurality of second conductors.