TW200301480A - Thin film magnetic memory device writing data with bidirectional current - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide constitution of a thin film magnetic memory device in which a data write-in current in accordance with a write-in data level can be supplied with simple circuit constitution. SOLUTION: One end of a bit line BL of a selection column is coupled electrically to a corresponding current feedback wiring RL by write-column selecting gates WCSGo and WCSGe turned on selectively in accordance with a column selection result. A data write-in circuit 51 sets the other end of the bit line BL of the selection column and the other end of the current feedback wiring RL to power source voltage Vcc and ground voltage GND respectively in accordance with a level of write-in data DIN through data buses Dbo, Dbe and an inversion data bus/WDB.

Description

200301480 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a thin film magnetic memory device, and more specifically, it relates to: a magnetic tunnel junction (MTJ: Magnet ic Tunnel Junction) Random access memory of the memory unit. [Previous Technology] MRAM (Magnetic Random Access Memory) components have attracted attention in memory devices that can permanently store data with low power consumption. The MRAM module is a memory device that uses permanent memory data of a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit, and can be randomly accessed for each thin film magnetic body. In particular, in recent years, the performance of MR AM devices has been dramatically improved by using tunnel magnetoresistive elements that use thin film magnets of magnetic tunnel junction (MTJ: Magnetic Tunnel Junction) in memory cells. The report on MRAM components including: a memory cell with a magnetic tunnel junction is shown in the following technical literature.

Roy Scheuerline et.al A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell, 2000 IEEE ISSCC Digest of Technical Papers, TA7.2, pl28-129. M. Durlam et.al Nonvolatile RAM based on Magnetic Tunnel Junction Elements ", 2000 IEEE ISSCC Digest of Technical Papers, TA7.3, pl30-131.

Peter K. Naji et.al A 256kb 3.0V 1T1MTJ

2075-5330-PF (Nl); Ahddub.ptd Page 5 200301480 V. Description of the invention (2) ---

Nonvolatile Magnetoresistive RAMM, ISSCC Digest of

Technical Papers, TA7 · 6, ρ122-123. Figure 2 1 shows the structure of a magnetic tunnel junction surface (also referred to as "MTJ memory unit"); = Zao Fan (refer to Figure 21 below: 'MTJ memory unit includes: tunnel magnetoresistive element tmr' which The resistance changes according to the level of the memory data; and the access element ATR is used to form a path for the data read current Is through the tunnel magnetoresistive element when the data is read. The access element ATR is represented by the electric field The effect type 1 electric body is formed, and the access element ATR is also referred to as an access transistor hereinafter. The access transistor ATR is connected between the tunnel magnetoresistive element TMR and a fixed voltage (ground voltage GND). For the MTJ memory cell, the write character line 写 [is used to indicate data write; the read character line RWL is used to perform data read; and the bit line BL is used for data read and data write The data line of the electrical signal corresponding to the data level of the transmitted and memorized data. Figure 22 is a conceptual diagram illustrating the data read operation from the M TJ memory unit. Referring to Figure 22, the tunnel magnetoresistive element TMR has a ferromagnetic layer (Hereinafter also referred to as "fixed magnetization" ") FL, which has a fixed magnetization direction; a ferromagnetic layer (hereinafter also simply referred to as a" free magnetization layer ") VL, is magnetized in the direction of an externally applied magnetic field; and an anti-ferromagnetic layer AFL. In the fixed magnetization layer FL A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the magnetization layer VL and the magnetization layer VL. The magnetization layer VL is magnetized in the same direction as the fixed magnetization layer FL or in the opposite direction according to the level of the written data.

2075-5330-PF (Nl); Ahddub.ptd Page 6 200301480 V. Description of the invention (3). A magnetic tunnel junction is formed by using the fixed magnetization layer FL, the track barrier τb, and the free magnetization layer VL. When the data item is released, the access transistor is turned on in accordance with the activation of the read word line RWL. Therefore, the data read current s can be made to flow to the bit line BL to the tunnel magnetoresistive element TMR to the access transistor ATR to the ground voltage GND. The resistance of the track magnetoresistive element TMR varies according to the relative relationship between the respective magnetization directions of the fixed magnetization layer j? L and the free magnetization layer VL. Specifically, the resistance of the tunneling magnetoresistive element TMR is the same (parallel) when the magnetization direction of the fixed magnetization layer FL and the magnetization direction of the free magnetization layer VL are opposite (parallel). Small. Therefore, 'if the free magnetization layer VL is magnetized in accordance with the direction of the memory data', the voltage change of the data readout current IS at the tunnel magnetoresistive element TMR varies according to the memory data level. Therefore, for example, after pre-charging the bit line BL to a fixed voltage, if the data read current is allowed to flow to the tunnel magnetoresistive element TMR ', by detecting the voltage of the bit line BL, the MT j memory cell can be read. Memory data. Figure 23 is a conceptual diagram illustrating the data writing operation for the MT J memory unit.

Referring to Fig. 23, at the time of data writing, the read word line RWL becomes inactive 'and the access transistor ATR becomes non-conductive. In this state, the data write currents used to magnetize the free magnetization layer VL in the direction in which the data are written respectively flow to the writing word line WWL and the bit line BL. The free magnetization layer vL is determined according to the data writing current flowing through the writing word line WWL and the bit line BL.

2075-5330-PF (Nl); Ahddub.ptd 200301480 V. The magnetization direction of the invention description (4) Figure 24 illustrates the data write current and the magnetoresistive element of the tunnel magnetoresistive element when writing data to the MT J memory cell. Conceptual diagram of the relationship between the magnetization directions. Referring to FIG. 24, the horizontal axis Η (EA) indicates a magnetic field acting on the free magnetization layer VL in the tunnel magnetoresistive element TMR in the direction of an easy axis (EA: Easy Axis). The 'vertical axis H (HA) represents a magnetic field acting on the free magnetization layer VL in the direction of a hard magnetization axis (HA: Hard Axis). The vertical axis h (HA) and the horizontal axis H (EA) each correspond to one of two magnetic fields generated by the current flowing through the bit line BL and the writing word line WWL, respectively. In MTJ memory cells, the fixed magnetization direction of the fixed magnetization layer is along the easy magnetization axis, and the free magnetization layer VL follows the level of the memory data (,, 1 ”and π 0 π), along the direction of the easy magnetization axis, and The fixed magnetization layer FL is magnetized in parallel (same) or anti-parallel (opposite) directions. Hereinafter, in this patent specification, R1 and R0 (but 'Rl> R0) are used to indicate two kinds of magnetization directions of each and the free magnetization layer VL. Corresponds to the resistance of the tunnel magnetoresistive element TMR. The MTj memory unit can store 1-bit data (π Γ and " 0Π) corresponding to the two types of magnetization directions of the free magnetization layer VL. The magnetization direction can only be rewritten if the sum of the applied magnetic fields η (E a) and H (HA) reaches the area outside the star-shaped characteristic line shown in the figure. The magnetic field corresponds to the strength of the region inside the star-shaped characteristic line, and the magnetization direction of the free magnetization layer is unchanged. As shown by the star-shaped characteristic line, by applying a magnetic field in the direction of the axis of the hard magnetization to the free magnetization layer VL, Reduces magnetic change along the easy magnetization axis Required

200301480 Fifth, the magnetization threshold of invention description (5). In the case of designing the operating point when data is written as shown in the example of FIG. 24, in the MTJ memory unit which is the object of data writing, the data writing magnetic field in the direction of the easy magnetization axis is designed so that its intensity becomes 1 ^ . That is, the value of the data write current flowing through the bit line BL or the writing word line WWL is designed so that the lean magnetic field is obtained. In general, the magnetic field is expressed by the sum of the switching magnetic field Hsw and the edge limit ΔΗ required for switching the magnetization direction. That is expressed as Hwr = Hsw + ΔΗ. In addition, in order to rewrite the memory data of the MT J memory unit, that is, the magnetization direction of the tunnel magnetoresistive element TMR, it is necessary to write data that has been positioned above the target current to both the writing word line W W L and the bit line BL. Therefore, the free magnetization layer VL in the tunnel magnetoresistive element TMR is magnetized in a direction parallel or opposite (anti-parallel) to the fixed magnetization layer FL according to the direction in which the data is written in the magnetic field along the easy magnetization axis direction (EA). The tunnel magnetoresistive element TMR—degree of writing magnetization direction ', that is, the memory lean of the early memory of MTJ memory, is maintained until a new lean write is performed. Therefore, the resistance of the tunnel magnetoresistive element TMR changes according to the magnetization direction that can be rewritten by using the applied data to write the magnetic field. The levels (M Γ and π 0 ") correspond to each other and can perform permanent data memory. Therefore, in the MARA module, when data is written, it is necessary to reverse the magnetization direction of the tunnel magnetoresistive element TMR in the MTJ memory unit selected as the data writing target. Therefore, it is necessary to control the direction of the data writing current flowing to the writing word line WWL and the bit line BL according to the level of the written data. Thus, providing

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Writing data into the data ^ The structure of the chip size booster circuit is complicated, and the problem of π of the MARA device occurs. [Summary of the Invention] The present invention is designed to provide a circuit structure with a simple stream of 0, which can provide data to be written according to the configuration data level of a thin-film magnetic memory device. The 'self-memory device' includes: a column of multiple memories applied in a single field, each of which is memorized in response to the first and second data written into the magnetic memory unit ^ person's material; the word lines for plural writing, The plural should be recorded in the first setting of the magnetic field, and the first data write line will be generated in the selected row, and the write current will flow in the predetermined direction respectively; Set, in the selected row, make the second data write current of the second data write field of the material flow in accordance with the write "direction; and the wiring for the complex current feedback along the same direction as the complex bit = line Set; each element line corresponds to one of the plurality of current feedback wirings, and the second data write current flows between one end side of the bit line suitable for electrical connection and the corresponding current feedback wiring. So this The main advantage of Ming is that in the thin film magnetic memory device, the voltage setting on the other end side of the bit line and the corresponding current feedback wiring according to the selection line connected between one end can be controlled in the bit line of the selection line. The direction of the current flowing on the line. As a result, the circuit configuration for controlling the direction of the data write current in accordance with the data write level can be simplified.

200301480 V. Description of the invention (7) A thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory cells arranged in a row and row shape, each of which is stored in response to the application of the first and second data writing magnetic fields. Data; word lines for plural writing, each corresponding to a row of a plurality of memory cells, in a selected row so that a first data writing current that generates the first data writing magnetic field flows in a predetermined direction; a plurality of bit lines, The setting corresponding to each of the plurality of memory cell rows, in the selection row, causes the second data writing current that generates the second data writing magnetic field to flow in the direction according to the written data; the plurality of first row selection lines are respectively set at Form a row block of K (K: integer of 2 or more) each memory cell row corresponding to different row addresses; K second row selection lines are used to select the corresponding K memories in each row block One of the unit cell rows; the row decoder selectively activates one of the plural first row selection lines and one of the K second row selection lines according to the row selection result; And data writing circuit, according to the plurality of first row selection lines and the K second row selection lines, one end side and the other end side of the bit line of the selection row are set to write data according to the first and second voltages, respectively. Each side. This thin-film magnetic memory device executes row selection by using a combination of row block selection each composed of a plurality of memory cell rows and selection of memory cell rows in each row block, which can reduce signals required for row selection. Number of wiring. The thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory units arranged in a row and shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; Lines, each corresponding to a plurality of memory cell columns, are set in the select column so that

2075-5330-PF (Nl); Ahddub.ptd Page 11 20031480 V. Description of the invention (8) The first data writing current of the first data writing magnetic field flows in a predetermined direction; the plurality of first bit lines, each A setting corresponding to a plurality of memory cell rows; and a data writing circuit, in a selection row, among the corresponding first bit lines and a portion corresponding to the selection memory cell, so that the second data writing magnetic field is generated The second data write current flows in the direction in which the data is written; it includes a plurality of bit line driver sections, and each row of the plurality of memory cell rows is respectively corresponding to the first end on the corresponding first bit line. Corresponding to the node, the second node corresponding to the other end side, and at least one intermediate node; in the selection row, one of the plurality of bit line driver sections is located at both ends of the part corresponding to the selection memory cell Two corresponding nodes on the first bit line are set to each of the first and second voltages according to the written data. In this thin film magnetic memory device, in the bit line of the selection row, the data writing current can flow only to a part of the interval corresponding to the selection memory cell. Therefore, the path of the data writing current can be made low-resistance, and the required data writing current can be easily supplied during low-voltage operation, and the data writing operation can be speeded up. In addition, erroneous writing of data in the memory cells of the non-selected memory block of the selected row can be suppressed. The thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory units arranged in a row and shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; Lines, each corresponding to a plurality of memory cell rows, in the selected row, the first data writing current that causes the first data writing magnetic field to flow in a predetermined direction; a plurality of bit lines, each and a plurality of memory cells Line corresponding settings,

2075-5330-PF (Nl); Ahddub.ptd Page 12 20031480 V. Description of the invention (9) The current of writing the second data to the second data writing magnetic field in the selection exercise order is in accordance with the direction of writing the data Flowing; and a writing word line driving circuit, in the selection row, causing the first data write current to flow in at least a portion corresponding to the writing word line; the writing word line driving circuit selects Column, corresponding to the first node corresponding to the one end side, the second node corresponding to the other end side, and at least one of the intermediate nodes on the corresponding writing character line, two of the portions corresponding to the selected memory unit The two nodes on the side are each one of the first and second voltages. In this thin film magnetic memory device, in the writing word line of the selection line, the data writing current can flow only to a portion corresponding to the selection memory cell. Therefore, the path of the data writing current can be reduced in resistance, and the required data writing current can be easily supplied during low-voltage operation, and the data writing operation can be speeded up. In addition, erroneous writing of data to memory cells in non-selected memory blocks can be suppressed. The thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory units arranged in a row and shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; Lines, each corresponding to a plurality of memory cell rows, in the selected row, the first data writing current that causes the first data writing magnetic field to flow in a predetermined direction; a plurality of bit lines, each and a plurality of memory cells The corresponding setting of the row, the second data writing current that generates the second data writing magnetic field is selected to flow in the direction according to the written data; and the word line driving circuit for writing is in the selected column, corresponding to At least a part of the writing character lines causes the first data writing current to flow; each writing character line is at an intermediate node

2075-5330-PF (Nl); Ahddub.ptd Page 13 20031480 V. Description of the invention (ίο) and first voltage connection; the word line drive circuit for writing includes first and second drive switches, in the complex memory The body unit columns are respectively corresponding to the first node corresponding to one end side and the second node corresponding to the other end on the corresponding writing character line; in the selection column, the first and second driving switches One of them is selected according to the position relationship between the selected memory cell and the intermediate node, and the corresponding node is connected to the second voltage. The thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory units arranged in a row and shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; Lines, each corresponding to a plurality of memory cell columns, in a selected row, the first data writing current that causes the first data writing magnetic field to flow in a predetermined direction; the plurality of first and second bit lines, each The setting corresponding to the plurality of memory cell rows, in the selection exercise order, the second data writing current that generates the second data writing magnetic field flows in the direction according to the written data; the selection switch, and each row of the plurality of memory cell rows. Corresponding settings are used to electrically connect one end side of the corresponding first and second bit lines in the selection line; and a data writing circuit that, when data is written, the first corresponding to the selection line And the other end side of the second bit line is set to each of the first and second voltages according to the written data; each wiring layer is used on a different wiring layer than the upper layer side of the plurality of memory cells Each of the first and second bit lines is provided from the formed first and second metal wiring lines, and the first and second bit lines corresponding to the same memory cell row are arranged in a predetermined area in the vertical direction to cross in the vertical direction. This thin-film magnetic memory device can electrically connect the data writing current to one end side according to the direction of the reciprocating current.

2075-5330-PF (Nl); Ahddub.ptd Page 14 200301480 V. Description of the invention (11) The first and second bit lines of the selection line. Therefore, it is possible to simplify the circuit structure that controls the direction of the data write current in accordance with the write data level. In addition, because the respective reverse current flows in the first and second bit lines adjacent to each other in the up and down direction, the magnetic noise generated from the first and second bit lines of the selected row is weakened in other memory cells. Directional effect. Therefore, it can reduce the influence of magnetic noise, prevent data from being written by mistake, and stabilize the operation. The thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory units arranged in a row and shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; Lines, each corresponding to a plurality of memory cell rows, in a selected row such that the first data write current that generates the first data write magnetic field flows in a predetermined direction; and a plurality of first and second bit lines, The settings corresponding to the rows of the plurality of memory cells are used to select the second data writing current that generates the second data writing magnetic field to flow in the direction of writing the data; used on the upper side of the plurality of memory cells The first and second metal wirings formed by different wiring layers are provided with respective first and second bit lines, and the first and second bit lines corresponding to the same memory cell row are arranged above and below a predetermined area in the vertical direction. The directions intersect; also includes: a data writing circuit, which selects the distance of the memory cells from the sum of the first and second bit lines corresponding to the selected row when the data is written One end side of the relatively short bit line is set to one of the first and second voltages, and the other end side of the bit line is set to one of the first and second voltages. The other side. This thin-film magnetic memory device uses one of the first and second bit lines of the selection line to approach one of the selection memory cells, so that the direction can be

2075-5330-PF (Nl); Ahddub.ptd Page 15 200301480 V. Description of the invention (12) Data written into the data write current flows. Therefore, in the selection line, the data writing current will not flow to the wiring close to the memory cell in the area without the selected memory cell. As a result, erroneous writing of data to non-selected memory cells can be suppressed in the selected row. A thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory cells, each of which stores data after being magnetized in a direction in which a magnetic field is written to the applied data; a plurality of bit lines, each of which is A corresponding setting for a predetermined division; and a data writing circuit, for at least one of the plurality of bit lines, supplying a data writing current that causes the data writing magnetic field to be generated in the direction of writing the data; the data writing circuit includes The plurality of first driving circuits each have a setting corresponding to the plurality of bit lines, and each drives a voltage on one end side of the corresponding bit line; the plurality of bit lines are divided into a plurality of arrays; each of the plurality of arrays has X (X: 2 The above integer) The bit lines are electrically connected to each other via short-circuit nodes; the data writing circuit further includes a plurality of second driving circuits, each corresponding to the complex array, and each driving the corresponding short-circuit node. Voltage; the sum of the plurality of first driving circuits selects at least one corresponding to the memory cell according to the written data and the first and One of the second voltages drives one end of the corresponding one; at least one of the plurality of second driving circuits and the corresponding one of the selected memory cells drives the corresponding short circuit at the other of the first and second voltages according to the written data node. This thin-film magnetic memory device can reduce the chip area by increasing the arrangement pitch of the drive circuit corresponding to the bit line and the other end side by X times. A thin-film magnetic memory device according to another aspect of the present invention includes:

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V. Description of the invention (13) Each of the plurality of memory units is magnetized and memorizes data in a direction in which a magnetic field is written in accordance with the applied data; the plurality of bit lines are respectively set corresponding to the predetermined distinction of the plurality of memory units; and The data writing circuit supplies, to at least one of the plurality of bit lines, a data writing current that generates a data writing magnetic field in accordance with the direction of writing the data; the plurality of bit lines is divided into a complex array; The groups each have two 70-bit lines electrically connected between the intermediate points; the data writing circuit includes a plurality of first driving circuits, each corresponding to the plural bit line, and each driving a corresponding bit line. Voltage on one end side; and a plurality of second driving circuits, each corresponding to the plurality of bit lines, respectively, respectively driving the voltage on the other end side of the corresponding bit line; among the plurality of arrays, the selection of a memory cell At least one, one of the corresponding two of the first driving circuits and the corresponding two of the second driving circuits, according to the written data, the one end side of the corresponding two bit lines Li one another and each of the one side of the respective drive as a brother and the second voltage. This 'special film magnetic body § Remembrance I' is not equipped with a driving circuit at the middle point of the bit line. In the bit line of the selection row, the data write current can only flow to the part corresponding to the selected memory cell. Interval. Therefore, it does not cause an increase in the area of the wafer, reduces the resistance of the data writing current path, makes it easy to supply the required data writing current during low voltage operation, and speeds up the data writing operation. In addition, erroneous writing of data to non-selected memory cells in the selected row can be suppressed. [Embodiment] An embodiment of the present invention will be described in detail below with "tea fl?" And drawings. In addition, the graph

2075-533〇-PF (Nl); Ahddub.ptd Page 17 200301480 V. The same-symbol in the description of the invention (14) means the same or equivalent part. Example 1 > ", Fig. 1 This embodiment of the Dragon AM component 1 responds to the external control signal CMD and address as% a T a ^ Write or output data DIN I :, 'Perform random storage Take the input material readout and data write operation \ 4_7 readout ° MRAM & the timing of the CLK synchronization of the material 1. ^ If in accordance with the external clock signal CU, but internally decided to move ^, not The MRAM component 1 receiving external clock signals includes: ㈤3. The overall operation of the MRAM component i can be controlled; the control circuit 5 'responds to the control signal CMD' and controls the plural MTs in the matrix. J memory: and 5 arrays 1 〇, is arranged so that it will be described in detail later. The structure of the memory array 10 is referred to as "memory cell row 2+ and ^ memory cell row (hereafter, read-only character line RWL. Also, The configuration of each unit is written using the character line WWL and only called the "memory unit /" since the second memory unit (the following is also MRAM components! Also includes "": the corresponding configuration bit button . Line driver 30 and read / write / II 152., line decoder 25, character ® inscribing control Roads 50 and 60. Column decoder 20 is based on the address in the memory array ο. I tiger ADD shows the column address M implementation of the row address 丁 Λ encoder 25 according to the address signal line driver 30 According to the column decoder 2 of the 仃 & selector, the read character line RWL is selectively changed to, Ί: the character line WWL is used to selectively change the data line when the data is read. Select the memory list to be used as the target for writing and the line address when writing

2075-5330-PF (Nl); Ahddub.ptd Page 18 200301480 V. Description of the invention (15) Yuan (hereinafter also referred to as "select memory unit"). The writing word line WWL is connected to the ground voltage G N D in a region 40 located on the opposite side of the memory array 10 from the arranged word line driver 30. The read / write control circuits 50 and 60 are designed to make the data write current and data read current flow to the memory cell row corresponding to the selected memory cell during data writing and data reading (hereinafter also referred to as A general term for a group of circuits arranged in the area adjacent to the controller 10 for the bit line BL of the "selection row"). The structure of the memory array and a circuit structure for performing a data writing operation on the memory array 10 are representatively shown in FIG. 2 '. Referring to FIG. 2, in the memory array 10, MT J memory cells MC are arranged in a matrix. Each MTJ memory cell MC includes a series-connected resistor that changes in accordance with the level of memory data, a tunnel magnetoresistive element TMR used as a magnetic memory portion, and an access transistor ATR used as an access element. As shown above, a typical application of the access transistor ATR is an MOS transistor of an electric field effect type transistor formed on a semiconductor substrate. In FIG. 2, representative memory cell MCs of the first to fourth memory cell rows, bit lines BU to BL4 corresponding to these memory cells, read character lines RWL1, RWL2, and write are shown. Use character lines WWL1, 'WWL2. In addition, in the following, when the signal lines of the writing character line, the reading character line, and the bit line are comprehensively expressed, the symbols [, RWL, and BL are used to indicate the specific writing character line. In the case of word lines and bit lines for reading, 'these symbols are added and expressed as WWL1, RWL1, and BL1. In addition, the high voltage state (power supply voltage Vcc) of the signal and signal line and

200301480 V. Description of the invention (16) The state of the low voltage state (ground voltage GND) is also called the "H" level and the "L" level. When the data is written, the $ yuan line driver 3 () selects the result according to the column row, and the word line WWL for the selected row becomes activated. The power supply voltage Vcc is connected. As already explained in FIG. 2 As shown, one end of each writing a-σ WWL is connected to the ground voltage GND in the area 40, and the data write: ^ IP flows from the word line driver 30 to the selected direction of the area 40, and the writing characters In the non-selected column, because the writing word line WWL · is kept in an inactive state (L level: ground voltage GND), the data writing current does not flow. Also, for writing Each signal line of the word tl line RWL remains inactive during data writing, and can be energy level (L level). 磁场 The magnetic field generated by the data writing current Ip is directed toward the difficult magnetization axis in the MTJ memory tunnel magnetoresistive element TMR The direction action. And, the action is caused by the data writing current flowing on the bit line of the selected row: MTJ 5 The tunnel magnetoresistive element Tmr in the memory cell saponin acts toward the easy magnetic universal.-Therefore ,, It is necessary to control the direction of the data writing current flowing on the bit line BL according to the level of the writing data MN. In the following, Η * and -Iw each indicate the data writing current flowing on the selected line when the data is written respectively. "" And "〇". In addition, the data writing current Iw is integrated. Represents the data writing current + 丨 and-丨 w. /; Ι Next, the structure of the data writing current ± Iw used to supply the bit line DIN of the selected row will be explained.

2075-5330-PF (Nl); Ahddub.ptd

P.20 200301480 V. Description of the invention (17) In the structure of the first embodiment, 乂 ^ 仏 仏 仏 仏 仏 口 口 口 口 口 and the bit line BL is arranged in the same direction as the digital current feedback wiring. Ms. + ^ ^ ^ ^ _, Yan KL each current feedback wiring RL is provided in each row of the plural memory lines. Memory array 1 〇 公 宝, 丨 Λ, &, ρ — each has κ (K ·· 2 or more)

The memory of each of the early supplementary lines of P A is charged a plurality of blocks CB. In Fig. 2, an example is shown in which two adjacent rows of 脰 fe 脰 = 仃 are constituted as a row block ⑶, that is, an example of κ = 2. In this case, each row block CB is composed of an odd row and an even row. Example of configuration / For example, a row block is constituted by the first and second memory cell rows

C B1 ′ is composed of the 3rd and 4th retentions-L Heart limb early fan 仃. Row block CB2 〇 The current feedback wiring RL is arranged in each row block CB. The plurality of memory cells in the same row block CB share the current feedback wiring. For example, the corresponding current feedback wiring RL corresponding to the lamp block CB1 is shared by the second and second memory cell rows corresponding to the bit lines BL1 and BL2, respectively. FIG. 3 is a structural diagram for explaining the arrangement of the current feedback wiring RL. Referring to FIG. 3 ', in the structure of the first embodiment, the mt j memory unit is disposed on a semiconductor substrate. An access transistor ATR is formed in the p-type region PAr on the semiconductor main substrate SUB. The access transistor ATr has source / inverter regions 110, 120 and gate 130, which are system regions. The source / drain region 1 1 0 is connected to a ground voltage GND through a metal wiring formed on the first metal wiring layer M1. The writing word line WWL uses a metal wiring formed on the second metal wiring layer M2. The bit line BL is provided on the third metal wiring layer M 3 on the upper side of the tunnel magnetoresistive element TMR. The tunnel magnetoresistive element TMR is disposed between the second metal wiring layer M2 provided with the word line WWL for writing and the third metal wiring layer M3 provided with the bit line BL. Save

2075-5330-PF (N1); Ahddub.ptd Page 21 20031480 V. Description of the invention (18) Take the source of the transistor ATR /> and the electrode region 1 2 〇 Via the metal film formed in the contact hole 1 5 〇 The first and second metal wiring layers M1 and μ, and the barrier metal 140 and the tunnel magnetoresistive element TMR are electrically connected. The barrier metal 14 is a buffer member provided to electrically connect the magnetoresistive element TMR and the metal wiring. As shown above, in the MTJ memory cell, the read character line RWL and the write character line WWL are provided as separate wirings. In addition, the writing word lines and bit lines BL require a data writing current for generating a magnetic field having a size larger than a predetermined value when writing data. Therefore, bit lines BL and writing word lines WWL are formed using metal wiring. The read word line RWL is provided in order to control the voltage of the access transistor ATR, and it is not necessary to actively flow a current. Therefore, from the viewpoint of increasing the density, the read word line RWL does not have a new independent metal wiring layer, and is formed on the same wiring layer as the gate 130 using a multi-silicon layer or a multi-sided structure. In the structural example shown in Fig. 3, a metal wiring layer M 4 different from the bit line b l is used to form a current feedback wiring R L. However, the current feedback wiring RL may be formed using a metal wiring layer on the lower side of the bit line BL or a metal wiring layer M3 which is the same layer as the bit line BL. Referring again to FIG. 2, a K data bus, an inverted data bus / WDB, and a data writing circuit 51 are provided in a region adjacent to the memory array 10. In the case of K = 2, two data buses DBo and DBe are arranged corresponding to the odd and even rows, respectively. When writing data, use one of the data buses DBo and DBe and

2075-5330-PF (Nl); Ahddub.ptd Page 22 200301480 V. Description of the invention (19) The phase data bus / WDB supplies data write current ± I w. When data is read out, one of the data buses DBo and DBe is connected to the selected memory unit. Referring to Fig. 4, the data writing circuit 51 includes a data writing current supply unit 52 and a switching circuit 53. The data writing current supply unit 5 2 includes a P-channel M0S transistor 1 5 1 for supplying a fixed current to the node NwO; a P-channel M0S transistor 152 for forming a current mirror that controls the passing current of the transistor 1 5 1 The circuit and the current source 153 °. The write current supply unit 5 2 further includes inverters 1 5 4, 1 5 5, and 1 6 that operate by receiving the operation current from the node nw 0. The inverter 1 5 4 inverts the voltage level of the written data DIN and transmits it to the node Nwi. The inverter 155 inverts the voltage level of the written data D I N and transmits it to the input node of the inverter 56. The inverter 1 56 inverts the output of the inverter 1 55 to the node Nw2. Therefore, the voltages of the nodes Nw; 1 and ^ 2 are set to one of the power supply voltage Vcc and the ground voltage GND according to the voltage level of the written data DIN. The Lang point N w 1 is connected to the inverse data bus / W D B. The switching circuit & 3 sets the voltage level to the node Nw2 and the data buses DB0 and DBe, which are the same as the data DIN, according to the selection signal cs0E indicating that the odd or even rows are selected. . Therefore, at the time of data writing, the data writing circuit 5 丨 sets one of the row selection results according to the data bus DB 0 and DB e to the same voltage level as the data DIN, and also reverses the data bus. / WDB is set to a voltage corresponding to the inverse phase of the data DIN. However, when reading the data,

2075-5330-PF (Nl); Ahddub.ptd page 23 200301480

V. Description of the invention (20) The material writing circuit 51 sets the nodes NW1 and Nw2 as floating bears, respectively. Next, the selection in the memory array line is explained. ~ ,,, 2 from above 2, set row selection line CSL and write row selection line WCSL in each row block CB. Each row selection line CSL is activated to the H level when data is read and when data is written into the Japanese, and the memory cell row in the corresponding row block CB is selected. On the other hand, the row selection line KSL for writing is used to write data at the head of the month, and the memory in the corresponding row block CB is selected to a level. Where / Tongue In addition, in each row block CB is configured to select K memory cells ::::: K write row selection lines. In the case of κ = 2, each of the countable and even rows corresponds to the write row selection lines WCSL0 and WCSLe. The writing and auxiliary selection line WCSL is activated when the odd-numbered lines become data writing. Yitian >-丨 ^ W +4 ^ ^: / The writing and auxiliary selection line WC ^ e becomes a shell on even lines.枓 The condition of the writing target is activated to the H level. The row controller 25 controls each row selection line CSL, each k = line, WCSL, and the row auxiliary selection line WCSL in accordance with the row selection result. ~ 疋 枓 rs: The second status month is used to control the connection control between the bit line, data bus, and inverse data bus. Select the setting line corresponding to the ^ body early yuan line to select the gate CSG. Lines 乂; Countable lines are electrically connected between the corresponding bit line BL and the data bus DBo bus DBe at the serial connection number / corresponding position and the data sink, g, and γοτ. The selection gate CSG of each row becomes conductive in response to the activation of the selection line CSL.

2075-5330-PF (Nl), Ahddub.ptd Page 24 20031480 V. Description of the invention (21) For example, in row block CB1, row selection gate CSG1 is located between bit line BL2 and data bus DBo. The row selection gate CSG2 is provided between the bit line BL2 and the data bus DBe. The row selection gates CSG1 & CSG2 are turned on in response to the activation of the row selection line CSL1. The current feedback wiring r l provided in each row block C B is connected in series between the node / n d and the inverse data bus / WDB and the selection gate rsG. The selection gate RSG becomes conductive in response to the activation of the corresponding write row selection line WCSL. For example, in the row block CB1, the current feedback wiring rli and the write row selection line WCSL are activated to become conductive selection gates to be connected in series between the inverse data bus / WDB and the node / N d . In addition, κ bit lines belonging to the same row block are each connected via independent κ write row selection gates and corresponding current feedback wiring RL. The κ write-row selection gate becomes conductive in response to the activation of the corresponding write-row secondary selection line. ^ In the case where the memory cell row corresponding to the bit line BL1 of the odd row is a selected row, the lean material bus Dbo and the reverse data bus / WDB are set to the Η level according to the level of the data DIN (power supply Voltage Vcc) and L level (ground voltage GND). In addition, the row selection line csu, the write row selection line WCSL1, and the write row subselection line WCSL0 become active, and the row selection CSG1, the selection gate RSG1, and the write row selection gate WCSG0 become conductive. Therefore, using the bit line BL1 and the corresponding current feedback wiring RLi which are electrically connected through one end of the node / Nd and one end thereof, the data can be written in the direction according to the data DIN level ± Iw flows to bit line BL1.

2075-5330-PF (N1); Ahddub.ptd Page 25 20031480 V. Description of the invention (22) Same as in the case where the memory cell row corresponding to the bit line BL 2 of the even row selects the row, the data is converged Row Dbe and reverse data bus / WDB know: according to the written data j) I n level is set to either η level (power supply voltage vcc) and l level (ground voltage gnd). In addition, since the row selection line CSL1, the writing row selection line WCSL1, and the writing row auxiliary selection line wCSLe become active, the row selection gate CSG2, the selection gate RSG1, and the writing row selection gate WCSGe are turned on. Therefore, using the bit line BL 2 and the corresponding current feedback wiring rl 1 which are electrically connected through one end of the node / Nd and one end thereof, the data can be written in the direction according to the level of the written data DIN. The electric current I w flows to the bit line BL2. Therefore, in the structure of Embodiment 1, the current path including the current feedback wiring RL connected to the inverse data bus / WDB, which is shared by the K memory cell rows, uses the data flowing in the bit line BL of the selected row. The writing current ± jw flows. Therefore, by controlling the voltage levels of the K (K = 2) data buses Dbo, Dbe and the inverse data bus / WDB of the memory cell rows shared in the memory array 10 as a whole, the voltage levels according to The data written into the data current Iw flows to the bit line of the selected row. That is, the circuit structure for controlling the direction of the data writing current ± I w in accordance with the data writing level can be simplified. 'At the time of the data read operation,' the character line driver 30 selects one of them. The selling daughter wire R W L is activated to the Η level. The row decoder 25 inactivates each of the write row selection lines WCSL and the write row auxiliary selection lines wCSLo and WCSLe to the L level. /

2075-5330-PF (Nl), Ahddub.ptd Page 26 200301480 V. Description of the Invention (23) Therefore, in each memory cell row, the bit muscle and the inverse data bus / WDB are electrically separated. In addition, one of the selected memory unit and the data bus DBo and DBe is electrically connected. Therefore, the data readout current supplied from the data readout circuit not shown in the figure to the data bus connected to the selection memory unit can be read out by detecting the change in the current or voltage of the data bus. Memory data. In addition, the representation shown in FIG. 2 corresponds to the structure of the fourth memory cell row, but in other memory units, signal lines or gates are also arranged according to the same structure. Dream of a modification of the embodiment 1 According to FIG. 5, the structure of the modification of the first example is implemented in accordance with FIG. 5. Compared with the structure shown in FIG. ~ »1. The choice of setting between the RL feedback wiring RL and the inverse data bus / WDB is different from the RSG. According to the structure of the modification of the first embodiment, the node / n d is always electrically connected to the reverse-phase bus / WDB in each rod F-block C β. However, at the time of data writing, Youxiang Guoxu #f 0 τ 隹 The non-selected row block, in response to the non-activation of the corresponding row selection line CSL, Zeng Sm produced strong, stepped on the disc +, each selected for selection The gate CSG becomes non-conducting. The block writes data on the bit line BL. The current I w does not flow. 0 — the same, the left bn

During the reading of the shell material, both the WCSGo and WCSGe selection gates are used to write 行 ^, DT 仃 on each rod for the purpose of writing. The block wires bl and the corresponding current are used for feedback distribution. Tick order „Taxi + γ — π 叱 are electrically separated from each other. As a result, in the structure of the modified example of Example 1, ★ can be approved-3 6 Taxi can also perform the same tributary items as in Example 1. It is used to select the setting corresponding to the current feedback wiring RL

Page 27 200301480 V. Description of the invention (24) The configuration of the gate RSG can also perform the same data reading and data writing operations as in the first embodiment. By adopting this structure, the structure of the memory array 10 can be simplified. In addition, in the first embodiment and its modification, it is shown that the row selection line CSL and the writing row selection line WCSL are arranged in a direction parallel to the bit line BL, that is, the row direction, and the writing row sub-selection line WCSL is arranged in the column direction. 〇, wCSLe structure, but these selection lines can be arranged along any direction. Embodiment 2 Referring to FIG. 6, in the structure of Embodiment 2, compared with the structure of Embodiment 1, the configuration of the current feedback wiring RL in each row block is omitted, and the configuration is opposite to each other through the memory array 10 The area configuration data buses Dbo, DB e and reverse data bus / WDB on the side are different. As in Embodiment 1, each row block CB has K memory cell rows corresponding to different row addresses. The structure of the case where κ = 2 is also shown in FIG. 6. The data buses DBo and DBe are arranged in the column direction in one of two areas adjacent to the memory array 10 in the row direction as in the first embodiment. The inverse data bus / WDB is arranged along the row direction in a region across the memory array 10 and the opposite sides of the data buses D B 0 and D B e. In each row block CB, the write row selection gates WCSGo and WCSGe are electrically connected between the inverse data bus / WDB and the corresponding bit line. The structure and operation of other parts are the same as those of the first embodiment and its modification, and detailed descriptions thereof will not be repeated. Therefore, when data is written, K rows are selected as gates in each row block.

2075-5330-PF (Nl), Ahddub.ptd Page 28, 20031480 V. Description of the invention (25) The CSG responds to the activation of the corresponding line selection line CSL, each of the k-bit line and the K data bus Connected electrically. The writing row selection gates WCSGo and WCSGe are turned on in response to the activation of the writing row selection sub-lines wcSLo and WCSLe. Therefore, according to the κ bit line,

The other end of the selected bar is electrically connected to the inverse data bus / WDB. By adopting such a structure, in the structure of the second embodiment, no current return phase is provided: the wiring RL is used, and the bit line for selecting the row is as simple as the structure of the first embodiment and its modification. Input current ± iw. Also, as in the first embodiment, the row selection line CSL can be configured for each row block CB, that is, each plural (κ) memory cell row, and the number of signal wirings required for row selection can be greatly reduced. Embodiment 3 FIG. 7 shows the structure of Embodiment 3, and the corresponding bit line of each memory cell row is composed of two complementary bit lines. In FIG. 7, representatively, the structure corresponding to the j-th (j: natural number) memory cell row is shown, but the structure is the same as that corresponding to each memory cell row. The bit lines BL j and / BLj constituting the bit line pair BLP j are each provided with metal wirings formed on the metal wiring layers M3 and M4 located on the upper side of the MTJ memory cell MC in a predetermined position in the vertical direction. Intersecting. 5 The memory array 10 includes η (η: an integer of 2 or more) a single 70-column memory array, each of which is arranged on each of the right and left areas of the predetermined area where the Li Yuan line BL and / BL intersect. (Integer expressed as η / 2) memory unit

2075-5330-PF (Nl); Ahddub.ptd Page 29 200301480 V. Description of Invention (26) column. Bit lines BL and / BL are formed in the left-hand area where the read word lines RWL1 to RWLm and the write word lines WWL1 to WWLm are arranged, respectively, by wirings arranged on the metal wiring layers M4 and M3. In addition, bit lines BL and / are formed in the right-hand region where the read character lines RWLm + 1 to RWLn and the write character lines WWL m + 1 to WWL η are arranged by wirings respectively disposed on the metal wiring layers M3 and M4. BL. It is connected in a predetermined area to the wiring corresponding to the bit line BL formed in each of the metal wiring layers M3 and M4. Similarly, wirings corresponding to the bit lines / BL formed by the metal wiring layers M3 and M4 are also connected in a predetermined area. One of the bit lines BL and / BL and the short distance between the MTJ memory cell, that is, the metal wiring layer M3 on the lower side, is connected to the MT J memory cell MC. The write row selection gate WCSG j responds to the activation of the corresponding write row selection line WCSL j, and connects one end of the corresponding bit line BL j and / BL j. In addition, a data bus pair DBP composed of complementary data buses DB and / DB is set. At the time of data writing, the voltages of the data buses db and / DB are respectively connected to the nodes Nw2 and Nwl of the data writing current supply unit 52 shown in FIG. 3. Therefore, the data bus DB and / DB are set to each of the power supply voltage Vcc and the ground voltage GND according to the level of the written data D I N. The row selection gate CSG j has a transistor switch connected between the other ends of the bit lines BL j and / BL j and the data bus DB and / DB, respectively. These transistor switches are turned on in response to the activation of the corresponding row selection line CSL j. By adopting this structure, the direction in which the writing current ± Iw according to the data written in the data D 丨 N flows to the bit lines BL and / bl of the selected row can be used as a reciprocating current folded back by the writing row selection gate WCSG j. In the left area, data is written using the current flowing on the bit line BL; in the right area, data is written using

2075-5330-PF (Nl); Ahddub.ptd page 30 200301480 V. Description of the invention (27) The current flowing on the bit line / BL performs data writing. Therefore, as in the first embodiment, the data writing current according to the writing data level can be supplied in the direction of the bit line of the selected row without causing the peripheral circuit to be complicated. In addition, the reverse currents flow to the bit lines BL and / BL adjacent to each other in the up-and-down direction, respectively, and the bit lines and / BL generated from the selected row act on the MT J memory of the adjacent memory cell row. The magnetic noise of the units weakens each other. Therefore, by reducing the influence of magnetic noise, it is possible to prevent erroneous writing of data 'and stabilize the operation. At the time of data reading, the row selection gate WCSG in each memory cell row becomes non-conductive due to the write row selection gate, and one end of the bit lines BL · and / BL · are electrically separated. In addition, at the selection row, the row selection gate CSG is turned on, and the other ends of the corresponding bit lines BL and / BL are connected to the data bus DB and / DB respectively. At the time of data reading, at least one of the data bus DB and / DB receives the supply of data writing current. In particular, in each memory cell row, a virtual memory cell (not shown in the figure) configured with a resistance of a middle gate, which can be selectively connected to each of the complementary bit lines BL and / BL, can be used. Of the structure. That is, the resistance of each virtual body unit is not the intermediate value of the two kinds of resistances of the memory unit memorizing π 1 ′ ′ and " 〇 ". % Own If such a virtual memory unit is configured, data is read out with each bit line pair according to the voltage between the complementary bit line BL, / BL being higher than the first ten bits. Λ Noise resistance Also, the bit line is arranged in the third embodiment to form a bit line.

200301480 V. Description of the invention (28) The number of memory cells connected to the bit lines BL and / BL of each pair of bit lines is set to be equal, and it can be corrected between the bit lines BL and / BL forming the same bit line pair BLP The RC load is unbalanced. In addition, the bit lines BL and / BL are intertwined to reduce interference noise between the two during data reading, and high-speed and high-precision data reading can be performed. Modification of Embodiment 3 The modification of Embodiment 3 shows a bit line arrangement in which the structures of Embodiment 2 and Embodiment 3 are combined. Referring to FIG. 8, in the structure of the modification of the embodiment 3, compared with the structure of the embodiment 3, the data buses DB1 and DBr and the inverse data bus / WDB in which the substitute bit line pair BLP is arranged are written on and replaced with The writing of the row selection gate WCSG j is different between the row selection gates WCSG1-j and WCSGr-j. The write row selection gate W C S G 1 — j is provided between the inverse data bus / w D B and one end side of the bit line BL j, and becomes conductive in response to the activation of the control signal SG 1. When the control signal SG1 is written, the area to the left of the predetermined area where the bit lines BL and / BL intersect includes the case where the memory cell is selected, and is activated to the unit level. The write row selection gate WCSGr — j is provided between the inverse data bus / WDB and one end side of the bit line BL j, and becomes conductive in response to the activation of the control signal SGr. When the control signal SGr is written, the area to the right of the predetermined area where the bit lines BL and / BL intersect includes the case where a memory cell is selected, which is activated to a unitary level. At the time of data readout ', each of the memory cell lines is electrically separated from the inverted data bus / W DB and the bit lines BL, / BL. In addition, by

2075-5330-PF (Nl); Ahddub.ptd page 32 200301480 V. Description of the invention (29) At least one of the supplied data bus DB1 and DBr is written and the same data is read as in Example 3. μ% 'Implement by adopting this structure' During data writing, λ j \ l 区域 / v selects the area of the memory cell, and the data writing current does not flow 6 1 and 3 冋 and Μ 了 了Metal wiring close to the three-dimensional unit. Therefore, in the selected row, data may be miswritten in the memory unit. The ρ system is not remembered, because the data on the bit line pair of the selection line is appropriate, the Ding Ma into the power industry is shorter than the structure of Example 3, which can reduce the resistance, and can be used for a short time, " L ^ K shell material writers will speed up and reduce power consumption. "Η

In addition, in the third embodiment and its modification, an example is shown in which one of the predetermined areas of A longitudinally causes the bit lines BL and / BL to win 7 in the up-down direction. However, it is also possible to use a plurality of settings. The structure of the intersection. Embodiment 4 Referring to FIG. 9, the memory array 10 is divided into a plurality of memory blocks along a column direction. In FIG. 9 ', the memory array 10 is divided into two memory blocks Mba and MBb, for example. In the §fe block Mba, the respective read character lines RWLal, RWLa2, ... and the write character lines WWU1, WWLa2, ... are arranged corresponding to the memory cell column. Similarly, in the 5th memory block Mbb, the configuration items corresponding to the memory cell columns use sub-element lines R W L b 1, R W L b 2, ..., and writing character lines WWLbl, WWLb2, .... That is, the read character line RWL and the write character line WWL are independently provided in the memory blocks Mba and MBb. On the other hand, the corresponding bit line B L ° in the memory blocks MBa and MBb corresponding to each memory cell row configures a data bus in each memory block.

2075-5330-PF (Nl); Ahddub.ptd Page 33 20031480 V. Description of the invention (30) The data bus DBa corresponding to the memory block MBa corresponds to one end side of the bit line (the memory block MBa side). Are arranged along the column direction in a region adjacent to the memory array 10. The data bus DBb corresponding to the memory block MBb and the other end side (the memory block MBb side) of the bit line BL are arranged along the column direction in a region adjacent to the memory array 100. The inverse data bus / WDB is common to the memory blocks MBa and MBb, for example, and is arranged along the column direction at the boundary between the memory blocks MBa and MBb. In each a line, a bit line is considered. A node N a corresponding to one end side and a node n b corresponding to the other end side are each connected via a drive switch and a data bus DBa and DBb, and via an intermediate node and Inverted data bus / WDB connection. For example, corresponding to the bit line BL, a driving switch is respectively provided between the nodes Na (1) and Nb (1) and the data buses DBa and DBb respectively corresponding to one end side and the other end side of the bit line BL. CDGM, a drive switch wdg 1 is provided between the intermediate node N m (1) and the inverse data bus / w DB. In addition, in the following, when expressing a node on a specific bit line, such as Na (1), Nb (1), Nm (1), a number with parentheses is added to express the bit line in an unspecified comprehensive The situation is just expressed as Na, Nb, Nm. The drive switches CDGal and CDGbl are opened and closed in response to the outputs of the row control brakes CGal and C G b 1, respectively. The drive switch w D G 1 is opened and closed in response to activation of the corresponding write row selection line WCSL1. A write line selection line WCSL is provided in each memory cell line, and is activated to the n level in the selection line during a data writing operation. The row control gate CGa 1 selects the corresponding first memory cell row when data is written, and when the selected memory cell belongs to the memory block MBa

2075-5330-PF (N1), Ahddub.ptd Page 34 200301480 V. Description of the invention (31) Condition, the corresponding drive switch CDGal becomes conductive. The data read line control gate CGal selects the corresponding first memory cell row, and turns the corresponding drive switch CDGal on. Coincidentally,

The current control gate CG a 1 has an AND gate and outputs the corresponding ANj between the voltage level of the write two selection line WCSL1 and the block selection signal SBa) ^ The gate result, and the OR gate outputs the output of the AND gate and the corresponding Read the result of 0R logic operation between the voltage levels of the selection line RCSL1. 〇R asked == The output input is composed of N-channel M0S transistor to drive the wheel of MCDGal. J Set the read line selection line "Recognition" in each memory cell row, and activate it to the H level in the selection row when the scholarship moves. The block selection signal SBa is activated when the second = the memory unit belongs to the memory block MBa. In the case where the selected memory unit belongs to the memory block MBb, the same setting is used, and the selection signal SBb is activated to the active level. &Amp; The block row control gate CGb 1 selects the corresponding when writing data The first record 丨 production ㈣ single fan line 'and in the case where the selected memory cell belongs to the memory block MBb ~, also, the corresponding drive switch CDGbl is turned on. On the data readout day ^, regardless of the row selection result' line The control gate CG b 1 makes the corresponding drive switch and CDGbl non-conductive. That is, the row control gate CGbl has an AND gate and outputs an AND between the voltage levels of the corresponding row selection line WCSL1 and the block selection signal SBb. Logic Z operation result. The output and input of the AND gate are composed of n-channel M0S transistors to drive the gate of the CDGbl switch. During data writing, the data buses DBa, DBb, and inverse data sinks

2075-5330-PF (Nl); Ahddub.ptd page 35 200301480 V. Description of the invention (32) Row / WDB each and in the embodiment! The data bus DBo, DBe and reverse data bus / W DB are the same settings. Specifically, with the same structure as the data writing circuit 51 of the first embodiment, the switch circuit 53 may be controlled in accordance with the block selection signals SBa and SBb. By adopting this structure, for example, when data is written, when the first memory cell row is selected, the drive switch WDG 1 is turned on. In addition, one of the drive switches CDGal and CDGbl belongs to the memory according to the selected memory cell. Which of the blocks MB a and MBb becomes conductive. That is, when the selected memory cell belongs to the memory block MBa, the drive switches MCDGal AWDG1 located on both sides of the selected memory cell become conductive, respectively, and the nodes N a (1) and N m (1) on the bit line BL 1 ) Each is connected to the data bus DBa and the reverse data bus / WDB. Therefore, the node Na0) and

Nm (1) is set to each of the power supply voltage ycc and the ground voltage GNI) in accordance with the written data d I n. Therefore, in the bit line BL1 of the selection row, the direction according to the lean write current ± I w of the written data DIN can flow to the nodes Na (丨) ~ Nm (corresponding to the memory block including the selection memory unit)丨). In addition, since the drive switch CDGbl is not turned on, the bit writing line BL1 on the selection row will not flow the data writing current between the nodes Nb (丨) ~ Nm (丨) that do not correspond to the selection memory cell. In other words, when the selected memory unit belongs to the memory block MBb, the drive switches CDGbl and WDG1 located on both sides of the selected redundant memory unit become conductive, and the drive switch CDGal becomes non-conductive. Therefore, in the selection of the bit line π line BL1, the direction can be written according to the data written in the data MN.

2075-5330-PF (Nl); Ahddub.ptd 200301480 V. Description of the invention (33) The flow ± I w flows between the nodes Nb (l) and Nm (l) corresponding to the memory block including the selected memory unit. On the bit line BL1 of the selection row, the data write current does not flow between the nodes Na (l) and Nm (l) which do not correspond to the selection memory cell. In FIG. 9, drive switches CDGal to CDGa4, CDGb, CDGb4, WDG, WDG4, and row control gates CGa are representatively shown from the first to the fourth memory cell rows and the respective configurations corresponding to the memory cell rows. CGa4, CGM ~ CGb4, read row selection lines RCSL1 ~ RCSL4, and write row selection lines WCSU ~ WCSL4. These drive switches, control gates, and row selection lines are similarly arranged in other memory cells. In addition, in each memory cell line, the operation at the time of data writing is performed in the same manner as in the first memory cell line. As shown in the above description, the structure of Embodiment 4 is the same as that of Embodiment}, and the current can be supplied in the direction of writing data according to the writing data D I N level, without complicating the peripheral circuits. In addition, in the bit line of the selection row, since the data write current flows only to the interval corresponding to the portion corresponding to the selected memory cell, the path of the data write current can be shortened and the resistance can be reduced. In recent years, low-voltage operation has been performed due to requirements such as lower power consumption. However, by reducing the resistance of the data writing current path, it is easy to supply the required data writing current even during low-voltage operation. In addition, reducing the resistance of the data writing current path can also contribute to speeding up the capital operation. 'In addition, in the selected row, because the data write current does not flow to the bit line 叽, the interval corresponding to the non-selected memory block can also suppress the

2075-5330-PF (Nl); Ahddub.ptd

Page 37 200301480 V. Description of the invention (34) The data of the memory unit of the selected memory block is written incorrectly. In addition, in the structure of the fourth embodiment, a plurality of intermediate nodes are provided on each element line, and the data can also be written in a more subdivided control section in which the current flows. In this case, each of the element lines BL needs to interact with each of the switches and data buses and the reverse-phase data buses of the plurality of drive switches provided corresponding to the nodes at one end, the plurality of intermediate nodes, and the nodes at the other end. Corresponding. Modified Example 1 of Embodiment 4 Refer to FIG. 10 ′. In Modified Example 1 of Embodiment 4, the memory array 10 uses a folded bit line structure. The memory array is divided into a plurality of memory blocks along the column direction as in the fourth embodiment. In FIG. 10, the memory array is divided into a plurality of memory blocks along the column direction. In FIG. 10, the memory array is also divided into two memory blocks Mba and MBb. In each of the memory blocks MBa and MBb, a read character line RWL and a write character line WWL are provided in each memory cell row. According to the folded bit line structure, a bit line pair BLP composed of complementary bit lines BL and / BL is arranged corresponding to each memory cell row. The complementary bit lines BL and / BL are commonly arranged in the memory blocks MBa and MBb. For example, the bit line B L1 and / B L 1 corresponding to the first memory cell row constitute a bit line pair BLP1. The MTJ memory cell MC is alternately connected to one of the bit lines BL and / BL every other column. For example, if the M TJ memory cell belonging to the first memory cell row is described, the M TJ memory cell in the first column is connected to the bit line bl 1, and the MTJ memory cell in the second column is connected to the bit line / BL 1 . Following one

2075-5330-PF (Nl), Ahddub.ptd Page 38 20031480 V. Description of the Invention (35) Similarly, MTJ memory single το is connected in the odd column and bit line BL1, and in the even column and bit line / B L1 connection. In addition, in the areas adjacent to the memory array, the data buses DBpa and ⑽ ^ corresponding to the memory blocks MBa and MBb are respectively set. In the area of the MBa side of the memory area, the data congestion is arranged along the column direction? 3. Includes complementary data buses DBa and / DBa. Similarly, the data bus DBpb is arranged in the area of the memory block MBb side along the row direction, including the complementary data buses DBb and / DBb. In the structure of the first modification of the fourth embodiment, the same applies to the drive switches, control brakes, and row selection lines in each memory cell. Therefore, the structure of the first memory unit will be described in a representative manner below. The drive switch CDGal has a transistor switch, which is respectively connected between the respective nodes Na (1) & / Na (1) and the data buses DBa and / DBa corresponding to one end side of the bit lines BL1 and / BL1. These transistor switches are opened and closed in response to the output of the row control gate CGa 1 having a structure similar to that of FIG. 9. The drive switch CDGbl has a transistor switch, which is respectively connected between the respective nodes Nb (丨) and / Nb (丨) and the data buses DBb and / DBb corresponding to the other ends of the bit το lines BL1 and / BL1. These transistor switches are opened and closed in response to the output of the row control gate CGb 1 having the same structure as that of FIG. 9. The drive switch WDG1 is connected between the intermediate node Nm (1) of the bit line BL1 and the intermediate node Nm (1) of the bit line / BL1 corresponding to the boundary portion of the memory blocks MBa and MBb. As in the structure of FIG. 9, the drive switch WDG 丨 is opened and closed in response to the corresponding write row selection line WCSL1. Data buses DBa and / DBa constituting the data bus DBPa

2075-5330-PF (Nl); Ahddub.ptd Page 39 20031480 V. Description of the invention (36) The voltage, including the case where the memory unit is selected in the memory block MBa, respectively, and the data write current shown in Figure 3 The nodes N w 2 and N w 1 of the supply unit 5 2 are connected. Therefore, the data buses DBa and / DBa are set to one of the power supply voltage Vcc and the ground voltage GND according to the level of the data DIN. Similarly, the data buses DBb and / DB b constituting the data bus DBPb include the case of selecting a memory unit in the memory block MB b, and are set to the power supply voltage vcc and the ground voltage according to the level of the data DIN Each side of GND. Therefore, when the first memory unit row is selected and the selected memory unit το belongs to the memory block MBa, the drive switches CDGal and WDG1 located on both sides of the selected memory unit become conductive, and are written according to the data written in DIN Input current ± I w Node on bit line pair BLp 丨

Na (l) ~ NπΚΙ) ~ / Nm (1) ~ / Na (1) flow. Moreover, because the drive switch CDGbl becomes non-conducting, on the bit line pair BLp of the selection row, the data write current will not flow to the node and the node that does not correspond to the selected memory cell * Nb (l) ~ NπKI / Nb (1) to / Nm (i) 2. Phase = Yes, when the selected memory cell belongs to the memory block _, each

2 $ & Select 5 drive switches ⑶ and ㈣U on both sides of the memory unit: two: = and the drive switch CDGal becomes non-conducting. Therefore, the order of the line is BLP 1. We can use a 4λ > w input current ± Iw to only write data to the package and write the data _ data write ^ ^ ^ ^ 栝, select the memory block of the memory unit to the library ☆ On the bit spool of the selected row, the data is written to the interval where the memory unit does not correspond. Said wood uses k kinds of structures w 'in a modification of the fourth embodiment [structure, in

200301480

V. Description of the invention (37) The memory array 10 adopts the folded bit line structure; ~ 丨 month / child, can also write the same data as in Example 4. In addition, in each memory cell row, a configuration can be used to selectively connect the complementary lines BL and / BL · to each element line of the long-term bit t Ν Dan has a medium p 中 lei, that is, each The structure of the virtual memory unit (not shown) of the virtual resistance. That is to say, the resistance of each N electric unit has its own body and the early element is set to the middle value of the two kinds of resistances in the memory of "1" and "quote." The virtual 5 body memory unit is configured to the right. In the case of each pair of element lines, it is performed in accordance with the voltage comparison between complementary bit lines BL and / BL. Μ Early bit can be read high. Γ Modification 2 of Embodiment 4 Referring to FIG. The structure of Modification 2 of Example 4 is compared with the structure of Embodiment 4 shown in FIG. 9 in the configuration corresponding to each bit line Bl. = Bit switches BDVa, Bd, and BDVni of the switch switches CDGa, CDGb, and WDG For example, for bit line BL1, the bit line drivers BDVal and BDVbl corresponding to the nodes Na (l) and Nb (l) respectively corresponding to one end side and the other end side of the bit line BL1, and the intermediate node Nm ( 1) The corresponding bit line driver BDVml is provided. The bit line driver BDVal has driver transistors DTHa and DTLa, which are respectively connected between the power voltage V cc and the ground voltage GND and the node Na (1). The driver transistor DTHa and DTLa opens and closes in response to the write control signal and WLal. Line driver having a driver transistor and DTHb DTLb, each connected to the power voltage and the ground voltage GND and vCc

200301480 V. Description of the invention (38) Between nodes Nb (l). The driver transistors DTHb & DTLb are opened and closed in response to the write control signals / WHbl and WLbl, respectively. The bit line driver has driver transistors DTHm and DTLm ', which are each connected between the power supply voltage ycc and the ground voltage GND and the node Na (l). The driver transistors DTHm & DTLm each open and close in response to the write control signals Wml and Wm # l. Bit line drivers BDVa, BDVb, and BDVm having the same structure are arranged in each memory cell row, but write control signals of the driver transistor group are independently set in each memory cell row. In this modified example, the data writing circuit (not shown in the figure) generates a writing control signal according to the data writing level, the memory block selection result, and the row selection result. In the selection row ', when the selected memory cell belongs to the memory block MBa, the bit line drivers BDVa and BDVm drive the corresponding node to the power supply voltage Vcc and the ground voltage GND according to the data written. However, the bit line driver BDVb does not drive the node porosity to one of the power supply voltage Vcc: and the ground voltage G N D. In the case where the remotely selected memory cell belongs to the memory block MBb, the bit line drivers BDVb and BDVm drive the corresponding nodes Nb and _ to the power supply voltage Vcc and the ground voltage GND according to each of the data written. On the other hand, the bit line driver BDVa does not drive the node Na to any one of the power supply voltage Vcc and the ground voltage G N D. As a result, like the structure shown in FIG. 9, on the bit line of the selection line, the direction of the data writing current according to the written data can only flow to and select the memory sheet = corresponding part (nodes Na ~ Nm or nodes between). Therefore, it is possible to reduce the resistance of the lean write current path, and at low voltage operation

2075-5330-PF (Nl); Ahddub.ptd Page 42 200301480 V. Description of the invention (39) It also makes it easy to supply the required data writing current, and speeds up the data writing operation. In addition, erroneous writing of data in the memory cells of the non-selected sentiment blocks of the selected row can also be suppressed. For the 'non-selected row' at the time of data writing, the bit line driver, BDVb and BDVni drive the corresponding nodes Na, Nb, Nm to ground voltage GND to prevent unwanted current from flowing. Moreover, the bit line drivers B D V a, B D V b, and B D V m do not drive the corresponding nodes n a, n b, and Nm to the power supply voltage Vcc and the ground voltage GND except during data writing. In addition, the read data buses RDB1, RDB2, and the intermediate node Nm are arranged at the boundary portions of the memory blocks MBa and MBb. The readout data buses R D B 1, R D B 2 and the bit line B L intersect and are arranged along the column direction. The respective settings corresponding to the memory cell rows are used to selectively connect the readout data gates R D B1, R D B 2 and the read-out selection gates RDSG and RDSG4,... The read selection gates RDSG1 to RDSG4, ... are turned on in response to the activation of the read row selection lines RCSU to RCSL4, .... Each readout selection gate is connected between the corresponding intermediate node and the readout data bus RDB1 'in the odd rows and between the corresponding intermediate node_ and the readout data bus RDB2 in the even rows. When the data is read, in response to the activation of the read word line RWL in the selection column, the bit line in the selection row is connected to the ground voltage GND via the selection memory cell. In this state, by using the data readout circuit 55, the data readout current is passed to the readout data buses RDB1, RDB2, and the current and voltage of the readout data buses RDB1, RDB2 are detected, and the self-selected memory is executed. The information of the unit is read out.

2075-5330-PF (Nl); Ahddub.ptd page 43 20031480 V. Description of the invention (40) At this time, it is set as the intermediate node Nm of the data bus RDB1, RDB2 for reading and the bit line of the selected row. The structure of the connection shortens the length of the bit line on the read current path, which can reduce the power of the read current path. Therefore, it is possible to support the output rate of negative items and the readout margin of tribute materials. In addition, in the folded bit line structure shown in FIG. 10, the configuration of the bit line drivers BDVa, BDVb, and BDVm that drive the switches C D G a, C D G b, and W D G may be replaced. Also in this structure, the data bus for readout and the selector gate for readout corresponding to the intermediate node Nm can be ordered as in FIG. 11. Embodiment 5 Referring to FIG. 12, in the structure of Embodiment 5, the memory array 10 is divided into a plurality of row blocks along the row direction. In FIG. 2, the memory array is divided into two row blocks CBa and CBb. In the row block CBa ', the bit lines BLal, ... corresponding to the memory cell rows are arranged. Similarly, in the row block CBb, the bit lines BLbl, ... corresponding to the memory cell rows are arranged. That is, in the row block CBaACBb, the bit line BL is independently provided. In the row blocks CBa and CBb corresponding to each memory cell column, a read character line RWL and a write character line .L are arranged together. Each writing word line WWL is connected at a boundary bit corresponding to the row blocks CBa and ⑽, and the intermediate node Nm is connected to the ground voltage GND. For example, ΐ I two rows and 1 should be used Λ Yuan ㈣ 乂 in the middle section and ⑴ 弟 and φ σ 一 5 5 write memory corresponding to a single character line L2 at the intermediate node Nm ( 2) Connect to ground voltage G ND.

200301480 V. Description of the invention (41) Fig. 12 represents the structure of the character word line WWL used to drive the character line driver 30. The word line driver 30 includes a current supply wiring SPL and a current supply circuit 31 provided in each row block. FIG. 12 shows current supply wirings spu and SPLb and current supply circuits 31a and 31b corresponding to the row blocks CBa and CBb, respectively. Referring to FIG. 13, the current supply circuit 31 a has a p-channel type | 408 transistor 3 3 a ′ which is electrically connected between the power supply voltage V cc and the current supply wiring s PL a; a P-channel type M0S transistor 33 b, The power supply voltage Vcc is electrically connected to the node Npl; the N-channel MOS transistor 34 is electrically connected between the node Npl and the ground voltage GND. Each gate of the transistors 3 3 a and 3 3 b is connected to a node n p 1. A control voltage Vrp is input to the gate of the transistor 34. Therefore, a current mirror circuit composed of transistors 33a and 3b supplies a current supply line SPLa set to the power supply voltage Vcc in accordance with the fixed current of the control voltage Vrp. The current supply wiring "" also has the same structure as the current supply wiring SPLA. Referring again to FIG. 12, the word line driver 3 has a driving switch RDGa provided between the node Na on one end of the writing word line WWL and the current supply wiring SPLa; and a driving switch RDGb provided on the writing word. Between the other vertical point N b of the element line boundary milk and the current supply wiring SPL b. In FIG. 12, in the first and the first memory cells, representatively represent the driving switches RDGai corresponding to the points Na (丨), Na (2), Nb (l), and Nb (2) respectively. , RDGa2, RDGbl, RDGb2 ° drive switch RDGa in the corresponding memory cell row and select

2075-5330-PF (Nl), Ahddub.ptd Page 45 200301480 V. Description of the Invention (42) The case where the memory cell belongs to the row block CBa becomes conductive. Similarly, the drive switch RDGb becomes conductive when the corresponding memory cell row is selected and the selected memory cell belongs to the row block CBb. For example, when the gate of the drive switch RDGal is written, when the first memory cell row is selected and the selected memory cell belongs to the row block C B a, a control signal / WRDla activated to the L level is input. Similarly, when driving the gate of the switch RDGbl, when the first memory cell row is selected and the memory cell belongs to the row block CBb when the data is written, the control signal activated to the L level is input / WRD 1 b . The column decoder 20 generates control signals / WRDla and / WRDlb according to the row selection result. The column decoder 20 generates a control signal RRd for each memory cell column. When data is read out, when the corresponding memory cell row is selected, the control signal R R d is activated to the Η level. The voltage of each read word line RWL is controlled according to the corresponding control signal R R d. For example, in response to the activation of the control signal RRd, the read word line RWL1 is activated to the Η level. By adopting this structure, the word line driver 30 selectively turns on one of the drive switches RDGa and RDGb in the selection column according to the positional relationship between the selection memory cell and the intermediate node Nm. As a result, the data writing current I p in a predetermined direction can be selectively flowed to the memory cells corresponding to the nodes Na to Nm and the sum of the nodes Nb to Nm on the selection character line. As shown in the above description, according to the structure of the fifth embodiment, the writing word lines in the selected row can cause the data writing current to flow only to a part of the section corresponding to the selected memory cell. Therefore, the path of the data writing current is reduced in resistance, and the required data writing circuit can be easily supplied even at a low voltage operation.

2075-5330-PF (Nl), Ahddub.ptd Page 46 200301480 V. Description of the Invention (43) Stream, and can speed up the data writing operation. In addition, erroneous writing of data to the memory cells of the non-selected row block of the selected row can be suppressed. Modification 1 of Embodiment 5 Referring to FIG. 14, in the structure of Modification 1 of Embodiment 5, compared with the structure of Embodiment 5 shown in FIG. 12, the word line driver further includes and writing characters. The drive switch RGG of the corresponding setting of the element line WWL is different. The drive switch R G G is connected between the intermediate node N m and the ground voltage G N D. For example, a drive switch RGG 1 which is arranged to correspond to the writing character line WWL1 and is electrically connected between the intermediate node Nm and the ground voltage GND. The control of the extreme output can be implemented by the selected row of the WRdl. The drive switch RGG may be implemented, for example, by an N-channel M 0 S transistor. When it is selected, the corresponding memory cell row is selected and activated. Signal WRd. For example, when the gate input of the drive switch RGG is in a memory cell row, it becomes active !! Level control signal,. Therefore, in the selection column, the intermediate node N m is connected to the ground voltage ◦ n D by turning on the driving switch RGG ^. The structure of the other parts of the character line driver 30 is the same, and detailed description is not repeated. By using this structure, and the structure of the fifth embodiment = word = L, the writing current of unwanted data is reduced, and the occurrence of data erroneous writing can be more suppressed. Modification 2 of Example 5 Describes the drive of the word line driver. In Modification 2 of Embodiment 5, the switch is arranged with high efficiency. Fig. 1 outlines the configuration of the driving switch of the second modification 5 of the fifth embodiment

200301480 V. Description of the invention (44) Read the picture. In FIG. 15, an example is shown in which the memory array is divided into four row blocks CBi to CB4 along the row direction. In each memory cell column, the writing word line WWL can be commonly provided for the row blocks CB and CB4. As shown in Embodiment 5 and its modification 1, nodes Na, Nb corresponding to one end side and the other end side of each of the writing word lines WWL, and the intermediate node Nm corresponding to the boundary portion of the row block The configuration corresponding to each node drives MRDG & RGG. The drive switch RDG is provided for connecting a corresponding node to a power supply voltage Vcc. The drive switch RGG is provided to connect the corresponding node to the ground voltage gnd. In each memory cell column, the drive switches RDG and RGG are alternately arranged in sequence. For example, in the structural example shown in FIG. 15, for the writing word line WWL j in the j-th column, the node Na corresponding to one end side thereof is (j) A drive switch RDG is provided, and the drive switch RGG is arranged at an intermediate node Nm 1 2 (j) corresponding to a boundary portion of the row blocks CB1 and CB2. From now on, the respective intermediate nodes Nm23 (j) corresponding to the boundary portions of the row blocks CB2 and CB3 and the intermediate nodes Nm34 (j) corresponding to the boundary portions of the row blocks CB3 and CB4 and the writing word lines WWLa The other side of the node rib (j) corresponding to the interactive configuration drive switches RDG, RGG, and RDG ° That is, regardless of the number of rows and blocks, each memory cell column is arranged in the order from node Na to node Nb. One of the M driving switches is formed by one of the driving switches RDG and RGG, and the other of the driving switches RDG and RGG is formed by the even one.

2075-5330-PF (Nl); Ahddub.ptd 200301480 V. Description of the invention (45) When data is written in the selection column, the sum of WWL selects the memory cell corresponding to 'each ^ since eight sum is equivalent to the character line for writing The driving switches RDG and RGG become paralyzed by two nodes at both ends of the part of the track ^-like, write in the selection column = element =, and embodiment 5 and its variations. The current only flows to and selects the memory 罝 _ WL, which enables the data to be written. By adopting this structure ::: The corresponding part of the row block. The material write current only flows to and selects the memory cell 2 ::; Secondly, in the selection column, the #knife interval can be suppressed. Because of this, the data was written by mistake. In addition, by shortening ㈡ =, it is easy to reduce power consumption even at low voltage operation. In addition, the number of dispositions of the movable switch may be; close_touch 'to reduce the drive. In addition, for the writing character line ww 丨 in the (j + l) column, a node and a node Na (m) and an intermediate node Nml2 ( m), Nm23 (jj's

Nm34 (J + 1) and node command (] + 1) correspond to the driving settings of RGG, RDG, RGG, RDG, and RGG. 1 That is, the configuration of the drive switch RDG corresponding to the replacement of the power supply voltage v c c and the drive switch RGg corresponding to the ground voltage GND every adjacent column. In other words, in each §self-memory cell column, if we focus on the odd-numbered drive switches, the types of drive switches arranged in the odd-numbered and even-numbered columns are different. For example, in the odd-numbered columns, the odd-numbered driving switches are each a driving switch RDG corresponding to the power supply voltage vcc, and in the even-numbered columns, each of the odd-numbered driving switches is freely formed with a driving switch RGG corresponding to the ground voltage GND.

2075-5330-PF (Nl); Ahddub.ptd page 49 200301480

V. Description of the invention (46) Therefore, the arrangement pitch of these driving switches can be relaxed, and the arrangement can be performed more efficiently. As a result, the area can be made smaller. In addition, regarding the drive switch RGG corresponding to the ground voltage, the configuration is omitted as in FIG. 1 1, and a structure in which the corresponding intermediate node Nm and the ground voltage GND are directly connected is adopted. Embodiment 6 ° In Embodiment 6, description will be made Figure 11 shows the efficient configuration of the bit line driver. . … • According to FIG. 16, in the structure of Embodiment 6, the bit line BL is divided into complex arrays of each bar (jI: number on X 2 ') in each group, and the other end of the X bit lines The side is electrically connected via a short-circuit node Ns. The structure of the case of p2 is shown as an example in FIG. . Each bit line BL is provided with a bit line driver BDVa for driving a voltage corresponding to a node on one end side. For example, for the bit line Bu, a bit line driver BDVal corresponding to the point Na (1) is set. On the other side of each element line BL, a bit line driver B D V b for driving the short-circuit node electric power is arranged. For example, for the bit line B L1 and BL2 common and corresponding to the node Ns (1), the configuration and operation of the bit line driver BDVM ° bit line driver BDVa and BDVb are as shown in FIG. 11: Repeat the detailed instructions. When data is written, the bit line driver BDVa corresponding to the selection row and the bit line driver BDVb corresponding to the remote selection group_ respond to the writing control signal from the data writing circuit (not shown in the figure). Corresponding node core and "drive as power source ^ £ V cc and ground voltage G Ν ^ each side according to the written data. As a result, the direction of the write current according to the written data to the selected line

2075-5330-PF (Nl); Ahddub.ptd Page 50 200301480 V. Description of the invention (47) Bit line BL. The readout data buses RDB1 and RDB2 are arranged correspondingly along the direction (column direction) crossing the bit line BL and the other end side of the bit line BL. In addition, the respective settings corresponding to the blocks are used to selectively connect the read-out selection gates r [] s G 1, RDSG2, ..., between the read data bus RD B1, RDB 2 and the short-circuit node N s. . The read selection gates RDSGi, RDSG2, ... are arranged outside the bit line driver BDVb. The RDSG1, which is a representative example of the odd-numbered read-out selection gate, responds to the activation of the read-row selection line RCSU $ RCSL2, and shorts the corresponding short-circuit node N s (1) and the read-out data bus R db 1 Connected electrically. The read-out selection gate RDSG2, which is a representative example of the even-numbered read-out selection gate, responds to the activation of the read-row selection line RCSL3 or {^ 讥 4, and shorts the corresponding short-circuit node Ns (2) and the read-out data bus RDB2. When the data is electrically read in between, in response to the activation of the read word line RWL of the selection row, the bit line of the selection row is connected to the ground voltage GND via the selection memory cell. In this state, by using the data readout circuit 55, the data readout current is passed to the readout data buses RDB1, rDB2, and the current and voltage of the readout data buses RDB1, RDB2 are detected, and the self-selecting memory is executed. The information of the unit is read out. Therefore, in the structure of the embodiment 6, since the bit line driver BDVb 'is shared among the X bit lines BL in each group, the arrangement pitch of the bit line driver BDVb can be made X times. Therefore, the selection gates RDSG1, RDSG2,... Can be efficiently arranged. As a result, the wafer area can be reduced.

2075-5330-PF (Nl); Ahddub.ptd Page 51 200301480 V. Description of the invention (48) Modification of embodiment 6 Referring to FIG. 17, the structure of the modification of embodiment 6 is shown in FIG. 16 Compared with the structure, the read selection gates RDSG1, RDSG2,... Are arranged on the inner side of the bit line driver BDVb. The structural factors of other parts are the same as those in Figure 16 and detailed descriptions are not repeated. By placing the readout selection gate inside the bit line driver, the bit line length in the read current path can be shortened relatively, and the resistance of the bit line portion can be reduced. Therefore, the data readout speed and the data readout margin can be improved. In other words, if the readout selection gate is placed outside the bit line driver as shown in FIG. 16, the length of the bit line in the read current path can be shortened relatively, and the resistance of the path can be reduced. Therefore, the data readout speed and the data readout margin can be improved. Alternatively, as shown in the structure shown in FIG. 18, the data buses RDB1, RDB2, and the readout selection gates RDSG1, RDSG2,... May be arranged corresponding to the middle point of the bit line BL. Embodiment 7 In Embodiment 7, a structure in which only a portion of data corresponding to a selected memory cell on a bit line BL can be supplied with a write current after reducing the number of bit line driver configurations is described. Referring to FIG. 19, in the structure of the embodiment 7, the bit line BL is divided into two complex arrays each, and in each group, the middle point (ie, the intermediate node Nm) corresponding to the two bit lines is electrically connected. connection. In Fig. 19, two adjacent bit lines are used to form each group. Each element line BL is provided to drive the node Na corresponding to one end side.

2075-5330-PF (Nl); Ahddub.ptd page 52 200301480 V. Description of the invention (49) 'Voltage bit line driver BDVa and BDVb used to drive the voltage equivalent to the node Nb on the other end side. The structure and operation of the bit line drivers BDVa and BDVb are the same as those shown in FIG. 11 and detailed description will not be repeated. For example, for bit line BL1, the set bit line driver BDVal corresponding to the node "(1), and the set bit line driver BDVbl corresponding to the node Nb (1), the intermediate nodes Nm (l) and Nm ( 2) Electrically connected. When the lean memory is written, when the selected memory cell belongs to the memory block MBa, the write control signal from the data write circuit (not shown) and the remote selection The two bit line drivers BDVa corresponding to the block drive the corresponding nodes Na to the parties who write the data according to the power supply voltage Vcc and the ground voltage gnd. And the two bit line drivers BDVb corresponding to the selection block Do not drive the corresponding node Nb to either the power supply voltage ^ or the ground voltage. P In the case where the selected memory cell belongs to the memory block MBb, the two bit line drivers corresponding to the selected block will correspond to Each of the node ribs 2 is driven by the power supply voltage Vcc and the ground voltage GND according to each μ of the written data, and the 2 bit line drivers corresponding to the remote selection block β j) ν a does not drive the corresponding node Na as the power supply voltage Either Vcc or ground voltage GND. The configuration bit line driver that does not correspond to the intermediate node is the same as that shown in Figure 1 1 = No structure. On the bit line of the selection line, the direction can be written according to the data of write ^ gree + data. The current flows only to and selects the memory. The corresponding points of the unit are between Na ~ Nm or between nodes Nb ~ Nm). Therefore, the path of data writing current can be reduced in resistance, and it can also be easily supplied during low voltage operation.

200301480 V. Description of the invention (50) --- Write current to the required data, and speed up the data writing operation. In addition, it also suppresses erroneous writing of data to non-selected memory cells in the selected row. The bit line drivers BDVa and BDVb of the 'non-selected group' at the time of lean writing to prevent unwanted current flow drive the corresponding nodes Na and Shuai to the ground voltage GND. In addition, at the time of data writing, the respective element line drivers BDVa and BDVb do not drive the corresponding nodes Na and Nb to either the power supply voltage Vcc or the ground voltage gnd. The read data buses rDB1 and RDB2 are arranged along the direction (column direction) that intersects the bit line BL and the other end side of the bit line BL. In addition, respective settings corresponding to the blocks are used to selectively connect the readout data buses RDB1, RDB2 and corresponding readout selection gates RDSG1, RDSG2,... This is the representative example of the odd-numbered read-out selection gate. The read-out selection gate RDSG1 responds to the activation of the read-line selection line RCSL1 or RCSL2. The corresponding bit line (BL2) and the read data bus RDB1 Connected electrically. The read-out selection gate RDSG2, which is a representative example of the even-numbered read-out selection gate, responds to the activation of the read-row selection line RCSL3 or RCSL4 'to the corresponding bit line (BL4) and the read data bus RDB2. Connected electrically. Therefore, by using the data readout circuit 55, the readout current is passed to the readout data buses RDB1 and RDB2, and the current and voltage of the readout data buses RDB1 and RDB2 are detected to execute the data of the self-selected memory cell. read out. Modification of Embodiment 7 Referring to FIG. 20, the structure of a modification of Embodiment 7 is shown in FIG. 19

2075-5330-PF (Nl); Ahddub.ptd Page 54 20031480 V. Compared with the structure of (51) of the invention, the read data buses RDB1 and RDB2 corresponding to the intermediate node N m of the bit line BL The arrangement is different in the central portion of the bit line BL. The structural factors of other parts are the same as those in Fig. 19, and detailed descriptions are not repeated. By adopting this structure, compared with the structure shown in FIG. 19, the bit line length in the read current path can be shortened to reduce the resistance of the bit line portion. Therefore, in addition to the effect of the structure of the embodiment 7, the withdrawal rate can be referred to as the data purchase speed and the data read margin.

2075-5330-PF (Nl), Ahddub.ptd Page 55 200301480 Brief Description of Drawings Figure 1 is a schematic block diagram showing the overall structure of a MARA module according to an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating the structure of the memory array of Embodiment 1. FIG. Fig. 3 is a structural diagram for explaining the arrangement of the current feedback wiring shown in Fig. 2. FIG. 4 is a circuit diagram showing the structure of the data writing circuit shown in FIG. 2. FIG. Fig. 5 is a circuit diagram illustrating the structure of a memory array according to a modification of the first embodiment. FIG. 6 is a circuit diagram showing a structure of a memory array of the second embodiment.

FIG. 7 is a conceptual diagram illustrating the arrangement of bit lines in Embodiment 3. FIG. Fig. 8 is a conceptual diagram showing the arrangement of bit lines in a modification of the third embodiment. FIG. 9 is a circuit diagram showing a structure of a memory array of Embodiment 4. FIG. Fig. 10 is a circuit diagram showing a structure of a memory array according to a first modification of the fourth embodiment. Fig. 11 is a circuit diagram showing a structure of a memory array according to a second modification of the fourth embodiment. Fig. 12 is a circuit diagram illustrating the supply of a data write current to the write word line of the fifth embodiment.

Fig. 13 is a circuit diagram showing the structure of the current supply circuit shown in Fig. 2. Fig. 14 is a circuit diagram showing the structure of a memory array according to the first modification of the fifth embodiment. FIG. 15 is a diagram illustrating the configuration of a driving switch according to the second modification of the fifth embodiment.

2075-5330-PF (Nl); Ahddub.ptd Page 56 200301480 Simple illustration of the diagram Fig. 16 is a circuit diagram showing a peripheral structure of the memory array of the sixth embodiment. Fig. 17 is a first circuit diagram showing a peripheral structure of a memory array according to a modification of the sixth embodiment. Fig. 18 is a second circuit diagram showing a peripheral structure of a memory array according to a modification of the sixth embodiment. Fig. 19 is a circuit diagram showing a peripheral structure of the memory array of the seventh embodiment. Fig. 20 is a circuit diagram showing a peripheral structure of a memory array according to a modification of the seventh embodiment. FIG. 21 is a schematic diagram showing the structure of an MTJ memory cell. Figure 22 is a conceptual diagram illustrating the data read operation from the MT J memory unit. Fig. 23 is a conceptual diagram illustrating the data writing operation for the MTJ memory cell. Fig. 24 is a conceptual diagram illustrating a relationship between a data write current and a magnetization direction of a tunnel magnetoresistive element when writing data to an MTJ memory cell. Component symbol description1 MARA component, 10-memory array, 20-column decoder, 25-row decoder, 30-word line driver, 51 data writing circuit, BL, / BL bit line, ADD address signal,

2075-5330-PF (Nl), Ahddub.ptd Page 57 200301480 Schematic description of ATR access transistor, CB row block, CSG row selection gate, DIN write data,

Mba, MBb memory block, RCSL read line selection line, RL current feedback wiring TMR tunnel magnetoresistive element, WCSL write line selection line, WWL write word line, CGa, CGb line control gate CA line Address, CSG row selection gate, CSL row selection line, GND ground voltage, MC MT J memory cell, RDSG read selection gate,, RWL read word line,

Vcc power supply voltage, / WDB inverting data bus, I p, ± I w data write current, pole, SPLa, SPLb current supply wiring, 3 1, 3 1 a, 3 1 b current supply circuit,

Ml, M2, M3, M4 metal wiring layer, WCSLe, WCSLo write line selection line, DBP, DBPa, DBPb data bus pair, BDVa, BDVb, BDVm bit line driver, WCSG, WCSGe, WCSGo write line selection Gate, CDGa, CDGb, WDG, RDGa, RDGb, RDG, RRG drive on

DBo, DBe, DBr, DB1, DB, DBa, DBb, / DB, / DBa, / DBb data bus.

m i

2075-5330-PF (Nl); Ahddub.ptd Page 58

Claims (1)

200301480 VI. Application Patent Scope 1. A thin-film magnetic memory device, comprising: a plurality of memory units arranged in a matrix, each of which memorizes the data written in response to the application of a first and a second data writing magnetic field; Word lines, each corresponding to a plurality of memory cell rows, are selected in a row so that a first data write current that generates the first data write magnetic field flows in a predetermined direction; a plurality of first bit lines, each and a plurality A corresponding setting of the memory cell row; and a data writing circuit, in the selected row, among the corresponding first bit line and the corresponding part of the selected memory cell, so that the second data writing magnetic field is generated The data writing current flows in the direction of writing the data. The data writing circuit includes a plurality of bit line driving sections. Each row of the plurality of memory cell rows is corresponding to one end side corresponding to the first bit line. Corresponding to the first node, the second node corresponding to the other end side, and at least one intermediate node; in the selected row, the plural bit line driver Among the moving parts, two of the two ends of the part corresponding to the selected memory unit set the corresponding nodes on the first bit line to the first and second voltages according to each of the written data. 2. The thin film magnetic memory device according to item 1 of the patent application scope, further comprising: first and second data lines, each corresponding to the one end side and the other end side of the first bit line; And inverted data lines, used to communicate the first and 2075-5330-PF (Nl), Ahddub.ptd Page 59 20031480 VI. Patent application scope 2 Data line complementary data; The data writing circuit will write the first and One of the second data lines is set to one of the first and second voltages, and the inverting data line is set to the other of the first and second voltages; the plurality of bit line driving sections each have: a first And a second driving switch are respectively disposed between the first and second nodes on the corresponding first bit line and the first and second data lines; and a third driving switch are disposed on the corresponding first bit Between one of the intermediate nodes on the meta-line and the inverted data line; when the data is written, in the selected row, one of the first and second drive switches and the third drive switch become conductive. 3. The thin film magnetic memory device according to item 1 of the patent application scope, which includes: a plurality of second bit lines, each corresponding to a plurality of memory cell rows, and complementary to each corresponding first bit line Bit line pairs; and first and second data line pairs, each corresponding to the two ends of the first bit line; the first and second data line pairs each include 2 data lines, write in the data It is used to communicate two pieces of data that are complementary to each other. The data writing circuit will set up the two data lines that constitute one of the first and second data line pairs according to the written data when the data is written. One of the first and second voltages and the other; the plurality of bit line driving sections each have: 2075-5330-PF (Nl); Ahddub.ptd Page 60 20031480 Sixth, patent application scope First drive switch, the first node on the corresponding first and second bit line and the first data line pair Between; the second driving switch is provided between the corresponding second node on the corresponding first and second bit lines and the second data line pair; and the third driving switch is provided between the corresponding first bit Between one intermediate node on the line and one intermediate node on the corresponding second bit line; when the data is written, in the selected row, one of the first and second drive switches and the third drive switch Turns on. 4. For example, the thin film magnetic memory device of the scope of application for the patent, wherein when the data is written, in the selection row, the first and second switches are in accordance with the position relationship between the selection memory unit and the intermediate node. Selectively becomes conductive. 5. For example, the thin film magnetic memory device of the scope of application for a patent, wherein each of the memory cells includes: a magnetoresistive element whose resistance changes in accordance with the written data; and an access element, which is at a predetermined voltage and Correspondingly, the first bit line is connected in series with the magnetoresistive element; when data is read, the access element becomes conductive at least in the selected memory unit; the thin film magnetic memory device further includes: The data lines are arranged along the direction intersecting the plural first bit line and corresponding to one of the at least one of the intermediate nodes; and the readout selection gates, respectively, with the plural first bit line Corresponding device 2075-5330-PF (Nl); Ahddub.ptd Page 61 20031480 6. The scope of the patent application is used to selectively connect the one intermediate node corresponding to the first bit line and the one when the data is read out. Read between the data lines. 6. The thin film magnetic memory device of claim 5 in which the one intermediate node is located at about the center of each of the plurality of first bit lines. 7. For the thin film magnetic memory device of the first patent application range, wherein the plurality of bit line driving sections each include: a first driver transistor, a corresponding node provided on the first bit line and the first bit line The data writing circuit is used to control opening and closing between voltages; and a second driver transistor is provided between a corresponding node on the first bit line and the second voltage, and the data writing circuit is used to control opening and closing. 8. A thin-film magnetic memory device, comprising: a plurality of memory cells arranged in a row shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; the word lines for plural writing, each The setting corresponding to the plural memory cell row, in the selected row, causes the first data writing current that generates the first data writing magnetic field to flow in a predetermined direction; the plural bit lines, each corresponding to the plural memory cell row It is provided that the second data write current that generates the second data write magnetic field flows in the direction of writing the data in the selection exercise order; and the word line driving circuit for writing, in the selection row, in the corresponding write At least a part of the character line is used to make the first data write current flow; the write character line drive circuit is in the selected row, the first node corresponding to one end side of the corresponding write character line, Equivalent to the other side 2075-5330-PF (Nl), Ahddub.ptd Page 62 20031480 Six. Among the second node of the patent application scope and at least one intermediate node, the two nodes located on both sides of the part corresponding to the selected memory unit For each of the first and second voltages. 9. The thin film magnetic memory device according to item 8 of the scope of patent application, wherein the writing word line drive circuit includes M drive switches from the first to M (M: an integer of 3 or more), and In each of the memory cell columns, the first node, the at least one intermediate node, and the second node corresponding to the corresponding writing character line are arranged in this order in a direction from the one end side to the other end side; In each of the memory cell columns, the odd-numbered driving switches are respectively disposed between one of the first and second voltages and corresponding nodes, and the even-numbered driving switches are respectively disposed at the other of the first and second voltages. And the corresponding node; among the M drive switches, the two drive switches located at both ends of the portion corresponding to the selection memory unit become conductive. 10. The thin-film magnetic memory device according to item 9 of the scope of patent application, wherein, in the odd-numbered row, the odd-numbered drive switches are respectively disposed between one of the first and second voltages and the corresponding node; For the even-numbered columns, the even-numbered driving switches are respectively disposed between the other of the first and second voltages and the corresponding node. 11. A thin-film magnetic memory device, comprising: a plurality of memory cells arranged in a matrix, each of which stores data written in response to the application of a first and a second data writing magnetic field; word lines for plural writing, and Settings corresponding to plural memory cell rows 2075-5330-PF (Nl); Ahddub.ptd page 63 20031480 6. Set the scope of patent application, select the row so that the first data writing current that generates the first data writing magnetic field flows in a predetermined direction; The digital line, each corresponding to a plurality of memory cell rows, is selected to exercise the second data writing current that generates the second data writing magnetic field to flow in a direction according to the written data; and the writing word line The driving circuit, in the selected column, causes the first data writing current to flow in at least a portion of the corresponding writing word line; each writing word line is connected to a first voltage at an intermediate node; the writing use The word line drive circuit includes first and second drive switches, and each of the plurality of memory cell rows corresponds to a first node corresponding to one end side and a second node corresponding to the other end side on the corresponding writing character line. In the selection column, one of the first and second drive switches selected according to the positional relationship between the selected memory cell and the intermediate node connects the corresponding node to the second voltage. 1 2. A thin-film magnetic memory device comprising: a plurality of memory units, each of which stores data after being magnetized in a direction in which a magnetic field is written in accordance with the applied data; a plurality of bit lines, each of which is separately distinguished from the plurality of memory units A corresponding setting; and a data writing circuit, for at least one of the plurality of bit lines, supplying a data writing current that generates a data writing magnetic field in accordance with a direction of writing the data; the data writing circuit includes a plurality of First drive circuit, each and the complex 2075-5330-PF (Nl); Ahddub.ptd Page 64 20031480 Sixth, the corresponding settings of the patented digital line, each driving the voltage on one end side of the corresponding bit line; the complex bit line is divided into a complex array ; Each of the plurality of arrays has X (X: an integer of 2 or more) the bit lines, and the other ends are electrically connected via a short-circuit node; the data writing circuit further includes a plurality of second driving circuits, each of which is connected to the The corresponding setting of the plurality of arrays respectively drives the voltage corresponding to the short-circuit node; the sum of the plurality of first driving circuits selects at least one corresponding to the memory cell to drive the one of the first and second voltages according to the written data Corresponding one end side; at least one of the plurality of second driving circuits and corresponding to the selection memory cell drives the corresponding short-circuit node at the other of the first and second voltages according to the written data. 1 3. The thin-film magnetic memory device according to item 12 of the scope of patent application, wherein each of the memory cells includes: a magnetoresistive element whose resistance changes in accordance with the magnetization direction; and an access element at a predetermined voltage and corresponding Bit lines are connected in series with the magnetoresistive element; during data reading, the access element becomes conductive at least in the selected memory unit; the thin film magnetic memory device further includes: a data line for reading, along The direction that intersects the complex bit line, and the configuration corresponding to the other end side of the complex bit line; and the readout selection gates, each corresponding to the setting of the complex array, respectively 2075-5330-PF (Nl); Ahddub.ptd Page 65 200301480 6. Scope of patent application When the data is read, it is used to selectively connect the corresponding short-circuit node with the data line for reading. 1 4. A thin-film magnetic memory device, comprising: a plurality of memory cells, each of which is magnetized in the direction of a magnetic field written in accordance with the applied data, and memorizes lean materials, and a plurality of bit lines are respectively distinguished from the plurality of memory cells. A corresponding setting; and a data writing circuit, for at least one of the plurality of bit lines, supplying a data writing current that causes the data writing magnetic field to be generated in accordance with the direction of writing the data; the plurality of bit lines are divided into A complex array; each of the complex arrays has two of the bit lines electrically connected between intermediate points; the data writing circuit includes: a plurality of first driving circuits, each corresponding to the plurality of bit lines, and each driving A voltage on one end side of the corresponding bit line; and a plurality of second driving circuits, each corresponding to the plurality of bit line settings, each driving a voltage on the other end side of the corresponding bit line; Including at least one of the selected memory cells, one of the corresponding two of the first driving circuits and the corresponding two of the second driving circuits in accordance with the writing And the corresponding expected one end side of the two bit line of the other end side of the respective drive for the one of the first and the second voltage. 15. The thin film magnetic memory device according to item 14 of the scope of patent application, wherein each of the memory units includes: 2075-5330-PF (Nl); Ahddub.ptd Page 66 20031480 Six. Patent application range Magnetoresistive element whose resistance changes according to the direction of magnetization; and access element, between a given voltage and corresponding bit line and The magnetoresistive element is connected; when data is read, the access element becomes conductive at least in the selection memory unit; the thin film magnetic memory device further includes: a data line for reading, along with the plurality of bits The direction in which the lines intersect, and the configuration corresponding to each of the intermediate points of the complex bit line; and the selection gates for reading, the settings corresponding to each of the complex arrays, which are used for selective connection when the data is read Corresponds between the intermediate point and the readout data line. 2075-5330-PF (Nl); Ahddub.ptd p. 67