TW578150B - Thin film magnetic memory device writing data with bidirectional current - Google Patents

Abstract

An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

Description

578150

[Technical field to which the invention belongs] The present invention relates to a thin-film magnetic memory device, and more specifically, to a memory unit including: a magnetic unit having a magnetic tunnel junction (MTJ: "Tunnel" mouth Tunnel Junction) Random access memory. [Previous Technology] MRAM (Magnetic Random Access Memory) components have attracted attention in memory devices that can permanently store data with low power consumption. The MRAM module is a memory device that uses permanent memory data of a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit, and can be randomly accessed for each thin film magnetic body. In particular, in recent years, the use of a tunnel magnetoresistive element using a thin film magnet of a magnetic tunnel junction (MTJ: Magnetic Tunnel Junction) in a memory cell has been reported, and the performance of MRAM devices has improved dramatically. The report on MRAM components including: a memory cell with a magnetic track interface is shown in the following technical literature.

Roy Scheuerline et.al A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell, 2000 IEEE ISSCC Digest of Technical Papers, TA7.2, pl28-129 o M. Dur1 am et.al Nonvolatile RAM based on Magnetic Tunnel Junction Elements1 ', 2000 IEEE ISSCC Digest of Technical Papers, TA7.3, pl3〇-131 〇 Peter K. Naji et.al A 256kb 3.0V 1T1MTJ

2075-5330-PF (Nl); Ahddub.ptd Page 5 578150 V. Description of the invention (2)

Nonvolatile Magnetoresistive RAM-, ISSCC Digest of

Technical Papers, TA7.6, pl22-123. Fig. 21 is a schematic diagram showing the structure of a memory unit (hereinafter also simply referred to as "MTJ memory unit") having a magnetic tunnel junction. Referring to FIG. 21, the MTJ memory cell includes: a track magnetoresistive element tmr, which: the resistance changes in accordance with the level of the memory data; and the access element atr for reading the material atr to form a tunnel magnetoresistive element TMR = IS path. The access element ATR is represented by an electric field effect; I !,: The body is formed, and the access element ATR is also referred to as an access element ^^ = 曰 ATR in the following. The access transistor ATR is connected between the track magnetoresistive element τ ^ (ground voltage GND).口 疋 电 For the MTJ memory cell, the write character line is configured to write; the read character line RWL is used to perform data read; and the data is used to transmit and read data during data read and data write. Memory 70 ▲ BL, the data line of the corresponding electrical signal. —Data Bits Figure 22 illustrates the data read from the MTJ memory cell. Refer to FIG. 22 for the concept of the masterpiece. The tunnel magnetoresistive element TMr has strong magnetism and is only referred to as “fixed magnetization layer”. FL has a fixed magnetization side: (hereinafter also referred to as a bulk layer (hereinafter also referred to as “free magnetization layer”) VL is magnetized in the direction of the applied magnetic field of the strong part; and the antiferromagnetic layer ^ is provided between the externally fixed magnetization layer FL and the free magnetization layer VL for insulation ^ L, ° on the fixed barrier (tunnel film) TB. The free magnetization layer VL is in the same direction as the fixed magnetization layer FL or the opposite direction of the 5th memory data according to the level of the written tunnel.

2075-5330-PF (Nl); Ahddub.ptd Page 6 578150 V. Description of the invention (3). A magnetic tunnel junction is formed using the fixed magnetization layer FL, the tunnel barrier TB, and the free magnetization layer VL. When the data 1 is purchased, the access transistor ATR is turned on in accordance with the activation of the read word line RWL. Therefore, the data readout current s can be made to flow to the bit line BL to the track magnetoresistance TMR to the access transistor ATR to the ground voltage gnd. The resistance of the track magnetoresistive element TMR varies according to the relative relationship between the respective magnetization directions of the fixed magnetization layer FL and the free magnetization layer VL. Specifically, the resistance of the tunnel magnetoresistive element TMR in the case where the magnetization direction of the fixed magnetization layer FL and the magnetization direction of the free magnetization layer VL are the same (parallel) is greater than the case where the magnetization directions of the two are opposite (anti-parallel). small. Therefore, 'if the free magnetization layer VL is magnetized in accordance with the direction of the memory data', the voltage change of the data readout current Is occurring in the tunnel magnetoresistive element TMR varies according to the level of the memory data. Therefore, for example, after pre-charging the bit line BL to a fixed voltage, if the data read current Is is made to flow to the tunnel magnetoresistive element TMR ', by detecting the voltage of the bit line b L, the μ TJ memory cell can be read. Memory data. Figure 23 is a conceptual diagram illustrating the data writing operation for the MT J memory unit.

Referring to Fig. 23, when data is written, the read word line RWL becomes inactive, and the access transistor ATR becomes non-conductive. In this state, the data write currents used to magnetize the free magnetization layer VL in the direction in which the data are written respectively flow to the writing word line WWL and the bit line BL. The free magnetization layer VL is determined according to the data writing current flowing through the writing word line WWL and the bit line BL.

2075-5330-PF (Nl); Ahddub.ptd Page 7 578150 V. Description of the magnetization direction of the invention (4) Figure 24 illustrates the data write current and tunnel magnetoresistance when writing data to the MTJ memory cell Conceptual diagram of the relationship between the magnetization directions of the components. Referring to Fig. 24, the horizontal axis H (EA) represents a magnetic field acting on the free magnetization layer VL in the tunnel magnetoresistive element TMR in the direction of an easy axis (EA: Easy Axis). The vertical axis H (HA) represents a magnetic field acting on the free magnetization layer VL in the direction of a hard magnetization axis (HA: Hard Axis). The vertical axis Η (HA) and the horizontal axis EA (EA) each correspond to one of two magnetic fields generated by the currents flowing through the bit line BL and the writing word line WWL, respectively. In the MTJ memory unit, the fixed magnetization direction of the fixed magnetization layer FL is along the easy magnetization axis, and the free magnetization layer VL is along the direction of the easy magnetization axis according to the level of the memory data (" 1, and π 〇 "). , Magnetize in a direction parallel (same) or anti-parallel (opposite) to the fixed magnetization layer FL. Hereinafter, in this patent specification, the resistances of the tunnel magnetoresistive element TMR corresponding to the two types of magnetization directions of the free magnetization layer VL are respectively represented by R1 and R0 (but R1> R0). The MTJ memory unit can store 1-bit data (π Γ and " 0Π) corresponding to the two magnetization directions of the free magnetization layer VL. The magnetization direction of the free magnetization layer VL can be rewritten only when the sum of the applied magnetic fields Η (ΕΑ) and Η (ΗA) reaches the area outside the star-shaped characteristic line shown in the figure. That is, in the case where the applied data writing magnetic field is equivalent to the strength of the region inside the star-shaped characteristic line, the magnetization direction of the free magnetization layer V l is unchanged. As shown by the star-shaped characteristic line, by applying a magnetic field in the axis direction of the hard magnetization to the free magnetization layer VL, it is possible to reduce the need to change the magnetization direction along the easy magnetization axis.

578150 Fifth, the magnetization threshold of invention description (5). In the case of designing the operating point when data is written as shown in the example of FIG. 24, in the MTJ memory unit of the data writing target, the data writing magnetic field in the direction of easy magnetization axis is designed so that its intensity becomes HWR. That is, the data writing current value of the data flowing on the bit line BL or the writing word material 1 is designed so that the data writing magnetic field HWR is obtained. Generally, the data writing magnetic field HWR is expressed by the sum of the switching magnetic field Hsw and the edge limit ΔΗ required for switching the magnetization direction. That is to say HWR = Hsw + △ Η. In addition, in order to rewrite the memory data of the MT J memory cell, that is, the magnetization direction of the tunnel magnetoresistive element TMR, it is necessary to make the data written above the alignment accuracy current flow to both the writing word line WWL and the bit line BL. Therefore, the free magnetization layer VL in the tunnel magnetoresistive element TMR is magnetized in a direction parallel to or opposite (anti-parallel) to the fixed magnetization layer FL in a direction in which the magnetic field is written along the direction of the easy magnetization axis (ea). The magnetization direction of the TMR-degree writing of the tunnel magnetoresistive element, that is, the memory data of the MTJ memory unit, is permanently maintained until new data writing is performed. Therefore, the resistance of the tunnel magnetoresistive element TMR changes according to the magnetization direction that can be rewritten by writing the magnetic field with the applied data. By making two kinds of magnetization directions of the free magnetization layer VL in the magnetoresistive element TMR and the surprise The data levels (π Γ and 1 '0π) correspond to each other, and permanent data memory can be performed. Therefore, in the MARA module, when data is written, it is necessary to reverse the magnetization direction of the on-track magnetoresistive element Mr in the MTJ memory unit selected as the object of data writing. Therefore, it is necessary to control the direction of the data writing current to the writing word line WWL and the bit line BL according to the level of the written data. Thus, providing

Write the data to the chip size and increase the current circuit structure. Make complicated

The content of the invention is to make a MARA piece. [The present invention is made with a simple stream. The purpose is to provide a circuit structure that can write data according to the data level of a thin film magnetic memory device. Each of the units listed in the magnetic field is connected to one of the same bit lines that make the second z-direction material bit line. The thin film 4 lines are written in correspondence with a plurality of data records and the flow of data is written; the direction corresponds to the magnetic body of the selected line, the respective data; the setting, the single-input magnetic field of the memory and the multiple settings; the second level Meta-line memory recall device, including memory of complex numbers written in the second current selected to the current pair of lines. Metadata writers and corresponding complex numbers should write the first and second data respectively and the word lines. The column makes the setting of the flow in a certain direction. The data is written in the electrical feedback wiring line and the current at one end of the plurality of electrical currents is fed back to the first asset. Therefore, the main advantage of the present invention is that in the thin film magnetic body, the bit line and the corresponding electricity are selected according to the connection between the ends of the thin film magnetic body. The voltage setting can control the direction of the current flowing on the selected line. As a result, it is possible to simplify the circuit configuration for controlling the direction in which the data is written in accordance with the material level. The structure of the electric body is written into the magnetic data record element, so that the plural wiring is written, the electric current is memorized, and the flow is returned to the selected line.

2075-5330-PF (Nl); Ahddub.ptd Page 10 578150 V. Description of the invention (7) The thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory cells, arranged in a matrix, and each memory response The data written by the application of the first and second data writing magnetic fields; the plural writing word lines, each corresponding to the plurality of memory cell rows, are arranged in a selection row so that the first data writing magnetic field is generated; A data write current flows in a predetermined direction; a plurality of bit lines, each corresponding to a row of a plurality of memory cells, are set in a selected row so that a second data write current that causes a second data write magnetic field to follow the write Data flows in the direction; the plurality of first row selection lines are respectively arranged in K (K: an integer of 2 or more) each memory cell row corresponding to each and a different row address forming a row block; K second rows The selection line is used to select one of the corresponding K memory cell lines in each line block; the line decoder makes one of the plurality of first line selection lines and the K second line selection lines according to the line selection result. Among And selective data activation circuits; and a data writing circuit, in accordance with a plurality of first row selection lines and K second row selection lines, setting one end side and the other end side of the bit line of the selection row according to the first and Each side of the second voltage writing data. This thin-film magnetic memory device executes row selection by using a combination of row block selection each composed of a plurality of memory cell rows and selection of memory cell rows in each row block, which can reduce signals required for row selection. Number of wiring. The thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory units arranged in a row and shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; Lines, each corresponding to a plurality of memory cell columns, are set in the select column so that

2075-5330-PF (Nl); Ahddub.ptd Page 11 578150 V. Description of the invention (8) ~-The first data writing current of the first data writing magnetic field moves in a predetermined direction; the first plural number of the plural Lines, each corresponding to a plurality of memory cell rows corresponding to 3 μ sets; and a data writing circuit, in the selection row, in the corresponding first ^ ″ destruction and the corresponding portion of the selected memory cell 'to make the second time ^ The second data write current written into the magnetic field is driven in the direction of the written data; it includes a complex bit line driver 'on the complex memory cell row < row, respectively, and the corresponding first bit line The setting corresponding to the point ~ f of one end side, the second node corresponding to the other end side, and at least one intermediate node; in the selection line, the slant in the plural bit line driver and the selection memory Two of the two ends of the part corresponding to the body unit set the corresponding nodes on the bit line as the first and second voltages according to writing and data. This thin-film magnetic memory device, in the bit line of the selection line, can cause the data write current to flow only to a part of the interval corresponding to the long-selected memory. Therefore, the path of the data writing current can be made low-resistance, and the required data writing current can be easily supplied during low-voltage operation, and the data writing operation can be speeded up. In addition, erroneous writing of data in the memory cells of the non-selected memory block of the selected row can be suppressed. A thin-film magnetic memory device of another structure of the present invention includes a plurality of memory units arranged in a row and row format, each of which stores data written in response to the application of the first and second data writing magnetic fields; The respective settings of the "metaline" and the plural memory cell row are selected in the selected row so that the first data writing current that generates the first data writing magnetic field flows in a predetermined direction; the plural bit line, the respective and plural memory Unit line corresponding settings'

2075-5330-PF (Nl); Ahddub.ptd Page 12 578150 V. Description of the invention (9) The current of writing the second data to the magnetic field of the second data in the selection order is in accordance with the direction of writing the data Flowing; and a writing word line driving circuit, in the selection row, causing the first data write current to flow in at least a portion corresponding to the writing word line; the writing word line driving circuit selects Column, corresponding to the first node corresponding to the one end side, the second node corresponding to the other end side, and at least one of the intermediate nodes on the corresponding writing character line, two of the portions corresponding to the selected memory unit The two nodes on the side are each one of the first and second voltages. In this thin film magnetic memory device, in the writing word line of the selection line, the data writing current can flow only to a portion corresponding to the selection memory cell. Therefore, the path of the data writing current can be reduced in resistance, and the required data writing current can be easily supplied during low-voltage operation, and the data writing operation can be speeded up. In addition, erroneous writing of data to memory cells in non-selected memory blocks can be suppressed. The thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory units arranged in a row and shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; Lines, each corresponding to a plurality of memory cell rows, in the selected row, the first data writing current that causes the first data writing magnetic field to flow in a predetermined direction; a plurality of bit lines, each and a plurality of memory cells The corresponding setting of the row, the second data writing current that generates the second data writing magnetic field is selected to flow in the direction according to the written data; and the word line driving circuit for writing is in the selected column, corresponding to At least a part of the writing character lines causes the first data writing current to flow; each writing character line is at an intermediate node

2075-5330-PF (Nl); Ahddub.ptd Page 13 578150 V. Description of the invention (ίο) and first voltage connection; the writing word line drive circuit includes first and second drive switches, and in the complex memory The body unit columns are respectively corresponding to the first node corresponding to one end side and the second node corresponding to the other end on the corresponding writing character line; in the selection column, the first and second driving switches One of them is selected according to the position relationship between the selected memory cell and the intermediate node, and the corresponding node is connected to the second voltage. The thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory units arranged in a row and shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; Lines, each corresponding to a plurality of memory cell columns, in a selected row, the first data writing current that causes the first data writing magnetic field to flow in a predetermined direction; the plurality of first and second bit lines, each The setting corresponding to the plurality of memory cell rows, in the selection exercise order, the second data writing current that generates the second data writing magnetic field flows in the direction according to the written data; the selection switch, and each row of the plurality of memory cell rows. Corresponding settings are used to electrically connect one end side of the corresponding first and second bit lines in the selection line; and a data writing circuit that, when data is written, the first corresponding to the selection line And the other end side of the second bit line is set to each of the first and second voltages according to the written data; each wiring layer is used on a different wiring layer than the upper layer side of the plurality of memory cells Each of the first and second bit lines is provided from the formed first and second metal wiring lines, and the first and second bit lines corresponding to the same memory cell row are arranged in a predetermined area in the vertical direction to cross in the vertical direction. This thin-film magnetic memory device can electrically connect the data writing current to one end side according to the direction of the reciprocating current.

2075-5330-PF (Nl); Ahddub.ptd Page 14 578150 V. Description of the invention (11) The first and second bit lines of the selection line. Therefore, it is possible to simplify the circuit structure that controls the direction of the data write current in accordance with the write data level. In addition, because the respective reverse current flows in the first and second bit lines adjacent to each other in the up and down direction, the magnetic noise generated from the first and second bit lines of the selected row is weakened in other memory cells. Directional effect. Therefore, it can reduce the influence of magnetic noise, prevent data from being written by mistake, and stabilize the operation. The thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory units arranged in a row and shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; Lines, each corresponding to a plurality of memory cell rows, in a selected row such that the first data write current that generates the first data write magnetic field flows in a predetermined direction; and a plurality of first and second bit lines, The settings corresponding to the rows of the plurality of memory cells are used to select the second data writing current that generates the second data writing magnetic field to flow in the direction of writing the data; used on the upper side of the plurality of memory cells The first and second metal wirings formed by different wiring layers are provided with respective first and second bit lines, and the first and second bit lines corresponding to the same memory cell row are arranged above and below a predetermined area in the vertical direction. The directions intersect; also includes: a data writing circuit, which selects the distance of the memory cells from the sum of the first and second bit lines corresponding to the selected row when the data is written One end side of the relatively short bit line is set to one of the first and second voltages, and the other end side of the bit line is set to one of the first and second voltages. The other side. This thin-film magnetic memory device uses one of the first and second bit lines of the selection line to approach one of the selection memory cells, so that the direction can be

2075-5330-PF (Nl); Ahddub.ptd Page 15 578150 V. Description of the invention (12) The data writing current of the written data flows. Therefore, in the selection line, in the area not containing the selection memory cell, the data writing current will not flow to the wiring close to the memory cell. As a result, erroneous writing of data to non-selected memory cells can be suppressed in the selected row. A thin-film magnetic memory device of another structure of the present invention includes: a plurality of memory cells, each of which stores data after being magnetized in a direction in which a magnetic field is written in accordance with the applied data; a plurality of bit lines, each of which and each of the plurality of memory cells A corresponding setting of a predetermined division; and a data writing circuit, for at least one of the plurality of bit lines, 'supplying a writing current for generating a data writing magnetic field in accordance with a direction of writing data; a data writing circuit; It includes a plurality of first driving circuits, each setting corresponding to the plurality of bit lines, each driving a voltage on one end side of the corresponding bit line; the plurality of bit lines are divided into a plurality of arrays; each of the plurality of arrays has X (x: An integer of 2 or more) the bit line is electrically connected at the other end side via a short-circuit node; the data writing circuit further includes a plurality of second driving circuits' each corresponding to the complex array setting, and each driving the corresponding short-circuit Node voltage; the sum of the plurality of first driving circuits selects at least one corresponding to the memory cell according to the written data One of the second voltages drives one end of the corresponding one; at least one of the plurality of second driving circuits and the corresponding one of the selected memory cells drives the corresponding short circuit with the other of the first and first voltages according to the written data node. This thin-film magnetic memory device can reduce the chip area by increasing the distance between the bit line and the driving circuit corresponding to the other end side by X times'. A thin-film magnetic memory device according to another aspect of the present invention includes:

2075-5330-PF (Nl); Ahddub.ptd 578l505. Description of the invention (13) Each of the multiple memory cells is magnetized and memorizes data in the direction of the magnetic field written in accordance with the applied data; multiple bit lines, each and A corresponding setting of the predetermined division of the plurality of memory cells; and a data writing circuit, for at least one of the plurality of bit lines, supplying a data writing current that causes the data writing magnetic field to be generated in the direction of writing data The complex bit line is divided into a complex array; each of the complex arrays has two of the bit lines electrically connected between intermediate points; the data writing circuit includes a plurality of first driving circuits, each of which is connected to the complex bit line The corresponding settings respectively drive the voltage on one end side of the corresponding bit line; and the plurality of second driving circuits, each corresponding to the plurality of bit line settings, respectively drive the voltage on the other end side of the corresponding bit line; Among the plurality of arrays, at least one of the selected memory cells, the corresponding two of the first driving circuits, and the corresponding two of the second driving circuits will match the data according to the written data. One of the one end side and the other end side of the corresponding two bit lines is driven to each of the first and second voltages. This thin-film magnetic memory device does not have a chirped area moving circuit at the middle point of the bit line, and in the selected bit line, the data write current can flow only to the interval corresponding to the portion corresponding to the selected memory cell. Therefore, it does not cause an increase in the area of the wafer to reduce the resistance of the data writing current path, and makes it easy to supply the required data writing current during low-voltage operation, and speeds up the body writing operation. In addition, erroneous writing of data to non-selected memory cells in the selected row can be suppressed. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the graph

2075-5330-PF (Nl); Ahddub.ptd 578150 V. The same symbol in the description of the invention (14) represents the same or equivalent part of the embodiment 1 ^ Refer to FIG. 1, the control signal CMD of the MRAM group of the embodiment of the present invention And address guardian Λ μ this —α, ^ t 彳 5 旒 add, perform random access, perform input = and write the material into the write or ^ ^ ^ ^-, and internally decide to move it; carved: The MR AM component 1 receiving the external clock signal includes: obituary 丨 Gacheng k, IMPAy,,., ^ ^ Control circuit 5 'responds to the control signal CMD, and controls the entire MRA Μ component 1 as a whole. Π & iy, υ masterpieces, and memory array 10, which have a plurality of MT J memories arranged in a row, 状-^…, body early. The structure of the memory array 1 0 will be explained in detail later. Each white right ττ seven ratio μ mouth mouth and MTJ § The list of early memory (also referred to as the "memory cell array" below) — Lengtian ~ -Fine DWT ”J Corresponding Arrangement Writing Lines WWL and Γ:: 7 Lines Two and One Line and MTJ Memory Cell Line (Hereinafter also referred to as §self memory cell line 丨) It is expected that AA 3R: 7 3 £ / τ ”) corresponds to the configuration bit line BL. The MRAM component 1 further includes: a column decoder 20, a row line driver 30, and read / write control circuits 50, 60: ;; 3: 3: 2: according to the column address RA indicated by the address signal ADD, and executes the 圮The memory array 10 is selected.醢 Λ nn master-y capture decoding is 2 5 according to the address signal ADD table 仃 address CA execution in the memory array " line selection. The character line drive H3G selects the result according to the row of the column decoder 2G to selectively activate the read character line RWL and selectively activate the character word line WWL at Zijin Temple. Second write ^ Make write CA indicates that it is designated as the data readout or data address and reservation address.

2075-5330-PF (Nl); Ahddub.ptd

Page 18 578150 V. Description of the invention (15) Yuan (hereinafter also referred to as "selected memory unit"). The writing word line WWL is connected to a ground voltage GND in a region 40 on the opposite side of the body array 10 where the word line driver 30 is arranged. The read / write control circuits 5 and 6 are designed to make the data write current and data read out at the time of the output, and the memory cell row corresponding to the data read unit. (Your Majesty is also called \\ 1 to \ select memory cell line BL and placed in the area adjacent to the controller 丨 〇 "· Wei (SI?, From the master to a person x < the general name of the injustice group The representative structure of the memory array and the circuit structure of the memory array 10 to perform data writing operations are shown in FIG. 2. The S-picture memory array 10 is arranged in a row, and the MTJ memory cells MC are arranged in a queue. Each The MTJ memory cell MC includes the level change of the serially connected data. It is used as magnetic information ... Z = μsix two -1 ^ Shiyinyu tunnel magnetoresistive element TMR and used as access power Crystal ATR. As shown above, the typical application of the transistor ATR for access is the M0S transistor that is a type transistor on a semiconductor substrate. Π < The fourth memory port P 77 djt body sheet, and the bit line BL1 BL4 corresponding to these memory cells RWL1, RWL2, and writing character lines WWL1, WWL2 〇 In addition, when the signal lines of writing character lines, reading character lines, and vanfan lines are not comprehensively expressed, the symbol medical [, RWL, and BL means that in the case of a specific writing character line, reading character line, and bit line, these symbols are marked with wwu, RWL1, and BL1. Also, the high-voltage state of signals and signal lines (Power supply voltage Vcc) and page 19 578150 V. Description of the invention (16) The state of the low voltage state (ground voltage GND) is also referred to as the "H" L "level. When the card and the column are pressed, the character line The driver 30 complies with the column decoder 2. The active word line WWL of the selected column is activated and connected to the power supply voltage Vcc. As shown in the description of FIG. 2, one end of each write WL is in the area 40. Connected to the ground voltage GND, material ^ = = flow in a predetermined direction, select and write = state 2 each signal line in the (attentive) thread muscle remains inactive during data writing ': data writing The magnetic field generated by the current Ip in the MTJ memory cell The magnetoresistive element TMR acts in the direction of the hard magnetization axis. However, during the data operation, the data write current flowing in the bit line BL of the selected row is generated by: = direction of the magnetoresistive element in the track of the willow memory cell Therefore, it is necessary to follow the direction of the current of the data writer in accordance with the level of the data DIN to be written. In the following; ^ ^ I w each table is not in the respective written data " 丨 f 'and, 〇 " In the case of the data writing current flowing on the line of the selection line, and the data writing current +

Iw knows that the data write current + ^ and-. The fire, ° Erming is used to supply the bit line direction of the selected row according to the data write current level of the data write level ± Iw structure. Page 20 2075-5330-PF (Nl); Ahddub.ptd 578150 V. Description of the invention (17) In the structure of the embodiment 1, a plurality of current feedback wirings RL are arranged along the same direction as the bit line BL. Each current feedback wiring RL is provided in each row of a plurality of memory cell rows. The memory array 10 is divided into a plurality of row blocks ⑶ each having κ (1 (·· 2 or more integer)) memory cell rows. In FIG. 2, each row structure of two adjacent memory cell rows is shown. An example of a row block CB, that is, κ = 2. In this case, an example in which each row block CB is composed of an odd numbered line and an even numbered line. For example, the first and second memory cell lines constitute a line area. The block CB1 'is composed of the third and fourth memory cell rows. The row block CB2 is provided with the current feedback wiring RL in each row block ⑶. The plurality of memory cell rows belonging to the same row block CB share the current feedback wiring. RL. For example, the current feedback wiring RL corresponding to the row block CB1 is shared by the first and second memory cell rows corresponding to the bit lines BL1 and BL2 respectively. Figure 3 is used to explain the current feedback Structure diagram of the configuration of the grant wiring rl. Referring to FIG. 3, in the structure of Embodiment 1, the MT J memory unit is arranged on the semiconductor substrate. The p-type region PAR on the semiconductor main substrate SUB forms an access transistor ATR. Access transistor ATR has source / drain for n-type region The domains 1 1 0, 1 2 0 and the gate 1 3 0. The source / drain region 1 1 0 is connected to a ground voltage g ν D through a metal wiring formed on the first metal wiring layer M1. The character is in writing The line WWL uses a metal wiring formed on the second metal wiring layer M2. The bit line BL is provided on the third metal wiring layer M3 on the upper side of the tunnel magnetoresistive element TMR. The tunnel magnetoresistive element TMR is arranged for setting and writing Between the second metal wiring layer M 2 of the word line WWL and the third metal wiring layer μ 3 where the bit line BL is disposed.

2075-5330-PF (Nl); Ahddub.ptd Page 21 578150 V. Description of the invention (18) a'- Take the source / drain region of the transistor ATR 12o through the metal film formed in the contact hole 15o The first and first metal wiring layers M1 and M2, the barrier metal 140 and the tunnel magnetoresistive element TMR are electrically connected. The barrier metal 14 is a buffer member provided for electrically connecting the tunnel magnetoresistive element TMR and the metal wiring. ^ As shown above ′ In the MTJ memory cell, the read character line and the write character line WWL are provided as separate wirings. In addition, the writing word line and bit line BL need to generate an iL® input current for generating a magnetic field having a size larger than a predetermined value when data is written. Therefore, the bit lines BL and the writing word lines WWL are formed using metal wiring. The read word line RWL is provided to control the gate voltage of the access transistor atr, and it is not necessary to actively flow a current. Therefore, from the viewpoint of increasing the density, the read word line RWL does not have a new independent metal wiring layer, and is formed on the same wiring layer as the gate 130 using a multi-silicon layer or a multi-sided structure. In the structural example shown in Fig. 3, a metal wiring layer M4 different from the bit line BL is used to form a current feedback wiring RL. However, the current feedback wiring RL may be formed using a metal wiring layer on the lower side of the bit line BL or a metal wiring layer M3 which is the same layer as the bit line BL. Referring to FIG. 2 again, K data buses, reverse data buses / WDBs, and data writing circuits 51 are provided in a region adjacent to the memory array 10. In the case of K = 2, two pieces of data corresponding to the odd and even rows are allocated to the bus DBo and DBe. When writing data, use one of the data buses DBo and DBe and

2075-5330-PF (Nl); Ahddub.ptd Page 22 578150 V. Description of the invention (19) Phase data bus / W D B Supply data write current ± I w. When data is read, one of the data buses DBo and DBe is connected to the selection memory unit. Referring to Fig. 4, the data writing circuit 51 includes a data writing current supply unit 52 and a switching circuit 53. The data writing current supply unit 52 includes a P-channel type MOS transistor 151 for supplying a fixed current at the node NwO; a P-channel type MOS transistor 1 52 for forming a current mirror that controls the passing current of the transistor 1 51 The circuit and the current source 153 ohm write current supply unit 52 also include inverters 154, 155, and 156 that operate by receiving the supply of the operating current from the node nw 0. The inverter 154 inverts the voltage level of the write > material D I N and passes it to the node n w 1. The inverter 1 5 5 inverts the voltage level of the written data D I N and transmits it to the input node of the inverter 5 6. The inverter 156 inverts the output of the inverter 155 to the node ^ 2. Therefore, the voltages of the nodes Nwl and Nw2 are set to one of the power supply voltage Vcc and the ground voltage GND according to the voltage level of the written data DIN. Node Nwl is connected to the inverse data bus / WDB. The switch circuit 53 sets the voltage level according to the selection signal cs0E in which the odd or even rows are not selected. It is also a selective connection between the node nw2 and the data buses db0 and DBe, which are the same as those written in the data. Therefore, at the time of data writing, the data writing circuit 51 will set one of the row selection results according to the data bus DBo and DBe to the same voltage as the data DIN, and set the inverse data bus / WDB is set to a voltage corresponding to the inverse phase of the data DIN. However, when the information is read out:

; Write 2 sets the nodes Nwl & Nw2 to floating state respectively. ”This time, the selection is made in the memory array 10 row. Select the map V, in the row block ⑶ set the row selection line csL and the writing line, the remote selection line CSL during data reading and data writing At the time of entry, 'the protection of the memory cell in the corresponding row block CB is selected', and it becomes the level. Moreover, each writing row selection line WCSL is written in the data: if the corresponding row area is selected The condition of the memory cell rows in the block CB is different. In the block CB of each row, the K write row selection lines for selecting one of the K memory cell rows 2 are arranged. In the case of κ = 2, the arrangement Respective lines for writing lines and odd lines correspond to the writing line auxiliary selection lines 讥 〇 and WCSLe., Writing line and auxiliary line selection lines 讥 〇 are activated to the level when the odd lines become data writing oblique images, and writing lines The sub-selection line WCSLe is activated to the Η level when the even row = the data writing target.... The row decoder 25 controls each row selection line CSL, each writing row selection line WCSL, and the writing sub-selection line WCSL according to the row selection result. 〇 、 Activation and non-activation of WCSLe. Next, it is used to control the bit line BL, The connection control between the material bus and the reverse data bus. The setting row corresponding to the memory cell row selects the gate CSG. The row selection gate CSG is in the odd row on the corresponding bit line BL and the data bus DB. 〇 is electrically connected. The even rows are electrically connected between the corresponding bit line BL and the data bus DBe. Each row selection gate csg becomes conductive in response to the activation of the corresponding row selection line CSL.

2075-5330 > PF (Nl); Ahddub.ptd Page 24 578150 V. Description of the invention (21) For example, in the row block CB1, the row selection gate CSG1 is set between the bit line BL2 and the data bus DBo. The row selection gate CSG2 is provided between the bit line BL2 and the data bus DBe. The row selection gates CSG1 and CSG2 are turned on in response to the activation of the row selection line CSL1. The current feedback wiring RL provided in each row block CB is connected in series between the node / Nd and the inverse data bus / WDB and the selection gate RSG. The selection gate RSG becomes conductive in response to the activation of the corresponding write row selection line WCSL. For example, in row block CB1, the current feedback wiring RL1 and the selection gate RSG1 that becomes conductive in response to the activation of the write row selection line WCSL are connected in series between the inverse data bus / WDB and the node / Nd. In addition, the K bit lines belonging to the same row block are each connected via independent κ write row selection gates and corresponding current feedback wiring RL. The K write-row selection gates become conductive in response to the activation of the corresponding write-row secondary selection line. In the case where the memory cell row corresponding to the bit line BL1 of the odd row is a selected row, the data bus Dbo and the inverse data bus / WDB are set to the Η level according to the level of the data DIN (power supply voltage Vcc ) And L level (ground voltage GND). In addition, since the row selection line csli, the writing row selection line WCSL1, and the writing row auxiliary selection line WCSL0 are activated, the row selection gate CSG1, the selection gate RSG1, and the writing row selection gate WCSGo are turned on. Therefore, using the bit line BL1 and the corresponding current feedback wiring RL1 which are electrically connected through one end of the node / N d and one end thereof, the current can be written in the direction of the data according to the level of the data DIN. earth! w flows to the bit line BL1.

2075-5330-PF (Nl); Ahddub.ptd Page 25 578150 V. Description of the invention (22) Same as the case where the memory cell line corresponding to the bit line BL2 of the even line selects the line, the data bus Dbe and the inverse data bus / WDB are set to one of the Η level (power supply voltage Vcc) and the L level (ground voltage GND) according to the level of the data DIN. In addition, since the row selection line CSL1, the writing row selection line WCSL1, and the writing row auxiliary selection line WCSLe are activated, the row selection gate CSG2, the selection gate RSG1, and the writing row selection gate WCSGe are turned on. Therefore, using the bit line BL2 and the corresponding current feedback wiring RL1 which are electrically connected through one end of the node / N d and one end, the data can be written in the direction of the data DIN. The current ± I w flows to the bit line BL2. Therefore, in the structure of Embodiment 1, a current path including the electric wire for feedback circuit rl connected to the inverse data bus / WDB, which is shared by the K memory cell rows, flows through the bit line BL of the selected row. Data write current ± jw flows. Therefore 'by controlling the voltage levels of K (K-2) data buses [] b ， dbe and inverse data buses / WDB voltage levels shared by the memory cell rows in the memory array 10, The current write current I w can be flowed to the bit line of the selected row according to the data written in the data. That is, the circuit structure for controlling the direction of the data writing current ± I w according to the data writing level can be simplified. On the other hand, during the data read operation, the word line driver 30 activates the read word line RWL of the selected row to a level. The row decoder 25 deactivates each of the write line selection lines WCSL and the write line selection lines wcSLo and WCSLe to the L level. '/

V. Description of the invention (23) Therefore, 'Each one of the memories is set, and one row / WDB is electrically divided ^ ^ 位, the bit line BL and the inverse data bus DBo and DBe i, except: select The memory unit and the data readout circuit of the data confluence supply and connect. Therefore, the data read current is not shown in the figure, and the change of the data bus connected to the memory unit can be read to select the passing current or voltage of the material bus. In addition, in Figure 2 generation #: _ :: memory data. It should be structured, but in Λ table and the fourth memory cell row pair, the signal line is arranged or used for selection: the S memory cell 'also follows the same structure. The modification of the first embodiment is shown in FIG. 5, Example 丨 Compared with the structure made by 4 n2, the structure of the core is omitted, which is different from that shown in FIG. 2 # / WDB ^ Pal P) r ^ ^ guaihui ^ and wiring RL and inversion Data Convergence: Deformation: == Dagger is different. If it is based on the actual material bus / WDB is electrically ^ ^: i.e. Dot / Nd is always written in the opposite direction of the line cV of the inversion shell, the response of the selected row block is corresponding. Therefore, in the non-selected Line two, V1; the selection gate csg becomes non-conducting. IW will not flow. The same: block 'data write current on the bit line BL and WCSGe are both present at the time of output,' also selected by the write line The brake and the corresponding current feedback two are turned on to separate the structure of the modified example of Example 1, a, and lice on the lice. As a result, the action is verified. # 乂, can also order and implement Example 1 The same information is read in 疋, and the selection corresponding to the current feedback wiring RL is omitted.

2075-5330-PF (Nl); Ahddub.ptd

Page 27 578150 V. Explanation of the invention (24) The configuration of the RSG can also perform the same data reading and data writing operations as in the first embodiment. By adopting this structure, the structure of the memory array 10 can be simplified. In addition, in the first embodiment and its modification, the row selection line CSL and the writing row selection line WCSL are arranged along the direction parallel to the bit line BL, that is, the row direction. WCSL0, WCSLe structure 'But these selection lines can also be arranged along any direction. Embodiment 2 Referring to FIG. 6, in the structure of Embodiment 2, compared with the structure of Embodiment 1, the configuration of the current feedback wiring RL in each row of the block is omitted, and the arrangement of the current feedback wiring RL across the memory array 1 The area configuration data buses D b 0, DBe and reverse data buses / WDB on the opposite side are different. As in Embodiment 1, each row block CB has K memory cell rows corresponding to different row addresses. The structure of the case where κ = 2 is also shown in FIG. 6. The data buses DBo and DBe are arranged in the column direction in one of two areas adjacent to the memory array 10 in the row direction as in the first embodiment. The inverse data bus / WDB is arranged along the column direction in a region opposite to the memory array 10 and the data buses DBo and DBe. "In each row block CB, the write row selection gate WCSGo & WCSGe is electrically connected between the inverse data bus / WDB and the corresponding bit line. The structure and operation of other parts and the embodiment 1 and its The modification example is the same, and the detailed description is not repeated. Therefore, when writing data, in each row block, κ row selection gates are used.

Page 28 578150 V. Description of the invention (25) The activation of the CSG response selection line CSL, between the -knowledge side of each M bit line and the K data bus is respectively at the electrical selection gates WCSGo and WCSGe; ie, _ ^ It is said that the activation of the secondary selection lines WCSLo and WCSLe becomes conductive. Leisurely ^ ^ m ^ ^ Therefore, according to the trip among the K bit lines, the other one selected by the remote selection result

. ^ „L. ^ System < The other, side and reverse data bus / WDB are electrically connected. The worst is to use this structure, especially y 丨 m ^ Only the structure of Example 2 is set, no current is set ^ With the wiring RL, the bit line use and embodiment of the selected row! And its skin shape example 1, a simple structure can supply the data write current ± iw. Also, as in λ embodiment 1, because for each row area Block CB, that is, the configuration of each complex (κ) memory cell row! One row selection line csl is sufficient, which can greatly reduce the number of signal wirings required for row selection. Embodiment 3 Referring to FIG. 7, the structure of Embodiment 3 The arrangement corresponding to each memory cell line is a bit line pair consisting of two complementary bit lines. In Figure 7, the representative table corresponds to the jth (j: natural number) memory cell line. The structure is the same as that corresponding to each memory cell row. The bit lines BL j and / BLj constituting the bit line pair BLPj use metal wiring layers M3 and M4 located on the upper side of the MTJ memory cell MC. The formed metal wiring is arranged at a predetermined position in the vertical direction to cross each other in the vertical direction. Lu Jiyi's body array 10 includes n memory cells (n: an integer of 2 or more), and m cells are arranged on the right and left sides of a predetermined area where bit lines BL and / BL intersect (m ! = integer represented by αη / 2) memory unit

2075-5330-PF (Nl); Ahddub.ptd Page 29 578150 V. Description of Invention (26) column. Bit lines BL and / BL are formed in the left area of the read character lines RWL and RWLm and the write character lines WWU to WWLm by wirings arranged on the metal wiring layers M4 and M3, respectively. Further, bit lines BL and / BL are formed in the areas to the right of the read character lines RWLm + 1 to RWLn and the write character lines WWLm + 1 to WWLn, which are respectively arranged on the metal wiring layers M3 and M4. It is connected in a predetermined area to the wiring corresponding to the bit line BL formed in each of the metal wiring layers M3 and M4. Similarly, the wiring corresponding to the bit line / BL formed in each of the metal wiring layers M 3 and M 4 is also connected in a predetermined area. One of the bit lines BL and / BL and the short distance between the MTJ memory cell, that is, the metal wiring layer M3 on the lower side, is connected to the MT J memory cell MC. The write row selection gate WCSG j connects the corresponding end of the bit line BLj and / BLj in response to the activation of the corresponding write row selection line WCSL j. In addition, a data bus pair DBP composed of complementary data buses DB and / DB is set. At the time of data writing, the voltages of the data buses db and / DB are respectively connected to the nodes Nw2 and Nwl of the data writing current supply unit 52 shown in FIG. 3. Therefore, the data bus DB and / DB are set to each of the power supply voltage Vcc and the ground voltage GND according to the level of the written data Dn. The row selection gate CSG j has a transistor switch connected between the other ends of the bit lines BLj and / BL j and the data bus DB and / DB, respectively. These transistor switches become conductive in response to the activation of the corresponding row selection line CSL]. By adopting this structure, the direction can be written according to the data written in the data D 丨 N ± Iw to the bit lines BL and / 6 [of the selected row, as a reciprocating current folded back by the write row selection gate WCSG j . In the left area, data is written using the current flowing on the bit line BL; in the right area, data is written using

2075-5330-PF (Nl); Ahddub.ptd ^ ^ page 30 578150 V. Description of the invention (27) ---: The current flowing on the bit line / BL performs data writing. Therefore, as in the case of the target example 1, the bit line direction of the selected row can be supplied in accordance with the data write level of the write data &, and the peripheral circuit will not be complicated. Also, because the reverse currents flow to the bit lines BL and / BL adjacent to each other in the up-and-down direction, a self-selection of the line / DT is allowed, and the effects of the sigma bit lines BL and / BL each act on the adjacent The magnetic noise of the MTJ memory cell & of the memory cell line weakens each other. Therefore, reducing the influence of magnetic noise can prevent data from being written by mistake and stabilize the operation. At the time of data reading, the bank WCSG becomes non-conducting and the gate side of each memory cell row is electrically separated from each other due to the write row selection gate. In addition, in the selection row, the row selection gate CSG becomes conductive, and the other ends of the corresponding bit lines BL and / BL are connected to the data bus dB and / db respectively. At the time of data reading, at least one of the data bus DB and / DB receives the supply of data writing current. In particular, in each memory cell row, a structure in which virtual memory cells (not shown in the figure) each having an intermediate resistance and which are selectively connected to complementary bit lines BL and / BL each bit line can be adopted. . That is, the resistance of each virtual memory cell is set to each of the memory cells having π 1 ”and“ 0 ”= the intermediate value of the two types of resistance. '、 If such a virtual memory cell is configured, each element line pair It is possible to read data with high gas tolerance according to the voltage comparison between the complementary bit lines BL and / BL for each unit. In addition, in the bit line configuration of Example 3, the bit lines are combined with each other to form a bit line.

2075-5330-PF (Nl); Ahddub.ptd Page 31 " " '------- 578150 V. Description of the invention (28) The bit lines BL and / BL of each bit line are connected The number of memory cells is set to be equal, which can correct the RC load imbalance between the bit lines BL and / BL forming the same bit line pair BLP. In addition, the bit lines BL & / Bl are intertwined to reduce interference noise between the two during data reading, and high-speed and high-precision data reading can be performed. Modification of Embodiment 3 The modification of Embodiment 3 shows a bit line arrangement in which the structures of Embodiment 2 and Embodiment 3 are combined. Referring to FIG. 8, in the structure of the modification of the third embodiment, compared with the structure of the third embodiment, the data buses DB 1 and DBr and the inverse data bus / WDB in which the replacement bit line pair BLP is arranged and The write row selection gate wcSGj instead of the write row selection gate WCSG1-j and WCSGr-j are different. The write row selection gate WCSG 1 — j is provided between the inverse data bus and one end side of the bit line BL j, and becomes conductive in response to the activation of the control signal% 1. The control signal SG1 is activated to a unitary level in the case where the memory cell is selected in the area to the left of the predetermined area where the bit lines BL and / 8 [cross at the time of data writing. The write row selection gate WCSGr — j is provided between the inverse data bus / WDB and one end side of the bit line BL j, and becomes conductive in response to the activation of the control signal SGr. When the control signal SGr is written, the area to the right of the predetermined area where the bit line BL A / BL intersects includes the case where the memory cell is selected, and is activated to the unit level. At the time of body reading ', the inverse data bus / WDB and the bit lines BL, / BL are electrically separated from each memory cell row. In addition, by

2075-5330-PF (Nl); Ahddub.ptd 578150

The data of at least one of the supplied data bus DB1 and DBr is written into Lei Leng ^ y electric ring, and the same data is read out as in Example 3. By adopting this structure, when data is written, in the area where the selection row does not include the selection memory cell, the data writing current does not flow to the metal wiring close to the MTJ Case 3 body cell. Therefore, in the selected row, data erroneous writing in a non-memory cell can be suppressed. In addition, since the data writing current path on the bit line pair of the selected row is shorter than the structure of the third embodiment, the resistance can be reduced, the data writing operation can be speeded up, and power consumption can be reduced. _ In addition, in the embodiment 3 and its modification, the structure in which the bit lines BL and / BL intersect in the vertical direction is given as an example in a predetermined vertical region. However, a structure in which a plurality of intersections are used is also used. . Embodiment 4 Referring to FIG. 9, the memory array 10 is divided into a plurality of memory blocks along a column direction. In FIG. 9, the memory array 1 is divided into two memory blocks Mba and MBb, for example. In the memory block Mba, read word lines RWLal, RWLa2,... And write words are arranged corresponding to the memory cell columns. Yuan lines wWLal, WWLa2, ... Similarly, in the memory block Mbb, the read character lines RWLbl, RWLb2, ... and the write character lines WWLbl, WWLb2, and corresponding to the memory cell column are respectively arranged, that is, 'read is independently set in the memory blocks Mba and MBb. A character line RWL and a write character line WWL. In addition, the corresponding bit line BL ° corresponding to each memory cell row in the memory blocks MBa and MBb is arranged in each memory block.

2075-5330-PF (Nl); Ahddub.ptd Page 33 578150 V. Description of the invention (30) The data bus DBa corresponding to the memory block MBa corresponds to one end side of the bit line BL (the memory block MBa side). Are arranged along the column direction in a region adjacent to the memory array 10. The data bus DBb corresponding to the memory block MBb and the other end side (the memory block MBb side) of the bit line BL are arranged along the column direction in a region adjacent to the memory array 10. The inverse data bus / WDB is common to the memory blocks MBa and MBb, for example, and is arranged along the column direction at the boundary between the memory blocks MBa and MBb. In each memory cell row, the bit line BL is connected to the node Na corresponding to one end and the node Nb corresponding to the other end via a drive switch and a data bus DB a and DB b, respectively. Data bus / WDB connection. For example, corresponding to the bit line, a driving switch is provided between the node N a (1) and the node N b (1) and the data bus DBa and DBb respectively corresponding to one of the known side and the other end side ( : 1) (^ 1 and CDGM, a drive switch WDG1 is provided between the intermediate node Nm (l) and the inverse data bus / WDB. In addition, in the following, the condition of a node on a specific bit line is expressed, such as (l), Nb (l), and Nm (1) are added with parenthesized numbers. In the case of unspecified comprehensive expression bit lines, they are only expressed as wNa, Nb, and Nm. The drive switches CDGal and CDGbl respond to each line. The control gates CGal and CGbl are opened and closed. The drive switch 〇G1 is opened and closed in response to the activation of the corresponding write row selection line WCSL1. A write row selection line WCSL is provided in each memory cell row. The selected row is activated to the H level. The deactivation control gate CGa 1 selects the corresponding first memory cell row when data is written, and when the selected memory cell belongs to the memory block MBa

578150, the corresponding drive switch CDGal is turned on. CGal selects the corresponding first memory cell row in the data green day-to-day operation control unit ^ Brother Makes the corresponding drive switch CDGal conductive. That is, the row control gate CGal has an AND logic, and the corresponding write row selection, the line WCSL1 and the voltage selection level of the ㈣selection signal SBa are logically different from each other. Result of 0R logic operation between the voltage levels of corresponding row selection lines RCSL1. 〇The output of the R gate is driven by an N-channel M0S transistor. The gate is only 0. A read line selection line rib 设置 is provided in each memory cell line, and is activated at the selected level when the data is read. The block selection signal is activated to the level when the selected memory unit belongs to the memory block MBa. In the case where the selected memory cell belongs to the memory block MBb, the block selection signal SBb of the same setting is activated to a high level. The row control gate C G b 1 selects the corresponding first memory cell row when data is written, and when the selected memory cell belongs to the memory block MBb, the corresponding drive switch CDGbl is turned on. When data is read, regardless of the row selection result, the row control gate CGbl makes the corresponding drive switch CDGbl non-conductive. That is, the 'row control gate C G b 1 has an A N D gate, and outputs the result of an AND logic operation between the corresponding row selection line WCSL1 and the voltage level of the block selection signal SBb. The output of the AND gate is the gate of the drive switch CDGbl composed of n-channel M0S transistors. At the time of data writing, the data buses DBa, DBb and reverse data bus

2075-5330-PF (Nl); Ahddub.ptd p.35 578150 V. Description of the invention (32) Each row / WDB and the data bus DB0, DBe and reverse data bus / WDB in Example 1 Settings. Specifically, with the same structure as the data writing circuit 51 of the first embodiment, the switch circuit 53 may be controlled in accordance with the block selection signals SBa and SBb. By adopting this structure, for example, when data is written, when the first memory cell row is selected, the drive switch WDG 1 is turned on, and in addition, one of the 'drive switches CDGal and CDGbl belongs to the memory according to the selected memory cell. Which of the blocks MBa and MBb is turned on. That is, when the selected memory cell belongs to the memory block MBa, the drive switches CDGal and WDG1 located on both sides of the selected memory cell are turned on, respectively, and the nodes Na (1) and Nm (1) on the bit line BL1 are respectively turned on. Connect with data bus DBa and reverse data bus / WDB. Therefore, the nodes "(1) and

Nm (1) is set to each of the power supply voltage vcc and the ground voltage gnd according to the data DIN. Therefore, in the bit line BL1 of the selection row, the direction of the data write current ± I w according to the data DIN written can flow in the direction corresponding to the nodes N a (1) to N m ( 1) between. In addition, since the drive switch CDGbl is not turned on, the bit writing line BLi in the selection row will not flow the data writing current between the nodes Nb (丨) to Nm (丨) that do not correspond to the selection memory cell. Conversely, when the selected memory cell belongs to the memory block MBb, the drive switches MCDGbl and 0 (; 1 become conductive 'and the drive switch CDGal become non-conductive respectively located on both sides of the selected memory cell. Therefore, the selection is performed. Bit 7L line BL 1 enables the direction to be written in accordance with the data written in data D 丨 N

2075-5330-PF (Nl); Ahddub.ptd p. 36 578150

Flow ± Iw flows between the nodes Nb (l) and Nm (l) corresponding to the memory block including the selected memory unit. On the bit line BL1 of the selection row, the data write current does not flow between the nodes Na (l) and Nm (l) which do not correspond to the selection memory cell. In FIG. 9, drive switches CDGal to CDGa4, CDGbl to CDGb4, WDG1 to WDG4, and row control gates CGal are representatively shown from the first to the fourth memory cell rows and the respective configurations corresponding to these memory cell rows. ~ CGa4, CGb, CGb4, read row selection lines RCSLi ~ RCSU, and write row selection lines WCSU ~ WCSL4. These drive switches, control gates, and row selection lines are similarly arranged in other memory cell rows. In addition, in each memory cell line, the operation at the time of data writing is performed in the same manner as in the first memory cell line. ^ As shown in the above description, in this way, the supply direction according to the write data will not complicate the peripheral circuits. In addition, the path between the bit corresponding to the selection line and the portion corresponding to the selection memory cell is shortened to reduce the resistance to perform low-voltage operation, but the resistance also flows during low-voltage operation. In addition, the data writing current path becomes faster. The structure of the fourth embodiment is consistent with the data write current of the D I N level in the first embodiment. The line ′ allows the data write current to flow because the data write current flows only in the interval of minutes. In recent years, the reduction in power consumption, such as lowering the power consumption of the data writing current path, can also facilitate the writing of data due to the reduction of power consumption. In addition, in the selection of rows, the sum of The non-selected memory area also prevents the write current from flowing to the interval corresponding to the bit line BL block.

2075-5330-PF (Nl); Ahddub.ptd page 37 578150 V. Description of the invention (34) The data of the memory unit of the selected memory block is written incorrectly. In addition, in the structure of the fourth embodiment, a plurality of intermediate nodes are provided on each element line, and the data can also be written in a more subdivided control section in which the current flows. In this case, it is necessary for each element line BL to interact with one of the switches and data buses and inverse data buses of the plurality of drive switches provided corresponding to the nodes on one side, the plurality of intermediate nodes, and the nodes on the other side. Corresponding. Modification 1 of Embodiment 4 Referring to FIG. 10, in Modification 1 of Embodiment 4, a memory cell array is configured with a folded-back bit line. The memory array 10 is divided into a plurality of memory blocks along the column direction as in the fourth embodiment. In FIG. 10, the memory array 10 is divided into a plurality of memory blocks along the column direction. In FIG. 10, the memory array 10 is also divided into two memory blocks Mba and MBb. In each of the memory blocks MBa and MBb, a read character line RWL and a write character line WWL are provided in each memory cell row. According to the folded bit line structure, a bit line pair BLP composed of complementary bit lines BL and / BL is arranged corresponding to each memory cell row. The complementary bit lines BL and / BL are commonly arranged in the $ Kiyi blocks μ B a and M B b. For example, a bit line pair BLP1 is formed by using bit lines BL1 and / BL1 corresponding to the first memory cell row. The MTJ memory cell MC is alternately connected to one of the bit lines BL and / BL every other column. For example, if the MTJ memory cell belonging to the first memory cell row is described, the MTJ memory cell in the first column is connected to the bit line BU, and the MTJ memory cell in the second column is connected to the bit line / BL1. Following one

2075-5330-PF (Nl); Ahddub.ptd p.38 578150 V. Description of the invention (35) " Surface ------- In the same way, MTJ memory cells are connected in odd columns and bit line BL1, Connect the bit line / B L1 in the even columns. Further, in a region adjacent to the memory array 10, a data bus DBpa & DBpb is provided corresponding to each of the memory blocks MBa and MBb. The data buses are arranged along the column direction in the area on the MBa side of the memory area. & Including complementary data buses DBa and / DBa °, the data bus DBPb is arranged along the column direction in the area on the side of the memory block MBb, including the complementary data buses DBb and / DBb. The structure of the modification of the fourth embodiment is the same as that of the drive switch, the control gate, and the row selection line in each memory cell. Therefore, the structure of the first memory unit will be described in a representative manner below. The drive switch CDGal has a transistor switch, which is respectively connected between the respective nodes Na (1) and / ^ (丨) and the data buses DBa and / DBa corresponding to one end of the bit lines BL1 and / BL1. These transistor switches are opened and closed in response to the output of the row control gate CGal having the same structure as that shown in FIG. The drive switch CDGbl has a transistor switch, which is respectively connected between the respective nodes Nb (1) & / Nb (1) and the data buses DBb and / DBb corresponding to the other ends of the bit lines BL1 and / BL1. These transistor switches are opened and closed in response to the output of the row control gate CGb 1 having the same structure as that of FIG. 9. The drive switch WDG1 is connected between the intermediate node Nm (丨) of the bit το line BL1 and the intermediate node Nm (1) of the bit line / bu corresponding to the boundary portion of the memory blocks MBa and MBb. As in the structure of FIG. 9, the drive switch WDG 丨 is opened and closed in response to the corresponding write row selection line WCSL1. Data buses DBa and / DBa constituting the data bus DBPa

2075-5330-PF (Nl); Ahddub.ptd Page 39 578150 V. Description of the invention (36) The voltage, including the case where the memory unit is selected in the memory block MBa, respectively and the data write current shown in Figure 3 The nodes Nw2 and Nw1 of the supply unit 52 are connected. Therefore, the data buses DBa and / DBa are set to one of the power supply voltage Vcc and the ground voltage GND in accordance with the level at which the data d I N is written. The data buses dbb and / DBb constituting the same data bus DBP b include the case of selecting a memory unit in the memory block MBb, and are set to the power supply voltage vc and the ground voltage gn according to the level of the data DIN. Each of D. Therefore, when the first memory cell row is selected and the selected memory cell belongs to the memory block MBa, the drive switches CDGal and WDG1 located on both sides of the selected memory cell become conductive, and are written in accordance with the data written in DIN The current ± Iw flows through the nodes on the bit line pair BLpi of the selected row, and the paths Na (l) ~ Nm (l) ~ / Nm (l) ~ / Na (1). In addition, since the drive switch CDGbl becomes non-conducting, the data write current does not flow to the node corresponding to the selected memory cell on the bit line pair BLp of the selected row. The interval from Nb (l) to Nm (l) and the node / Nb (1) to / Nm (1) i interval. On the other hand, when the Tian select memory unit belongs to the memory block MBb, the drive switches CD 讣 and Yang 61 on both sides of the select memory unit become conductive: and the drive switch CDGal becomes non-conductive. Therefore, at the position of the selected lamp, the line pair BLP1 can make the direction according to the data written in the written data ± I w only flows to the path 1 of the harmony sentence 4 & in the memory block of the 4 two-body unit Corresponding to Tan Ding 70 line pair BLP1, the data write current will not flow to the interval that does not correspond to the selected memory unit. By using the seed structure, the structure of the modification of the fourth embodiment, the

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In the case where the memory array mG uses a folded-back bit line structure, the same data is written as in the fourth embodiment. jSubscribe In addition, in each memory cell row, a structure in which a virtual memory cell (not shown in the figure) having a resistance can be selectively connected to each of the element lines BL and / BL can be used. That is, the resistance of the memory unit of 0 is set to the intermediate value of the two kinds of resistances of the memory "i" and "quote." If the virtual memory unit is equipped with this virtual memory unit, The element line is read according to the data of the high voltage comparison between the complementary bit lines BL and / BL. M 14 Modification 2 of Embodiment 4 Referring to FIG. 11, in the structure of Modification 2 of Embodiment 4, Compared with the structure of Embodiment 4 shown in FIG. 9, the bit lines driving nBDVa, BDVb, and BDVm are different in the bit lines instead of driving switches CDGa, CDGb, and WDG in a configuration corresponding to each bit line. For example, for bit line BL1 , The setting bit line drivers corresponding to the nodes Na (l) and Nb (l) corresponding to one end side and the other end side thereof respectively write BDVal and BDVbl, and the setting bit line driver corresponding to the intermediate node _ (1) The BDVml 0-bit line driver BDVal has driver transistors DTHa ADTLa, which are each connected between the power supply voltage Vcc and the ground voltage GND and the node Na (l). The driver transistors DTHa and DTLa are opened and closed in response to the write control signals mal and WLal, respectively. .Same, bit line driver-BDVM has driver The actuator transistors DTHb and DTLb are respectively connected to the power supply voltage Vcc and the ground voltage GND and

2075-5330-PF (Nl); Ahddub.ptd

578150 V. Description of the invention (38) Between nodes Nb (l). The driver transistors DTHb & DTLb are opened and closed in response to the write control signals / WHbl and WLbl, respectively. In addition, the bit line driver 1 has driver transistors DTHm and DTLm 'which are connected between the power supply voltage Vcc and the ground voltage GND and the node Na (1), respectively. The driver transistors "heart and" are opened and closed in response to the write control signals Wml and Wm # 1, respectively. The bit line drivers BDVa, BDVb, and BDVm having the same structure are arranged in each memory cell row, but the writing control signals of the driver transistor group are independently set in each memory cell row. In this modified example, the data writing circuit (not shown in the figure) generates a writing control signal according to the data writing level, the memory block selection result, and the row selection result. In the selection line, in the case where the selected memory cell belongs to the memory block MBa, the bit το line drivers BDVa and BDVm drive the corresponding node Na and drive each of the written data according to the power supply voltage Vcc and the ground voltage GND. The bit 7G line driver BDVb does not drive the node Nb to either the power supply voltage Vcc or the ground voltage GND. On the other hand, in the case where the delta memory cell is selected as the memory block MBb, the bit driver BDVb and BDVm drive the corresponding node Nb ANm to each of the power supply voltage Vcc and the ground voltage GND according to the written data. However, the bit line driver BDVa does not drive the node Na to either the power supply voltage Vcc: and the ground GND. As a result, as with the structure shown in FIG. 9, the bit line fi in the selection row is OK, and the direction of the writing current according to the data written in the data only flows to the part corresponding to the selected L body unit (node na ~ n ^ Or between nodes nb ~ N m). Therefore, it is possible to reduce the resistance of the data write current path, and to operate at low voltage

578150

In addition, the non-selective memory for data writing can also make it easy to supply the required data writing current and speed up the operation. In addition, erroneous writing of data to a memory cell in a selected row block can be suppressed. When the data is written, the non-selected rows of the line I, D v g, BMb, and BDVra drive the corresponding nodes Na, Nb, and Nm to = = GND_ to prevent unwanted current from flowing. In addition, except when writing data, the bit lines drive HBDVa, BDVb, and BDVm, and the corresponding nodes Na, Nb, and Nm are not driven to the power supply voltage ycc and the ground voltage (jnd. In addition, the read data bus RDB1, RDB2 and the intermediate node. Correspondingly arranged at the boundary portion of the memory blocks MBa and MBb. The data bus RDB1, RDB2 for reading and the bit line BL intersect and are arranged along the column direction. The settings corresponding to the memory cell rows It is used to selectively connect the read-out selection gates RDSG1 to RDSG4 between the data buses RDB1, RDB2 and the bit line BL. The read-out selection gates rdSGI to RDSG4, ... each respond to the read row selection. The lines RCSL1 to RCSL4, ... are activated to become conductive. Each readout selection gate is connected between the corresponding intermediate node N m and the readout data bus RDB1 in the odd rows, and is connected to the corresponding intermediate node Nm in the even rows. When the data is read from the read data bus RDB2, in response to the activation of the read word line RWL in the selection row, the bit line in the selection row is connected via the selection memory cell and the ground voltage GND. By using resources The readout circuit 55 reads out the data to make an electric current to the readout data bus RDB1, RDB2, detected readout data busbars RDB1, RDB2 of current and voltage, performs selection information from the memory unit to read out.

2075-5330-PF (Nl); Ahddub.ptd Page 43 578150 V. Description of the invention (40) At this time, it is set as the middle point of the data line RDB1, RDB2 for reading and the bit line of the selection line The structure of the N m connection shortens the bit line length on the read current path and reduces the resistance of the read current path. Therefore, the data readout speed and the data readout margin can be improved. In addition, in the folded bit line structure shown in FIG. 10, the configuration of the bit line drivers BDVa, BDVb, and BDVm that drive the switches C D G a, C D G b, and W D G may be replaced. Also in this structure, the data bus for readout and the selector gate for readout corresponding to the intermediate node Nm can be ordered as in FIG. 11. Embodiment 5 Referring to FIG. 12, in the structure of Embodiment 5, the memory array is divided into a plurality of row blocks along the row direction. In FIG. 12, the memory array 10 is divided into two row blocks CBa and CBb. In the row block CBa, the arrangement bit lines BLal,... Corresponding to the memory cell rows, respectively. Similarly, in the row block CBb, the arrangement bit lines BLbl,... Corresponding to the memory cell row are respectively. That is, in the row block CBa & CBb, the bit line BL is independently provided. Further, in the row blocks CBa and CBb corresponding to each memory cell column, a read character line RWL and a write character line WWL are arranged together. Each writing word line WWL is connected to a ground voltage G N D at an intermediate node N m corresponding to a boundary position of the row blocks CBa and CBb. For example, the writing word line WWL1 corresponding to the first memory cell row is connected at the intermediate node Nm (1) to the voltage GND, and the writing word line WWL2 corresponding to the second memory cell row is at the intermediate node. Nm (2) is connected to ground voltage gnd.

578150 V. Description of the invention (41) Fig. 12 represents the structure of the character word line WWL used to drive the character line driver 30. The word line driver 30 includes a current supply wiring SPL and a current supply circuit 31 provided in each row block. 2 shows current supply wirings SpLa * spLb and current supply circuits 31b corresponding to the row blocks CBa and CBb, respectively. Referring to FIG. 13, the current supply circuit 31a has a p-channel type MOS transistor 3 3a. The voltage vcc and current supply wiring are electrically connected; the P-channel type M0S transistor 33b is electrically connected between the power supply voltage vcc and the node Npl; the N-channel type M0S transistor 34 is connected to the node Npl and ground The voltage GND is electrically connected. The gates of the transistors 33a and 33b are connected to the node NM. A control voltage vrp is input to the gate of the transistor 34. Therefore, a current mirror circuit composed of transistors 33 & and 33b is used to supply a current supply line SPLa set to the power supply voltage Vcc in accordance with the control current vrp at a fixed current. The current supply wiring 讣 "also has the same structure as the current supply wiring SPLa. Referring again to FIG. 12, the character line driver 30 also has a drive switch ⑽. The node Na and the current are provided on one end side of the writing word line WWL. The supply wiring SPLa and the drive switch RDGb are provided between the node Nb on the other end side of the writing word line and the current supply wiring SPLb. In FIG. 12, the first and second memory cell columns are representative Indicates that the drive switches RDGal, RDGa2, RDGbl, RDGb2 and drive switches RDGa corresponding to the nodes Na (丨), Na (2), Nb (l), and Nb (2) are respectively selected in the corresponding memory cell column and selected.

578150 Description of the invention (42) The case where the memory unit belongs to the row block CBa becomes conductive. Similarly, the drive switch RDGb becomes conductive when the corresponding memory cell row is selected and the selected memory cell belongs to the row block CBb. For example, when the gate of the driving switch is "at > writing", the control signal / WRDla activated to the L level is input when the first memory cell column is selected and the selected memory cell belongs to the row block CBa. Similarly, when the gate of the drive switch RDGM is written, when the first memory cell column is selected and the selected memory cell belongs to the row block CBb, a control signal / WRDlb activated to a level of 1 is input. The column decoder 20 is used to generate control operations / WRDla and / WRDlb according to the row selection result. … Generate control signal RRd. Memory cell row Corresponding control signal RRd The response of the control signal RRd is 30. In the selection row, the switches RDGa and RDGa are driven according to the selection, so that the node body unit on the character word line in the predetermined direction can correspond to one of them. In the structure of Example 5, when only the path to the memory is selected and the path for writing the current to the memory is selected, the data required for low power is written to the column decoder 20. When the data is read from each memory cell, the corresponding one is selected. The control signal RRd is activated to the threshold level. The voltage of each read word line RWL is controlled in accordance with. For example: The activated word line RWL1 is activated to a level (by using this structure, the word line drives the position of the selected memory cell and the intermediate node Nm to one of RDGb to be selectively turned on. The result is written The selective current of the input current Ip is selected between the columns of Na ~ Nm and the sum of nodes Nb ~ Nm. As shown in the above description, if the writing word line of the implementation column is used, data can be written into the current unit correspondingly. Part of the interval. Therefore, the data is blocked, and it is easy to supply during low voltage operation.

578150 V. Description of the invention (43) " ---->, and can speed up the data writing operation. In addition, the data of the memory unit of the non-selected row block of the selected row is also used in the Z 2 system for the modification 1 of the fifth embodiment. Referring to FIG. 14, the structure of the modified example of the fifth embodiment is different from the structure of the fifth embodiment in that the word line driver further includes a drive switch RGG provided corresponding to the word line WWL shown in I2. . Drive on, and connect RGG between intermediate node Nm and ground voltage GND. For example, a driving switch RGG1 which is arranged between the intermediate node ^ and the ground voltage GND corresponding to the & unidirectional line WWL1 is electrically connected. The θ drive switch RGG is composed of, for example, an N-channel type MOS transistor, and is activated as a control signal WRd of the unit ^ when a corresponding memory cell row is selected at its idle input. For example, when the gate input of the drive switch RGG is selected as the first memory cell row, the control signal WRdl is activated. Therefore, in the selection column, the corresponding intermediate node N m and the ground voltage G N D are connected by turning on the driving switch RGG. The structure of the other parts of the word line driver 30 is the same as that of the fifth embodiment, and detailed description will not be repeated. By adopting such a structure, compared with the structure of the fifth embodiment, the writing word line WWL in a non-selected column reduces the possibility of an undesired data write current flowing, and further suppresses data miswriting. occur. Modification 2 of Embodiment 5 In Modification 2 of Embodiment 5, a high-efficiency arrangement of drive switches constituting a word line driver will be described. FIG. 15 is a diagram illustrating the configuration of a driving switch according to the second modification of the fifth embodiment.

2075-5330-PF (Nl); Ahddub.ptd Page 47 578150 V. Description of the invention (44) Read the picture. L 'illustrates the structure of dividing the memory array 10 into four row blocks cbi, 4 along the row direction. In each memory cell column, it is possible; = blocks CB and CB4 are common to set the character-lined holes for writing. Ten orders. As shown in Embodiment 5 and its modification, the nodes corresponding to one end side and the other end side of each of the writing lines WWL, the handsome, and the intermediate node Nm corresponding to the boundary portion of the row block. The switch RDG or RGG corresponding to each node. The on drive switch RDG is provided to connect the corresponding node to the power supply voltage Vcc. The drive switch RGG is provided to connect the corresponding node to the ground voltage ⑽. In each memory cell column, alternately configure

RDG and RGG. J For example, in the structural example shown in FIG. 15, for the writing character line WWL j in the column], a driving switch RDG is provided for the node Na (j) corresponding to one end side thereof, and for a row block CB1 And the intermediate node Nm 1 2 (j) of the boundary portion of CB2 is configured to drive the switch rgg. From here on, the respective intermediate node cores 23 (j) corresponding to the boundary portions of the row blocks CB2 and CB3, the intermediate node cores 34 (j) corresponding to the boundary portions of the row blocks ^ B3 and CB4, and the writing equivalent words The interactive configuration corresponding to the node Nb (j) on the other end of the element line WWLa drives the switches 'RDG', RGG, and RDG °. In the direction, M drive switches are arranged in sequence. One of the drive switches RDG and RGG constitutes an odd-numbered drive switch, and the other of the drive switches RDG and RGG constitutes an even-numbered drive switch.

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When data is written, in the selection column, the corresponding parts of the memory and the memory unit are selected separately for writing. The writing switches RDG and RGG become conductive. Because of this point, the corresponding point is h and the example 5 and its 7 variants are opened. # 'On the writing character line of the selection column, electricity can be made to correspond to the row block to which the selection memory cell belongs. section. The worse one adopts this structure, and the writing current of the writing character data in the selection column flows only to a part of the interval corresponding to the selection memory cell. ^ Column 'inhibits random writes to memory cells in non-selected memory blocks. In addition, since the path of the data writing current is shortened, the resistance can be reduced, the data writer operation can be speeded up, and the power consumption A can be reduced. In addition, it is easy to supply a sufficient data write current during low voltage operation. In addition, since the driving switches RDG or RGG can be shared between adjacent blocks, the number of driving switches can be reduced, and the circuit area can be reduced. This = 'For the writing character line WWL j + 丨 in the (j + 1) column, the same as the node Na (j + Ι), the intermediate node Nmi 2 (j + l), Nm23 (j + Ι) , Nm34 (j Η) and node Nb (j +1) corresponding to the driving switches RGG, RDG, RGG, RDG and RGG are set in turn. That is, the arrangement of replacement of the drive switch RDG corresponding to the power supply voltage Vcc and the drive switch rgG corresponding to the ground voltage GND alternately every adjacent column. In other words, in each memory cell row, if the odd-numbered drive switch is focused on, the types of drive switches arranged in the odd-numbered row and the even-numbered row are different. For example, in the case of an odd-numbered row, each of the odd-numbered drive switches is a drive switch RDG corresponding to the power supply voltage Vcc, and in an even-numbered row, each of the odd-numbered drive switches is freely formed with a drive switch RGG corresponding to the ground voltage GND.

2075-5330-PF (N1); Ahddub.ptd Page 49 578150 V. Description of the invention (46) One-Therefore, 'relaxing the configuration spacing of these drive switches can be configured more efficiently. Make the area smaller. In addition, as for the drive switch RGG corresponding to the ground voltage gnd, the configuration is omitted as in FIG. 1 1, and a structure in which the corresponding intermediate node core and the ground voltage GND are directly connected may be adopted. Example 6 In Example 6 ', the high efficiency of the bit line driver shown in FIG. 11 will be described. Referring to FIG. 16, in the structure of the embodiment 6, the bit line 乩 is divided into a complex array of bars (integers of 2 or more). In each group, the other end side of the X bit lines is electrically connected via the short-circuit node Ns. Connected. The structure of the case where X = 2 is shown in FIG. 16 as an example. ^ Each bit line BL is provided with a bit line driver for driving a voltage corresponding to node Na at one end side. For example, for bit line BL1, a bit line driver BDVai corresponding to node Na (l) is provided. And the bit line driver -BDVb for driving the voltage of the short-circuit node Ns is arranged on the other end side of each bit line BL. For example, for the bit lines Bu and BL2, the settings corresponding to the short-circuit node Ns (1) are common. The bit line driver BDVbl. The structure and operation factors of the bit line driver and the driver are the same as those shown in Figure 丄), and detailed descriptions are not repeated. When writing data, the bit line driver BDVa corresponding to the selection row and the bit line driver BDVb corresponding to the selection group respond to the writing control signal from the data writing circuit (not shown in the figure), The center drive is one of the power supply voltage Vcc and the ground voltage GND according to the written data. As a result, the direction of the writing current can be selected according to the data written in the data.

2075-5330-PF (Nl); Ahddub.ptd Page 50 578150 V. Description of the invention (47) Bit line BL. The readout data buses RDB1 and RDB2 are arranged correspondingly along the direction (column direction) crossing the bit line BL and the other end side of the bit line BL. In addition, respective settings corresponding to the blocks are used to selectively connect the read-out selection gates rdSGI, RDSG2,... Between the data buses RDB1, RDB2 and the short-circuit node Ns. The read selection gates RDSG1, RDSG2, ... are arranged outside the bit line driver BDVb. This is the representative example of the odd-numbered read-out selection gate. The read-out selection request RDSG1 responds to the activation of the read-row selection line RCSL1 or RCSL2, and connects the corresponding short-circuit node Ns (l) with the read data bus RDB1. Electrically connected. The RDSG2, which is a representative example of the even-numbered read-out selection gate, responds to the activation of the read-row selection line RCSL3 or RCSL4, and connects the corresponding short-circuit node Ns (2) with the read-data bus RDB2. Electrically connected. When the data is read out, in response to the activation of the read word line RWL of the selected row ', the bit line of the selected row is connected to the ground voltage GND via the selection memory cell. In this state, by using the data readout circuit 55, the data readout current is passed to the readout data buses RDB1 and RDB2, and the current and voltage of the readout data buses RDB1 and RDB2 are detected, and the self-selection memory is executed. The information of the unit is read out. Therefore, in the structure of Embodiment 6, since the bit line driver BDVb is shared among the X bit lines BL in each group, the arrangement pitch of the bit line drivers Bj) Vb can be made X times. As a result, the selection gates RDS (n, RDSG2,...) Can be arranged with high efficiency. As a result, the chip area can be reduced.

2075-5330-PF (Nl); Ahddub.ptd Page 51 578150 V. Description of the invention (48) Modification of embodiment 6 Refer to FIG. 17 'The structure of the modification of embodiment 6 and FIG. 16 Compared with this structure, the read selection gates RDSG1, RDSG2, ... are provided on the inner side of the bit line driver BDVb. The structural factors of other parts are the same as those of Fig. 16-detailed description will not be repeated. By disposing the readout selection gate inside the bit line driver ', the bit line length in the read current path can be shortened relatively, so that the resistance of the bit line portion can be reduced. Therefore, the data readout speed and the data readout margin can be improved. In other words, if the readout selection gate is placed outside the bit line driver as shown in Fig. 6 and the bit line length of the read current path is relatively shortened, the resistance of the path can be reduced. Therefore, the data readout speed and the data readout margin can be improved. Alternatively, as shown in the structure shown in FIG. 18, the data bus RDB1, RDB2, and the read selection gates RDSG1, RDSG2, ... may be arranged at a position corresponding to the middle point of the bit line BL. Embodiment 7 In Embodiment 7, a structure in which only a portion of data corresponding to a selected memory cell on a bit line BL can be supplied with a write current after reducing the number of bit line driver configurations is described. Referring to FIG. 19, in the structure of the embodiment 7, the bit line BL is divided into two complex arrays each, and in each group, the middle point (ie, the intermediate node Nm) corresponding to the two bit lines is electrically connected. connection. In FIG. 19, two adjacent bit lines are used to form each group. Each element line BL is provided to drive the node Na corresponding to one end side.

2075-5330-PF (Nl); Ahddub.ptd Page 52 578150 V. Description of the invention (49) Bit line driver BDVa for voltage and r η vh-for driving the voltage equivalent to the node N b on the other side Λώ βγ- ^ The structure and moving of BDVa and BDVb as H-line driver are not the same as those shown in Figure 1, and detailed description is not repeated. For the bit line BL1, Greenbrew sets the bit corresponding to Na, and points Na⑴. In addition, the intermediate nodes Nm⑴ and Nm (2) are selected when the electrical unit i is a person who belongs to the memory block MBa. That is, the write control letter k from the data writing circuit (not shown in the figure) and the two bit line drivers BDVa corresponding to the selection block drive the corresponding nodes Na to the power supply voltage Vcc and the ground voltage gnd respectively. Write

Hi each: Fang. In addition, the two bit line drivers corresponding to the selected block do not drive the corresponding node Nb to the power supply voltage Vcc and the ground GN]). ^ In the case where the selected memory cell belongs to the memory block MBb, the two bit line drivers corresponding to the selected block drive the corresponding node ribs 2 to the power supply voltage Vcc and the ground voltage G0 in accordance with the write The parties entering the data " and the two bit line drivers BDVa corresponding to the selection block do not drive the corresponding node Na to either of the power supply voltage Vcc and the ground voltage gnd 0, the result is not a configuration corresponding to the intermediate node The bit line driver has the same structure as the figure f Γ. On the bit line of the selection line, the direction of the writing data can be written according to the data written in the shell material. The current flows only to the point corresponding to the selected memory cell (between nodes Na ~ Nm). Or between nodes Nb ~ Nm). Therefore, it is possible to reduce the resistance of the data input current path, and also make it easy to supply the voltage during low-voltage operation.

578150

Z ′ is a non-selection M when writing materials, in order to prevent unwanted electricity ^: Bit line driver BDVa, BDVb will drive the corresponding nodes Na, Nb, ground voltage GND. In addition, at the time of data writing, each element line driver BDVa, BDVb does not drive the corresponding nodes Na, Nb to either the power supply voltage Vcc or the ground voltage GND. The readout data buses RDB1 and RDB2 are arranged correspondingly along the direction (column direction) crossing the bit line BL and the other end side of the bit line BL. In addition, the corresponding settings of each block are used to selectively connect the read data buses RDB1 and RDB2 to corresponding read bit selection gates RDSG1, RDSG2,... The read-out selection gate RDSG1, which is a representative example of the odd-numbered read-out selection gate, responds to the activation of the read-row selection line RCSU * RCSL2, and converts one of the corresponding bit lines (BL2) and the read data bus RDB1. Connected electrically. This is a representative example of the even-numbered read-out selection gate. The master-out selection gate RDSG2 responds to the read row selection line RCSL3 or the activation of the daughter-in-law. The RDB2 is electrically connected to each other. Therefore, by using the data readout circuit 55, the readout current is passed to the readout bus RDB1, RDB2, and the current of the readout data bus ⑽ ..., RDB2 current is detected. Voltage, read data from the selected memory cell. For a modification of the seventh embodiment, refer to FIG. 20 ′, the structure of the modification of the seventh embodiment, and FIG. 9

2075-5330-PF (Nl); Ahddub.ptd Page 54 578150 V. Compared with the structure of (51) of the invention, the readout data bus RDB1, RDB2 configuration corresponding to the intermediate node Nm of the bit line BL It differs in the center part of the bit line BL. The structural factors of other parts are the same as those in Fig. 19, and detailed descriptions are not repeated. By adopting this structure, compared with the structure shown in FIG. 19, the bit line length in the read current path can be shortened to reduce the resistance of the bit line portion. Therefore, in addition to the effect of the structure of Embodiment 7, the data reading speed and the data reading margin can be improved.

2075-5330-PF (Nl); Ahddub.ptd Page 55 578150 Brief Description of Drawings Figure 1 is a schematic block diagram showing the overall structure of a MARA module according to an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating the structure of the memory array of Embodiment 1. FIG. Fig. 3 is a structural diagram for explaining the arrangement of the current feedback wiring shown in Fig. 2. FIG. 4 is a circuit diagram showing the structure of the data writing circuit shown in FIG. 2. FIG. Fig. 5 is a circuit diagram illustrating the structure of a memory array according to a modification of the first embodiment. FIG. 6 is a circuit diagram showing a structure of a memory array of the second embodiment.

FIG. 7 is a conceptual diagram illustrating the arrangement of bit lines in Embodiment 3. FIG. Fig. 8 is a conceptual diagram showing the arrangement of bit lines in a modification of the third embodiment. FIG. 9 is a circuit diagram showing a structure of a memory array of Embodiment 4. FIG. Fig. 10 is a circuit diagram showing a structure of a memory array according to a first modification of the fourth embodiment. Fig. 11 is a circuit diagram showing a structure of a memory array according to a second modification of the fourth embodiment.

Fig. 12 is a circuit diagram illustrating the supply of a data write current to the write word line of the fifth embodiment. Fig. 13 is a circuit diagram showing the structure of the current supply circuit shown in Fig. 2. Fig. 14 is a circuit diagram showing the structure of a memory array according to the first modification of the fifth embodiment. FIG. 15 is a diagram illustrating the configuration of a driving switch according to the second modification of the fifth embodiment.

2075-5330-PF (Nl); Ahddub.ptd Page 56 578150 Schematic description of simple diagrams. Fig. 16 is a circuit diagram showing a peripheral structure of the memory array of the sixth embodiment. Fig. 17 is a first circuit diagram showing a peripheral structure of a memory array according to a modification of the sixth embodiment. Fig. 18 is a second circuit diagram showing a peripheral structure of a memory array according to a modification of the sixth embodiment. Fig. 19 is a circuit diagram showing a peripheral structure of the memory array of the seventh embodiment. Fig. 20 is a circuit diagram showing a peripheral structure of a memory array according to a modification of the seventh embodiment. FIG. 21 is a schematic diagram showing the structure of the MT J memory unit. Fig. 22 is a conceptual diagram illustrating a data read operation from a MTJ memory cell. Fig. 23 is a conceptual diagram illustrating the data writing operation for the MTJ memory cell. Fig. 24 is a conceptual diagram illustrating a relationship between a data write current and a magnetization direction of a tunnel magnetoresistive element when writing data to an MTJ memory cell. Component symbol description1 MARA component, 10-memory array, 20-column decoder, 25-row decoder, 30-word line driver, 51 data writing circuit, BL, / BL bit line, ADD address signal,

2075-5330-PF (Nl); Ahddub.ptd Page 57 578150 The diagram briefly explains the ATR access transistor, the address of the CA row, the block of the CB row, the gate for the CSG row selection, the gate for the CSG row selection, CSL Row selection line, DIN write data, GND ground voltage, Mba ', MBb memory block, MC MTJ memory cell, RCSL read row selection line, RDSG read selection gate RL Current feedback wiring, RWL Read word line, TMR tunnel magnetoresistive element, Vcc supply voltage, WCSL write row select line, / WDB reverse data bus, WWL write word line, Ip, ± Iw data write current, CGa, CGb Line control gate, SPLa, SPLb current supply wiring, 3 1, 3 1 a, 3 1 b current supply circuit,

Ml, M2, M3, M4 metal wiring layer, WCSLe, WCSLo write and select lines, DBP, DBPa, DBPb data bus pairs, BDV a, BDV b, BDV m bit line driver, WCSG, WCSGe, WCSGo write Select the gate, CDGa, CDGb, WDG, RDGa, RDGb, RDG, RRG drive switch, DBo 'DBe, DBr' DB1, DB ~ DBa 'DBb ~ / DB > / DBa, / DBb data bus.

2075-5330-PF (Nl); Ahddub.ptd Page 58

Claims (1)

578150 6. Scope of patent application 1. A thin-film magnetic memory device, comprising: a plurality of memory units arranged in a matrix, each of which memorizes data written in response to application of a first and second data writing magnetic field; Word lines, each corresponding to a plurality of memory cell rows, are selected in a row so that a first data write current that generates the first data write magnetic field flows in a predetermined direction; a plurality of first bit lines, each and a plurality A corresponding setting of the memory cell row; and a data writing circuit, in the selected row, among the corresponding first bit line and the corresponding part of the selected memory cell, so that the second data writing magnetic field is generated The data writing current flows in the direction of writing the data. The data writing circuit includes a plurality of bit line driving sections. Each row of the plurality of memory cell rows is corresponding to one end side corresponding to the first bit line. Corresponding to the first node, the second node corresponding to the other end, and at least one intermediate node; in the selection row, the plural bit line drives Two of the two ends of the part corresponding to the selected memory cell have the corresponding nodes on the first bit line set to each of the first and second voltages according to the written data. 2. The thin film magnetic memory device according to item 1 of the patent application scope, further comprising: first and second data lines, each corresponding to the one end side and the other end side of the first bit line; And inverted data lines, used to communicate the first and 2075-5330-PF (Nl); Ahddub.ptd Page 59 578150 VI. Patent application scope 2 Data line complementary data; When the data is written in accordance with the written data, the first and One of the second data lines is set to one of the first and second voltages, and the inverting data line is set to the other of the first and second voltages; the plurality of bit line driving sections each have: a first And a second driving switch are respectively disposed between the first and second nodes on the corresponding first bit line and the first and second data lines; and a third driving switch are disposed on the corresponding first bit Between one of the intermediate nodes on the meta-line and the inverted data line; when the data is written, in the selected row, one of the first and second drive switches and the third drive switch become conductive. 3. The thin film magnetic memory device according to item 1 of the patent application scope, which includes: a plurality of second bit lines, each corresponding to a plurality of memory cell rows, and complementary to each corresponding first bit line Bit line pairs; and first and second data line pairs, each corresponding to the two ends of the first bit line; the first and second data line pairs each include 2 data lines, write in the data It is used to communicate two pieces of data that are complementary to each other. The data writing circuit will set up the two data lines that constitute one of the first and second data line pairs according to the written data when the data is written. One of the first and second voltages and the other; the plurality of bit line driving sections each have: 2075-5330-PF (Nl); Ahddub.ptd Page 60 578150 VI. Patent application first drive switch, the first node on the corresponding first and second bit line and the first data line pair Between; the second driving switch is provided between the corresponding second node on the corresponding first and second bit lines and the second data line pair; and the third driving switch is provided between the corresponding first bit Between one intermediate node on the line and one intermediate node on the corresponding second bit line; when the data is written, in the selected row, one of the first and second drive switches and the third drive switch Turns on. 4. For example, the thin film magnetic memory device of the scope of application for the patent, wherein when the data is written, in the selection row, the first and second switches are in accordance with the position relationship between the selection memory unit and the intermediate node. Selectively becomes conductive. 5. For example, the thin film magnetic memory device of the scope of application for a patent, wherein each of the memory cells includes: a magnetoresistive element whose resistance changes in accordance with the written data; and an access element, which is at a predetermined voltage and Correspondingly, the first bit line is connected in series with the magnetoresistive element; when data is read, the access element becomes conductive at least in the selected memory unit; the thin film magnetic memory device further includes: The data lines are arranged along the direction intersecting the plural first bit line and corresponding to one of the at least one of the intermediate nodes; and the readout selection gates, respectively, with the plural first bit line Corresponding device 2075-5330-PF (Nl); Ahddub.ptd Page 61 578150 6. The scope of the patent application is used to selectively connect the one intermediate node corresponding to the first bit line and the Read between the data lines. 6. The thin film magnetic memory device of claim 5 in which the one intermediate node is located at about the center of each of the plurality of first bit lines. 7. For the thin film magnetic memory device of the first patent application range, wherein the plurality of bit line driving sections each include: a first driver transistor, a corresponding node provided on the first bit line and the first bit line The data writing circuit is used to control opening and closing between voltages; and a second driver transistor is provided between a corresponding node on the first bit line and the second voltage, and the data writing circuit is used to control opening and closing. 8. A thin-film magnetic memory device, comprising: a plurality of memory cells arranged in a row shape, each of which stores data written in response to the application of the first and second data writing magnetic fields; the word lines for plural writing, each The setting corresponding to the plural memory cell row, in the selected row, causes the first data writing current that generates the first data writing magnetic field to flow in a predetermined direction; the plural bit lines, each corresponding to the plural memory cell row It is provided that the second data write current that generates the second data write magnetic field flows in the direction of writing the data in the selection exercise order; and the word line driving circuit for writing, in the selection row, in the corresponding write At least a part of the character line is used to make the first data write current flow; the write character line drive circuit is in the selected row, the first node corresponding to one end side of the corresponding write character line, Equivalent to the other side 2075-5330-PF (Nl); Ahddub.ptd Page 62 578150 VI. Among the second node and at least one intermediate node in the scope of patent application, the two nodes located on both sides of the part corresponding to the selected memory unit For each of the first and second voltages. 9. The thin film magnetic memory device according to item 8 of the scope of patent application, wherein the writing word line drive circuit includes M drive switches from the first to M (M: an integer of 3 or more), and In each of the memory cell columns, the first node, the at least one intermediate node, and the second node corresponding to the corresponding writing character line are arranged in this order in a direction from the one end side to the other end side; In each of the memory cell columns, the odd-numbered driving switches are respectively disposed between one of the first and second voltages and corresponding nodes, and the even-numbered driving switches are respectively disposed at the other of the first and second voltages. And the corresponding node; among the M drive switches, the two drive switches located at both ends of the portion corresponding to the selection memory unit become conductive. 10. The thin-film magnetic memory device according to item 9 of the scope of patent application, wherein, in the odd-numbered row, the odd-numbered drive switches are respectively disposed between one of the first and second voltages and the corresponding node; For the even-numbered columns, the even-numbered driving switches are respectively disposed between the other of the first and second voltages and the corresponding node. 11. A thin-film magnetic memory device, comprising: a plurality of memory cells arranged in a matrix, each of which stores data written in response to the application of a first and a second data writing magnetic field; word lines for plural writing, and Settings corresponding to plural memory cell rows 2075-5330-PF (Nl); Ahddub.ptd page 63 578150 6. Set the scope of the patent application, select the row so that the first data writing current that generates the first data writing magnetic field flows in a predetermined direction; The digital line, each corresponding to a plurality of memory cell rows, is selected to exercise the second data writing current that generates the second data writing magnetic field to flow in a direction according to the written data; and the writing word line The driving circuit, in the selected column, causes the first data writing current to flow in at least a portion of the corresponding writing word line; each writing word line is connected to a first voltage at an intermediate node; the writing use The word line drive circuit includes first and second drive switches, and each of the plurality of memory cell rows corresponds to a first node corresponding to one end side and a second node corresponding to the other end side on the corresponding writing character line. In the selection column, one of the first and second drive switches selected according to the positional relationship between the selected memory cell and the intermediate node connects the corresponding node to the second voltage. 1 2. A thin-film magnetic memory device comprising: a plurality of memory units, each of which stores data after being magnetized in a direction in which a magnetic field is written in accordance with the applied data; a plurality of bit lines, each of which is separately distinguished from the plurality of memory units A corresponding setting; and a data writing circuit, for at least one of the plurality of bit lines, supplying a data writing current that generates a data writing magnetic field in accordance with a direction of writing the data; the data writing circuit includes a plurality of First drive circuit, each and the complex 2075-5330-PF (Nl); Ahddub.ptd Page 64 578150 VI. The corresponding settings of the patented digital line, each driving the voltage at one end of the corresponding bit line; the complex bit line is divided into a complex array ; Each of the plurality of arrays has X (X: an integer of 2 or more) the bit lines, and the other ends are electrically connected via a short-circuit node; the data writing circuit further includes a plurality of second driving circuits, each of which is connected to the The corresponding setting of the plurality of arrays respectively drives the voltage corresponding to the short-circuit node; the sum of the plurality of first driving circuits selects at least one corresponding to the memory cell to drive the one of the first and second voltages according to the written data Corresponding one end side; at least one of the plurality of second driving circuits and corresponding to the selection memory cell drives the corresponding short-circuit node at the other of the first and second voltages according to the written data. 1 3. The thin-film magnetic memory device according to item 12 of the scope of patent application, wherein each of the memory cells includes: a magnetoresistive element whose resistance changes in accordance with the magnetization direction; and an access element at a predetermined voltage and corresponding Bit lines are connected in series with the magnetoresistive element; during data reading, the access element becomes conductive at least in the selected memory unit; the thin film magnetic memory device further includes: a data line for reading, along The direction that intersects the complex bit line, and the configuration corresponding to the other end side of the complex bit line; and the readout selection gates, each corresponding to the setting of the complex array, respectively 2075-5330-PF (Nl); Ahddub.ptd page 65 578150 6. Scope of patent application For reading out the shell material, it is used to selectively connect the corresponding short-circuit and output data lines. · 51 14 · A thin-film magnetic memory device, comprising: a plurality of memory units, each of which is magnetized in accordance with the direction in which the data is written, and memorizes data; each of the plurality of bit lines, respectively, and each of the plurality of memory units And the data writing circuit of the trowel, for the bit line of the complex bit line, the writing current that generates the data writing magnetic field in accordance with the direction of writing A data is supplied; The complex bit line is divided into a complex array; each bit complex array has two electrical connections between the intermediate points. The data writing circuit includes: a second driving circuit, each of which is connected to the complex bit line. Correspondingly set the voltage of one end side of the corresponding bit line to be driven respectively; and set the second driving circuit of f, I and the voltage of the other end side of the corresponding bit line to drive the corresponding bit line · ^ ° The ^ complex array of towels includes selecting at least one of the memory elements, ^ 2 the first driving circuit and corresponding 2 the second driving circuit, and writing the corresponding 2 bit lines according to The other end side is respectively driven to the first and the second voltage of each of the "15 · Shikou application patent scope of the thin film magnetism 14" wherein each of the memory cells includes: 骽. Hidden device, page 66 2075 -5330-PF (Nl); Ahddub.ptd 578150 VI. Patent application magnetoresistive element whose resistance changes according to the direction of magnetization; and access element between the predetermined voltage and corresponding bit line and the magnetoresistive element Serial connection; when data is read, the access element becomes conductive at least in the selection memory unit; the thin-film magnetic memory device further includes: a data line for reading along a direction crossing the bit line A configuration corresponding to each of the intermediate points of the plurality of bit lines; and a selection gate for reading, a setting corresponding to each of the plurality of arrays, and a connection for selectively connecting the corresponding middle when the data is read out Between the dot and the readout data line. 2075-5330-PF (Nl); Ahddub.ptd p. 67