SU995363A1 - Frequency modulator - Google Patents

Description

This invention relates to the transmission of Discrete information.

The frequency modulator containing the master oscillator of pulse sequences, the output of which through the corresponding elements of the comparison are connected to an adder, the output of which is connected to the input of the quasi-sinusoidal signal generating unit, the control unit whose control input is connected to one of the outputs of the forgar bodies of pulse sequences, and OUTPUTS: to the second inputs of the corresponding comparison elements, while the control unit is made in the form of a reversible cash register KS1X 1.

The disadvantage of the device lies in its complexity, a large number of functional units, which leads to a decrease in reliability.

The closest technical solution to the proposed one is a frequency modulator containing a shift offset reg, the first output of which is connected to the input of a quasi power co-signal, and a sequentially connected master oscillator and

characteristic frequency driver 2.

However, in the proposed modulator, noise immunity is insufficient.

The purpose of the invention is to increase the. Utility

To do this, the frequency modulator containing the spoil register is the first

to the output of which is under 1 (connected to the input of a formaker of a quasi wave signal, n connected in series by a master oscillator and a driver of characteristic frequencies, 1 are listed

15 decoder in series-connected frequency divider and modulo two adder, the output of which is connected to the first input of the shift register, the second and third inputs of which are connected respectively to the output of the decoder and frequency divider whose input is connected to the output of the characteristic frequency former and the first input desection of the ator, to the second input of which the second output of the shift register is connected, the third output of which is connected to the second input of the adder - modulo two.

Fig. 1 depicts a structural

30 electrical schematic

devices; in fig. 2 is a diagram illustrating the operation of the device.

The device contains a master oscillator 1, a driver of 2 characteristic frequencies, a divider of 3 frequencies, an adder 4 modulo two, a shift register 5, a decoder ь, a driver of a 7 quasi-sinusoidal signal.

The device works as follows.

From the generator 1, the pulse sequence is fed to the input of the generator 2 characteristic frequencies, where pulse sequences are formed with the frequency of the repetition, at the frequency of the communication, corresponding to the transmission of the logical signal J 1 and O by K times.

To the second input of the characteristic frequency generator 2, an information sequence of signals (Fig. 2a) is received, controlling the manipulation of the characteristic frequencies

From the output of the imaging unit 2, the sequence of signals (Fig. 2S) is fed to the input of the frequency divider 3 with the division factor tn. From the output, frequency divider 3 is the result of dividing the sequence. The signals (Fig. 2.B) are fed to the first (clock) input of the shift register 5 and the first input of the adder 4 modulo two, to the second input of which are fed from the second output of the shift register 5 (from the last bit). From the output of the adder 4 modulo two obtained, in the result of the addition to the module two, the sequence is fed to the second (informational) input of the shift register 5 (Fig. 2d). From the third output of the shift register 5, the signal sequence is fed to the second input of the decoder 6, to the first input of which a sequence of gating pulses is output from the output of the driver 2 characteristic frequencies. From the output of the decoder b to the third input of the shift register 5, a signal of the initial installation arrives, which eliminates the appearance of it. preempted by conditions

Failure or at the beginning of work. At the outputs of the bits of the bit of the shift register 5 (in the case under consideration), sequences of signals are shifted in phase (Fig. 2, b, e, g I 3). The impulse arrives at the input of the imager 7 (quasi-sinusoidal signal (Fig. 2 e, 3)), the formed quasi-sinusoidal signal is removed from the output (Fig. 2 and).

The shift register 5 additionally provides for dividing the sequence of signals from divider 3 two times so as to maintain equality,

Thus, in the proposed device increases noise immunity.

Claims (2)

1. Author's certificate of the USSR (553724, cl. H 03 C 3/06 ,. 1975. 2. The author's certificate of the USSR 373895, cl. H 04 L 27/10, 1971 (prototype).  LPLLAShLLSHP  l p mm mm fuiTL. j pg