SU1474863A1 - Phase manipulator - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to simplify the manipulator design. The phase manipulator contains a master oscillator 1, a divider 2 frequencies, an elec I 3, a reversible counter 4, a shift register 5 and a multiplexer 6. The information input of register 5 receives a pulse carrier, resulting from dividing the clock frequency divider 2 from generator 1. The outputs of the multi-bit register 5 are connected to the information inputs of the multiplexer 6, controlled by the counter 4. As a result of the sequential connection of the information inputs of the multiplexer 6, a phase-controlled signal is formed at the output of the latter. 1 il.

Description

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The invention relates to power, communication, and can be used in discrete information transmission systems.

The purpose of the invention is to simplify the construction of the manipulator torus.

The drawing shows the functional electrical circuit of the phase manipulator.

The phase manipulator contains a master oscillator 1, a divider 2 frequencies, 10 element I 3, a reversible counter 4, as well as a shift register 5 and a multiplexer 6.

The phase manipulator works as follows.15

The information input of the shift register 5 is pulsed to the carrier f N 9 obtained by dividing the clock frequency fT from the master oscillator 1 by a divider 2 frequency. 20

f t a n f

carried

(one)

where A is the coefficient determining the magnitude of the phase shift (for

A 2, for 4 t - A 4).

The division factor N of the frequency divider 2 determines the degree of smoothness of the phase change when changing the sign of the information.

The outputs of the multi-bit shift register 5 are connected to the information inputs of the multiplexer 6. As a result of the alternate connection of the information inputs of the multiplexer 6, a phase-controlled signal is formed at the output of the latter.

The multiplexer 6 is controlled by a reversible counter 4, to the reversing input of which the information sequence is fed and to the clock input is the synchronization frequency

N-b

TO

(2)

B is the speed of the transmitted information; 50 K is the coefficient determining the part of the duration of the information parcel during which a step change in the phase 55 of the pulsed carrier should occur.

five

0

0

five

five

0

five

0 5

The synchronization frequency fc comes from the output of the element 3, the first input of which is connected to the overflow output of the reversible counter 4.

When the sign of the information sequence changes, the signal at the output of the overflow of the reversible counter 4 permits the synchronization frequency fc to pass through the element 3 until the reversing counter 4 reaches the same overflow state. At the subsequent change of the sign of the information sequence, the counting and change of the phase of the impulse carrier begins, but already in the opposite direction, until another reversal counter 4 overflows, and this ensures a stepwise change in the phase of the pulsed carrier.

The magnitude of the step and the duration of the process of changing the phase of the pulsed carrier can vary widely in accordance with the requirements.

The conceptual design of the phase manipulator is implemented on simple discrete elements, which also provides an increase in the reliability and stability of its operation.

Claims (1)

Invention Formula A phase handler containing a master oscillator, a frequency divider, an AND element and a reversing counter, the reversing input of which is an information input of the phase handler, characterized in that, for the sake of simplicity, a shift register and a multiplexer are entered, the control inputs of which are connected to the outputs reversible counter, the clock input and the overflow output of which are connected respectively to the output and the first input of the AND element, the second input of which is the clock input of the phase manipulator, the output of which is The output of the multiplexer, the information inputs of which are connected to the outputs of the shift register, the clock input of which is connected to the output of the master oscillator and the input of the frequency divider, the output of which is connected to the information input of the shift register.