SU900423A1 - Pulse synchronization device - Google Patents

Description

(54) CONSTITUTION FOR SYNCHUNIZATION

one

The invention relates to a pulsed technique and can find P1H {change in shch {fvovyh devices for various purposes, for example, in electronic digital computers, digital measuring instruments and digital devices.

A device for synchronizing pulses is known, comprising a pair of paraphase clock pulses, a trigger, four AND elements and a trigger signal bus 1.

A disadvantage of the known device lies in the fact that in it it is common to form a signal of interference at the output of the device and start forming a useful signal if the moment coincides, the synchronized gas signals and inputs of the output element I are blocked with the rise time of the trigger signal. This is due to the fact that the prohibitory signal generated by the input element And when it overlaps the synchronizing signal, enters the input of the output element AND with a delay determined by the delay time of the signal in the input element I. As a result, the signal PULSE

interference is passed to the output of the device, which reduces the reliability of its work. This is manifested, in particular, if the switching time of elements is shorter than the time of the fall or rise of the signal front, and the response thresholds of the element vary, which is quite possible for elements with (1 direct links, for example, for integrated circuits).

The closest in technical essence to iso-teiga is a device for

“On synchronization of pulses, containing three t {1ggera, tshertor, electronic OR, and six elements II 2.

The disadvantages of this device are, j in that the form of the output signal occurs at the end of the input pulse, which reduces the speed of the device, as well as the lack of reliability of its work when scattering the sign of the time of individual elements, which can lead

20 to the formation of a signal interference at the output of the device.

The purpose of the invention is to increase the reliability of the device.

This circuit is achieved by the fact that the device for synchronizing pulses, which contains the TRN trigger, the inverter and the AND element, whose outputs through the OR element are connected to the output bus of the device, while the inverter input is connected to the sync pulse bus and the first input of the first And element, the second input which is connected to the direct output of the first trigger, and the output of the inverter is connected to the first input of the second element, the second input of which is connected to the direct output of the second trigger, and the single input of the third trigger is connected to the bus running ka, additional three inverters connected in series are introduced, the first zero input of the third trigger is connected to the start bus, and the output of the main inverter is connected to the second zero input of the third trigger and the input of the first additional H1 shertor, whose output is connected to the second zero input of the third trigger, and the outputs of the second and third additional inverters are connected respectively to the third single and zero inputs of the third trigger, the direct output of which is connected to the single input of the first tr Igger, the first zero input of the second trigger and the third input of the second element, And, the fourth input of which is connected to the inverse output of the first trigger, the second zero input of the second trigger and the fourth Zero. the input of the third flip-flop, the inverse output of which is connected to the single input of the second flip-flop, the first zero input of the first flip-flop and the third input of the first element I, the fourth input of which is connected to the inverse output of the second flip-flop, and the fourth single input of the third flip-flop.

The drawing shows the functional diagram of the device.

The device contains the first-third triggers 1-3, the first and second elements 4, 5 AND, the main and additional elements 6-9 NOT, element 10 OR, bus 11 sync pulses, bus 12 launch and the output bus 13 of the device. The third trigger contains the elements 14, 15 AND-NOT.

The device works as follows.

In the initial state, the triggers 1 and 2 are set to the zero state by a signal of the initial setup (not shown). At the same time, prohibiting signals from their single outputs are closed by elements 4, 5, respectively. In addition, in the initial state, a inhibitory signal is sent to the start bus 12 (for example, amusing a zero level), which goes to the corresponding single

and the zero inputs of trigger 3. In connection with this, both elements 14 and 15 in trigger 3 are closed, and at both its direct and inverse outputs, the enabling signals (for example,

positive polarity potentials). In the presence of an enable signal on the bus 11

element 15, and the outputs of the elements 6, 8 NOT n at the corresponding inputs of the element 14 prohibitory signals.

If a trigger signal is applied to the start bus 12 at the time the detonating signal appears on the sync pulse bus 11, element 15 is opened and element 14 remains closed because its inputs receive inhibit signals from the outputs of elements 6, 8 NOT and the element 15. At this, the trigger 3 goes to state 1, and the inhibiting signal from the output of element 15 goes to the zero output of trigger 3, respectively, and then to the corresponding input of element 4 I and to the single

5 input trnger 2, which leads to the closure of the element 4 and the input connected to the zero output of trigger 3, and to the installation of trigger 2 in state 1 with a delay equal to the response time of this trngger.

0Signal from single output trigger 2

the element 5 I is prepared for operation, and the signal from the zero output of the trigger 2 is closed by the corresponding inputs of the element 4 AND, as well as the element 14 in the trigger 3 and, moreover, the zero state of the trigger 1 is confirmed. 1 flip-flop 1 and prohibits the passage of signals through element 4 AND for the duration of the further operation of the device. After the signal on the bus 11 of the clock pulses becomes prohibiting, the output signal appears at the output of element 6, NOT, and at the corresponding input of element 5. In this case, the element 5 And opens, and at its output, and, consequently, on the output bus 13 of the device, an output signal is formed. If, on the start bus 12, the enabling signal is applied at the time of the occurrence of the inhibit signal on the sync pulse bus 11, the signal from the single output of flip-flop 3 sets the status to 1 flip-flop 1. Similarly, the signal from the single flip-flop output 1 opens 4, and opens by the signal from the zero output of this trigger, element 5 I, as well as element 15 in trigger 3, is closed on the co5 dispatch inputs and, in addition, the zero state of the second trigger is confirmed. Another permissive signal, which arrives at tiin II sync pulses, passes through element 4 AND and element 10 OR onto the output bus t3 of the device. If the duration of the sync pults received on the bus of the 11 clock pulses is equal to the duration of the pause between the clock pulses in both considered, the clock signal on the device's output bus is shifted relative to the moment of the start signal of the trigger signal for a time equal to shsh less than half of the time period of C 1 clock pulses. The elimination of short-term overlap of synchronization signals on the zero and single inputs of trigger 3, when a sync pulse appears on the bus 11 sync pulses and, therefore, the elimination of short-term low level noise on the zero and single outputs of trigger 3, is as follows. For example, if the signal at the output of element 6 is NOT and, therefore, at the input of element 7 is NOT and at the corresponding electronic input of trigger 3 is prohibiting, then at. increasing the leading edge of the resolution signal at the output of element 6; At the output of element 9, the NOT signal also remains permissive, since it is twice inverted with respect to the signal at the output of element 7 NOT. In this case, the exclusion of simultaneous appearance of resolving synchronizing signals at the zero and single inputs of the trigger 3 is provided by the element 8 NOT, since the signal is at its output, and, consequently, at the corresponding single input of the trigger 3 during the run time. elements 7, 8 is NOT prohibitive. The resolution of the output of the sample 8 does NOT appear after the signal at the input of element 8 is NOT, and, consequently, at the corresponding zero input three hectares 3 connected to the input of element 8 N become - prohibiting. This eliminates the overlap of the enabling clock signals at the single and zero inputs of the trigger 3 when the rising edge of the signal at the input of the element 7 is NOT. In the case of a falling edge of the permitting signal at the input of element 7, the inhibiting signal must first appear at the corresponding single input of the trigger 3 connected to the input of element 7 NOT and then the enabling signals at the outputs of elements 7, 9 should NOT appear. If, however, when the falling edge of the permitting signal at the input of the element 7 is NOT, this element 36 is triggered prematurely, for example, due to the difference in pores of triggering elements, and an output signal appears at its output, then the inhibiting signal at the output of element 9 does not continue saving because the elements 8, 9 have not yet worked. Thus, even in this case, the overlap of the enabling clock signals from the outputs of elements 6–9 NOT to the corresponding single and zero inputs of trigger 3 is excluded. In connection with the appearance of the enabling signal on the launch bus 12, only the ojiom of the elements 14 or 15, in which both clock signals are resolvable at the time of the incoming trigger signal. In the event that the rising front of the start signal and the rising and falling edges of the synchronizing signals at the outputs of elements 6-9 do NOT exceed the response times of these elements and, therefore, overlap in the vrayune, then the possibility of interference is also excluded on the output bus of the device even with a simultaneous short-term response to the resolution and resolution of synchronized signals at the corresponding inputs of elements 14 and 15. For example, if the signal. the trigger enters the pin 12 at the time of the rise of the leading edge of the enabling clock signal on the bus 11. Then, accordingly, there is a decrease in the enable signals at the outputs of elements 6, 8 NOT and a rise of the enabling signals at the outputs of elements 7, 9 HE. In this case, it is possible to overlap the resolving synchronization from the gnals on the corresponding inputs of the element 14 with the enabling synchronizing signals on the inputs of the element 15. As until the moment the signal arrives on the launching bar 12, both the elements 14 and 15 are closed and their outputs are kept to allow signals, while The appearance of permissive synchronization signals at the inputs of ... l element 15 and at the inputs of element 14 it is possible that the prohibition signals are briefly generated at the internal outputs of these elements. The duration of the echo of the signals depends on the time it takes for the elements 14 and 15, on the duration of the rising and falling edges of the signals, and also on the size of the thresholds for the operation of the elements. Short-time inhibit signals from the outputs of elements 14 and 15, on the one hand, affect through feedback the corresponding inputs of these same elements, on the other hand, they affect the single inputs of the trigger 1, 2 and the inputs of the 4, 5 I. If the first

element J5 is closed by the signal sent from the output of element 14, and then 8 state 1 trigger is set), the synchronous signal from the 1 sync pulse to the output and device output is resolved through element 4 I. The short signal of the noise at the output of element 15 leads in the case considered to limit the duration of the signal generated at the output of element 4I. The situation is similar if the prohibitive signal from the output of element 14 is first set to above 1 trigger 1 before the moment is closed By the indicated signal of element 15. If after switching the first trigger to state 1, element 15 is not yet closed, for example, due to insufficient duration of the inhibit signal at the output of element 14, then element 15 is closed by the inhibit signal from the zero output of trigger 1. At the same time, the inhibit signal with the zero output of the trigger 1 closes the element 5 And n keeps the trigger 2 in operation. The signal of the disturbance at the output of the element 5 is also generated. And in this case also does not occur, since it is securely closed during the transients considered in higher. This is ensured by the fact that element 5 AND, prior to the arrival of the start signal, is blocked by a inhibitory signal from a single output of trigger 2. When the considered short-time inhibit signals appear at the outputs of elements 14 and 15, the prohibition of the operation of element 5 I is first ensured by the inhibit signal from the output of element 14 and then prohibitory signal from the output of element 6 is NOT, because at this point. time signal at its output is prohibiting. After the trigger 1 is set to the state 1, the closed state of the element 5 I is provided by inhibiting the zero output of this trigger.

Similarly, the formation of interference signals at the output device not in the device is eliminated even if, when short-term inhibit signals appear at the outputs of elements 14 and 15, the first switch to state 1 flip-flop 2. In this case, element 5 remains open and at its output the signal after the appearance of the resolving clock signal at the output of element 6 is NOT.

Thus, the proposed device makes it possible to eliminate the possibility of generating interference signals on the device output bar, both with any combination of switching times of its elements, and with increasing fronts of signals compared to the switching time of elements, including;

and when increasing the fronts of the output signals arriving on the wave 11 sync pulses and the start bus 12, for example, if the fronts of the input signals are distorted due to the influence of parasitic capacitances lines cp 3 connected to the synchronous bus 11 and the start bus 12.

Formula invented

A device for snynchronization of pulses, containing a flip-flop, an inverter and two AND elements, whose outputs are connected to the output bus of the device through the OR element, while the inverter input is connected to the clock bus and the first input of the first element AND, the second input of which is connected to the direct output the first trigger, and the output of the inverter is connected to the first input of the second element I, the second input of which is connected to the direct output of the second trigger, and the single input of the third trigger is connected to the trigger strip, characterized in that increase the reliability, an additional three successively connected inverters are inserted into it, the first zero input of the third trigger is connected to the start bus, and the output of the main inverter is connected to the second zero input of the third trigger and the input of the first additional inverter, whose output is connected to the second zero input the third trigger, and the outputs of the second n of the third additional inverters are connected respectively to the third single and zero inputs of the third trigger, the direct output of which is connected to the unit a single input of the first trngger, the first zero input of the second trigger and a third input of the second element, the fourth input of which is connected to the inverse output of the first trigger, the second zero input of the second trigger and the fourth zero input of the third trnger, the inverse output of which is connected to the single input of the second trigger, the first zero input of the first trigger and the third input of the first element I, the fourth input of which is connected to the inverse output of the second trigger, the second zero input of the first trigger n quarter m single input of the third trnggera.

Sources of information taken into account in the examination

1. USSR Author's Certificate No. 307502, cl. H 03 K 3/57, 1970.

2. USSR author's certificate number 739721, cl. H 03 K 5/13, 1978.

Claims (1)

Claim A device for synchronizing pulses containing three flip-flops, an inverter and two AND elements, whose outputs through the OR element are connected to the device output bus, while the inverter input is connected to the clock bus and the first input of the first And element, the second input of which is connected to the direct output of the first trigger and the inverter output is connected to the first input of the second element I, the second input of which is connected to the direct output of the second trigger, and the single input of the third trigger is connected to the trigger bus, characterized in that reliability increases, additionally three consecutively connected inverters are added to it, the first zero input of the third trigger is connected to the startup bus, and the output of the main inverter is connected to the second zero input of the third trigger and the input of the first additional inverter, the output of which is connected to the second zero input of the third trigger , and the outputs of the second and third additional inverters are connected respectively to the third unit and zero inputs of the third trigger, the direct output of which is connected to unit th input of the first trigger, the first zero input of the second trigger and the third * it input of the second element And, the fourth input of which is connected to the inverse output of the first trigger, the second zero input of the second trigger and the fourth zero input of the third trigger, the inverse output of which is connected to the single input of the second trigger , the first zero input of the first trigger and the third input of the first element I, the fourth input of which is connected to the inverse output of the second trigger, the second zero input of the first trigger and the fourth unit nym input of the third trigger.