SU1248041A2 - Synchronizing device - Google Patents

Description

The invention relates to a pulse technique and can be used to synchronize asynchronous w - pulses with clock pulses.

The purpose of the invention is to expand the functionality by obtaining an additional sequence of synchronized pulses, delayed relative to the main one.

FIG. 1 shows an electrical functional diagram of a synchronization device; in fig. 2 - time diagrams that show his work.

The synchronization device contains three flip-flops 1, 2 and 3, the element AND- ШИИ 4, the element EXCLUSIVE OR 5, the element AND b, the counter 7 pulses, the decoder 8, the element OR 9, 3 the input of the first trigger I is connected to the first bus 10 clock pulses, with the first input of the element AND-OR 4 and with the first input of the element OR 9, K-input - with the second bus 11 clock pulses j, with the second input of the element I-W 4 and with the second input of the element OR 9, direct output - with the third input of the I-IL 4 element, the inverse output with the fourth input of the I-ШШ 4 element, the fifth and sixth inputs of which are connected to you the second trigger 2, the C input of which is connected to the output of the element EXCESSING OR 5, the first input of which is connected to the C input of the first trigger 1 and the input bus 12, the second input to the output of the element OR-OR 4, with the output bus 13 and with the R input of the third trigger 3, the C input of which is connected to the output of the Ibis element by the additional output bus 14, the output to the input of setting the zero of the counter 7 pulses, the output of which is connected to the input of the decoder 8 whose output is connected to the first input element And 6, the second. the input of which is connected to the counting input of the counter 7 pulses and to the output of the SHSh 9 element.

The synchronization device operates as follows.

In the initial state on the .12 bus (Fig. 2a) there is a level on Schick 10 (Fig. 2 &) - the first sequence of clock pulses; bus 11 (Fig. 2 &) - the second sequence of clock pulses; at the direct output of the trigger 1 (Fig. 2d) - at the output of the trigger 2 (Fig. 2A) on the bus 13 (Fig. 2e) - at the output of the tripper 3 (Fig. 2- at the output of the element 9 (Fig. 2) - the third sequence of clock pulses; at the output of the counter 7 .. (Fig. 2i) -. At the output of the decoder 8 (Fig. 2k) - on the bus 14 (Fig. 2n) - O.

When a synchronized pulse appears on bus 12 (Fig. 2a), it is a single level pulse with a duration shorter than the time interval between the falling edge of pulses of one clock sequence and the leading edge of successive pulses of another clock sequence (Fig. 2 & 6 ), at the output of element 5, a signal of the same level and duration is formed.

In case of a falling edge of the input pulse (Fig. 2c) with a clock pulse (Fig. 2c) coming through the bus 11 to the K input of the trigger 1, the latter switches to the zero state (Fig. 2 g).

With a delay due to the passage of the input pulse (Fig. 2a) to the output of element 5, the trigger 2 is switched by the falling edge of the pulse, at the C input, in the opposite (one) state (Fig. 2.A).

The zero level (fig. 2d), coming from the direct output of flip-flop 1 to the third input of element 4, prohibits the passage at the output of an element of 4 clocks arriving via bus 11 to its second input, and the unit level coming from the inverse output trigger 1 to the fourth input of element 4, together with a single unit (Fig. 2A) coming from the output of trigger 2 on the five and sixth inputs of element 4, allows the next clock pulse to pass to the output of element 4 (Fig. 25), incoming bus 10 to its first entry.

The single impulse formed in the output of element 4 (Fig. 2e) is fed to the bus 13, through the second input of element 5 to the C input of the trigger 2 and to the R input of the trigger -3. The falling edge of this pulse trigger 2 switches to the opposite (zero) state (Fig. 2e). The zero level supplied from the output of trigger 2 to the fifth and sixth inputs of element 4, prohibits the passage of subsequent clock pulses to its output. Those. at each asynchronous input pulse (Fig. 2a), only one pulse (Fig. 2e) passes through the bus 13 to the clock sequence selected by the TpHfrer

one.

When a synchronized pulse coincides (Fig. 2a) with a clock pulse (Fig. 25), received on bus 10, trigger 1 switches behind the front of the input pulse (Fig. 2a) to the unit state (Fig. 2 g) and to output element 4 passes the next impulse (Fig. 2e), arriving via bus 11 (Fig. 2b); - In the case when the input pulse (Fig. 2q) arrives in the time interval between clock pulses (Fig. 25, &) arriving on buses 10 and 11, trigger 1 does not change its state and the output element 4 passes the next impulse from the same clock bus as before.

The pulse generated on bus 13 (Fig. 2c) switches trigger 3 to the zero state (Fig. 2), the Zero level coming from the output of trigger 3 to the zero input of the counter 7 allows the counter 7 to switch with the falling edge of pulses (Fig. 2 coming from the output of the element 9 to its counting input. The code (Fig. 2i) recorded in the counter 7 increases until it reaches the value at which the decoder 8 forms at its output a unit level (Fig. 2k). In the case presented in the diagram (Fig. 2n), the value of this code is equal to 3. E The dinic level (Fig. 2k), coming from the output of the decoder 8 to the second input of element 6, allows the next pulse from the third sequence of clock pulses (Fig. 2h) fed to the first input of element 6 to pass to its output. output element

ten

15 20

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This 6 pulse (Fig. 2A) is fed to the bus 14 and to the C-ykhod of the trigger 3, switching the latter to the opposite front (one) state (Fig. 2eO. The unit level from the direct output of the trigger 3 sets the counter 7 to zero the state (fig. 2i) in which it is held until the trailing edge of the next pulse formed on bus 13 (fig. 2e) arrives.

Thus, on bus 14, pulses are generated that are synchronized with clock pulses arriving on bus 10 and II clocks, equivalent in duration to pulses formed on bus 13, and delayed relative to them by the number of half-periods of clock pulses decoder 8.

Claims (1)

Formula isob rete n i whom Sync device auth. St. No. 1213529, characterized in that, in order to expand the functionality by obtaining an additional sequence of synchronized pulses delayed relative to the main one, an additional output bus, the OR element, the pulse counter, the decoder, the And element, are introduced into it. the third trigger, the R-input of which is connected to the output bus, the C-input to the output of the I element and an additional bus, the output to the input of the zero setting of the pulse counter whose output is connected to the input of the decoder, the output connected to the first input of the AND element, the second input of which is connected to the counting input of the pulse counter and to the output of the OR element, the first input of which is connected to the first bus of clock pulses, the second to the input of the bus of clock pulses. a) ff) L) f) ff) ff) F) //; ) l) I one n n l n n n n n n n n n n one I one 1 n n n n n n n n n n n n FIG. g Compiled by T, Sokolova Editor A. Lezhnin Tehred E. Chizhmar Proofreader V. But hect 4140/57 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries M3035, Moscow, Zh-35, Raushsk nab., 4/5  Production and printing company, Uzhgorod, st. Project, 4 one  t n n n n n n n