SU1378029A1 - Pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in computing and radio engineering in building registers and memory devices, filters and delay devices using charge transfer devices based on switched capacitors. The purpose of the invention is to increase the reliability of operation. The device contains IK-triggers 1 and 4, shift register 2, clock bus 3, control bus 5, trigger 6, D-trigger 7 and frequency divider 8. Compared with the prototype, the proposed device contains a smaller number of elements and connections between them, which increases its reliability. The device eliminated the additional bus installation in the zero state, since from any arbitrary state it always comes back to its original state. The device provides tight control of control pulses to the clock. 1 il. with (L

Description

The invention relates to a pulsed technique and can be used in computational and radio engineering in building registers and memory devices, filters and delay devices using charge transfer devices based on switched capacitors. In particular, the invention

6, 7 are in the state O. In this state the device passes from any arbitrary state, arising, for example, after the device is turned on. At the initial moment of time, the leading edge of the pulse from the control bus 5 at the output of the trigger 1, at the 1-input of which can be used to form | g and G, and at the K-input - O, setting the clocking and controlling signals of the 528ХК1 chip .

The aim of the invention is to increase the reliability of operation.

The drawing shows an electrical schematic diagram of the device.

The device for generating pulses contains the first 1K-type trigger 1, the shift register 2, the synchronizing input of which is connected to the clock bus 3, and the (i + 2) output to the synchronizing input of the second 1K-type trigger 4, the third trigger 6, the direct output of which is connected to the 1 input of the second flip-flop A, the fourth D-type flip-flop 7 and the frequency divider 8, and the third flip-flop 6 is executed on the D-type flip-flop, the synchronizing input of the frequency divider is connected to the sync input of the first trigger 1 and connected to the control bus 5, and the output is frequency unit 8 is connected to the clock input of the fourth trigger, the D input of which is connected to bus 1, and the output is connected to the D input of the third trigger 6, the clock input of which is connected to the (i-2) output of the shift register 2 and connected to R- the input of the first trigger 1, the 1-input of which is connected to the bus 1, and K- the input with the bus O, the R-input of the third trigger 6 is connected to the direct output of the second trigger 4, the K-input of which is connected to the inverse output

15

20

thirty

third

the first trigger 6, the output of which is connected to the R input of the fourth trigger 4 and connected to the first output bus 9, the second, third and fourth output buses 10, 11, 12 are connected respectively to (i-2) -, i-, (i + 2) -outputs 50 of the shift register 2, the information input of which is connected to the output of the first trigger 1.

The device works as follows .55

The initial state of the device is considered as such, in which the register, 2 shifts, divisor 8, triggers 1, 4,

1 is fed, which is fed to the information input of shift register 2. The next impulse from the clock bus 3 at the next time instant sets the state 1 on the first output of register 2, which causes resetting flip-flop 1 at input R, At the next time moment, O appears at the first output of register 2, since at its information input, the potential O. takes place. The occurrence of each successive pulse from the clock bus 3 at the synchronization input of register 2 is advanced 1 by it. Thus, 25 signals, from the outputs of register 2, we get three phase-shifted sequences of pulses.

The pulses from the control bus 5 are fed to a divider 8, at the output of which we get a sequence of pulses with a frequency that sets the frequency of the output pulses,

At the next time point, the leading edge of the pulse coming from the output of divider 8, trigger 7 goes to state 1, because it is at its D input, and at the R input it is O, and thus prepares trigger 6 to switch to state 1.

At the next time point, on the trailing edge of the clock pulse coming from the output bus 10, the trigger 6 is set to state 1, because at its D-input there is 1 from the output of trigger 7, and at the R-input - O from the output of trigger 4 ,, The leading edge of the pulse coming from the output bus 12, the trigger 4 goes into state 1, because at the 1 input it acts 1, and at the K input the state O from the corresponding outputs of the trigger 6. As soon as the output of the trigger 4 appears 1, which affects the R input of the trigger 6, the trigger 6 is zeroed. the potentials at the outputs of the trigger 6 prepare the trigger 4 for switching to the state O, and at the next instant of time 35

40

6, 7 are in the state O. In this state the device passes from any arbitrary state, arising, for example, after the device is turned on. At the initial moment of time, the leading edge of the pulse from the control bus 5 at the output of the trigger 1, at the 1-input of which G acts, .a on the K-input - O, sets G, .a on the K-input - O, sets5

0

0

: 0

five

1 is fed, which is fed to the information input of shift register 2. The next impulse from the clock bus 3 at the next time instant sets the state 1 on the first output of register 2, which causes resetting flip-flop 1 at input R, At the next time moment, O appears at the first output of register 2, since at its information input, the potential O. takes place. The occurrence of each successive pulse from the clock bus 3 at the synchronization input of register 2 is advanced 1 by it.

The pulses from the control bus 5 are fed to a divider 8, at the output of which we get a sequence of pulses with a frequency that sets the frequency of the output pulses,

At the next time point, the leading edge of the pulse coming from the output of divider 8, trigger 7 goes to state 1, because it is at its D input, and at the R input it is O, and thus prepares trigger 6 to switch to state 1.

At the next time point, on the trailing edge of the clock pulse coming from the output bus 10, the trigger 6 is set to state 1, because at its D-input there is 1 from the output of trigger 7, and at the R-input - O from the output of trigger 4 The leading edge of the pulse coming from the output bus 12, the trigger 4 goes into state 1, because at the 1 input it acts 1, and at the K input the state O from the corresponding outputs of the trigger 6. As soon as the output of the trigger 4 appears 1, which affects the R input of the trigger 6, the trigger 6 is zeroed. the potentials at the outputs of the trigger 6 prepare the trigger 4 for switching to the state O, and at the next instant of time 5

0

At the front of the next clock pulse from bus 12, trigger 6 goes to state O.

Chip type 564IR2 can be used as shift register 2, divider 8 can use 564IE15 chip, chip 564TV1, 0 flip-flop device 564ТМ2 as 1K-flip-flop, and D-trigger can also be made on the basis of 564ТМ2 chip.

Compared with the prototype, the proposed pulse shaping device is simpler in construction, since it contains a smaller number of elements and connections between them, as a result of which it has high reliability. The proposed device does not require an additional bus for setting to the zero state, since A device from any arbitrary state always comes to its original state. The device provides tight binding of control pulses to clock ones.

Claims (1)

Invention Formula A device for generating pulses containing the first 1K-type trigger, a shift register, the synchronizing input of which is connected to the clock bus, and () the output to the synchronizing input of the second trigger 0 n 5 0 1K-type, control bus, the third trigger, the direct output of which is connected to the 1-input of the second trigger, which is due to the fact that, in order to increase the reliability of operation, the fourth D-type trigger and frequency divider are introduced, and the third trigger made on the D-type trigger, the clock input of the frequency divider is connected to the clock input of the first trigger and connected to the control bus, and the output of the frequency divider is connected to the clock input of the fourth trigger, the D input is connected to the bus of the logical unit, and the output is connected with D-in the house of the third trigger, the clock input of which is connected to the (i-2) output of the shift register and connected to the R input of the first trigger, 1 input of which is connected to the bus of a logical unit, and K input of a bus of a logical zero, R input The third trigger is connected to the direct output of the second trigger, K- whose input is connected to the inverse output of the third trigger, whose direct output is connected to the R-input of the fourth trigger and connected to the first output bus, the second, third and fourth output buses are connected to ( i-2) -, i-, (i + 2) - outputs shift register, the information input of which is connected to the output of the first trigger.