SU853790A1 - Pulse synchronizing device - Google Patents

Description

The invention relates to a pulse. technology and can be used in synchronizers, devices for processing, converting and transmitting information.

A clock synchronization device is known that contains two IKRS triggers, two I elements and a single vibrator, the input of which is connected to a source of control pulses, and an output to the first input of the first trigger, the output of which is connected to the third input of the second trigger And, the first input of which is connected to the first input of the second element I and the clock pulse source, and the output is connected to the first input of the second trigger, the second input of which is connected to the second 20 output of the second trigger, and the first output - a second input of the second AND gate, the output of which, is yuschiys output clock device connected to vtorym25

the entrance of the first trigger

The disadvantages of the known device are the necessity of applying at the input of the control signal a single vibrator with an output-Q duration.

pulse, less than or equal to the duration of the clock pulse, the inaccuracy of synchronization associated with the ambiguity of the allocation of the first or second clock pulse following the arrival of the control signal, depending on the relative position in time of the control and clock pulses.

It is also known a device for synchronizing pulses, which contains two triggers and an I-NC element, one of the inputs of which is connected to the second output of the second trigger, and the other connected to the clock bus and the C input of the second trigger, the O input of which is connected to. the output of the first trigger, the D input of which is connected to the logic level 1, the C input to the sync bus bar, and the reset input to the inverse output of the second trigger; C2.

The disadvantage of this device is its low reliability, since extra fragmentation pulses can be generated at the device output.

Claims (2)

The aim of the invention is to increase the reliability of the device. This goal is achieved by the fact that, in a device for synchronization, there are pulses containing two flip-flops and an NAND element, one of the inputs of which is connected to the output of the second trigger, whose D input is connected to the output of the first trigger, whose 0 input is connected to the level logical 1, with the C input of the first trig, the geur is connected to the sync bus of MiMix pulses, and the C input of the second trigger is connected to the bus of clock pulses, an inverter is input, the input of which is connected to the bus of clock pulses, and the output is connected to another input of the element AND-NOT, which exit on coupled to the reset inputs of flip-flops. The drawing shows a block diagram of the device. A device for synchronizing pulses contains triggers 1 and 2 of type D, an element AND-HE 3, an inverter 4, as well as a bus 5 of synchronized pulses, a bus 6 clock pulses, an output 7 of the device. In the initial state, the triggers 1, 2 are in the zero state, i.e., low voltage levels are set at their direct outputs, respectively, and low potential is present at output 7. The clock frequency is fed continuously. On the bus 5 low potential. When a positive synchronized pulse of arbitrary duration appears on bus 5, trigger 1 is transferred to one state, while from the direct output of trigger 1 high potential arrives at the D input of the trigger 2. Positive front of the first clock pulse received at the C input of the trigger 2 , after installing on its D-input a single potential, on the forward output of flip-flop 2, a single potential is set, which arrives at the first input of the AND-HE 3 element, preparing Lebanon to pass the signal from the inverter 4, and simultaneously The output edge of the output signal forms at this time. At the moment the input clock ends at the output of the inverter pa 4, a single potential is formed that goes to the second input of the AND-HE element 3, and the output of the AND-HE element 3 a zero potential is formed. The zero potential from the output of the element IS-NE 3, arriving at the installation R-inputs, sets the triggers 1 and 2 to the initial zero state, regardless of whether the synchronized pulse is removed or still continues to flow and forms the output pulse 7 at the output 7. The synchronization device is ready to receive a new synchronized pulse. Thus, the device provides synchronization of signals of arbitrary duration, without additional conversion by duration, while the output 7 of the device uniquely allocates the first clock pulse received on bus 6 after the appearance of the synchronized signal on bus 5. Formula for synchronization of pulses two triggers and an NAND element, one of the inputs of which is connected to the output of the second trigger, the D input of which is connected to the output of the first trigger, the D input of which is connected to logical 1, with the C input of the first trigger connected to the bus clock, pulses, and the C input of the second trigger with the bus clock pulses, which is so that, in order to increase reliability, an inverter is inputted into it with the clock bus, and the output is connected to another input of the NAND element, the output of which is connected to the inputs of a trigger. Sources of information taken into account during the examination 1. USSR author's certificate No. 585597, cl. H 03 K 5/153, 1977., 2. Gnnikov B.C. Integral electronics in measuring devices, L., Energie, 1973, p., 114, fig. bia