SU966874A2 - Pulse shaper - Google Patents

Description

(54) FORMER OF PULSES The publication refers to the pulse technique and can be used in automation and digital measuring devices. By ocHd BHOMy auth.St. 680149 a pulse shaper is known that contains input and output D-flip-flops, the B-input of the input D-flip-flop is connected to the control signal bus, and the C-input of the O of the figger and the output D-flip-flop are connected to the clock pulse bus, while the non-inverting input of the input D-flip-flop. connected to; The C-input of the output D-flip-flop f The disadvantage of this pulse generator is impossible-. The formation of not only one impulse, but also impulses. The purpose of the invention is to enhance the functional capabilities of the pulse former by obtaining a series of pulses. The stated goal is reached; It is due to the fact that the NAND element is entered into the pulse generator, the first input of the NAND element is connected to the direct output of the input D trigger, the installation R input of which is connected to the output of the I NB element, the second input of the last with shindy sync pulses and the third input - with the bus mode selection. FIG. 1 shows the cxeMk pulse driver functional; in fig. 2 shows timing diagrams explaining its operation in the single pulse formation mode and in the series of pulse generation mode. The pulse shaper contains an input D-flip-flop 1, an output D-flip-flop 2, an NAND gate 3, a control signal bus 4, a clock pulse bus 5, a mode selection bus 6. . The device works as follows. . In the initial state on the bus 4 of the control signal there is a logic zero level, on the bus 5 clock pulses - a continuous sequence of pulses. If there is a choice of the mode of a logical zero level on the bus 6 from the output of the NAND element. 3, the high level of the logical unit is fed to the setup R-input of the D-flip-flop driver, operates in the single pulse generation mode (Fig. 2a).

To translate the pulse former into the pulse train formation mode, it is necessary to feed the level 6 of the bus onto bus 6. Consider the operation of the pulse former in the formation mode. pulse series.

in the initial state, input 1 and output 2 D-flip-flops are in zero states. The zero state of D-flip-flop 1 is confirmed by the level of the logic zero of the control signal present on its D-input, since the setting R-input of the D-flip-flop 1 from the output of IS-NO 3 is the level of the logical one, and the zero state D -trigger 2 is confirmed by the level of logical zero that is present at its R-input in the pauses between pulses arriving on the bus 5-When a logical unit level appears on the 4th bus, the nearest whole synchronizing impulse by its positive front through the C-input sets the .D -trigger 1 in one an IDE; e state that. This is possible due to the fact that at the same time on the D-input of the Trigger 1 there is a level of the logical unit of the control signal,.

At the same time, at the direct output of the D-trigger 1, a positive differential is generated, which, acting on the C input of the L flip-flop 2, translates it into a single sarting. Such a translation of the O-flip-flop 2 is possible due to the fact that B etog. the time of the y-input of the output 5-flip-flop 2 is the level of the logical unit of the clock pulses. After a high level of logical unit, appears at the forward output of and -trigger -1, a high level is present at all three inputs of the AND-HB 3 element and, therefore, the output of the AND-NE 3 element appears logical zero, which, acting on the R input of Dtrigger 1, resets it to the zero state. Logical zero on the forward

the output of the P-flip-flop 1; input element AND-NOT 3, provides the appearance at the output of the element AND-NOT 3 levels of logical units. After the end of the clock at the R-input of Otrigger 2, a logic zero level appears, returning the P-trigger 2 to its initial zero state, as well as confirming the level of the logical unit at the output of the element

AND-NOT 3. The positive front of the next clock pulse at the C-input sets the p-flip-flop 1 to the unit state again and the whole process repeats.

Impulse formation continues until a logical unit level is present at the input of the control signal (Fig. 26). When a logical zero signal appears on the bus of the logical zero, the next clock pulse cannot trigger the input trigger and the formation of the pulse train ends.

The pulse shaper allows you to form both single pulses and their series.

Claims (1)

Invention Formula Pulse shaper auth. St. 680149, in connection with the fact that, with the purpose of expanding the functionality, the element 1ШЕ is inserted into the driver, with the first input of the element; AND IS NOT connected to the direct output of the input D-flip-flop, the setting R- whose input is connected to the output of the NAND element, the second input of the latter is connected to the clock bus, and the third input is connected to the mode selection bus. Information sources, taken into account in the examination 1, USSR Copyright Certificate No. 680149, Cl, H 03 K; 5/01, 1974. t And 3 WITH t J WITH and