SU836817A1 - Digital frequency detector - Google Patents

Description

(54) DIGITAL FREQUENCY DETECTOR

fc The invention relates to a communication technique and can be used for ff, e tecting frequency telegraphy signals. in which the difference in the frequency periods of pressing and pressing is comparable with the period of the reference frequency. A digital frequency detector is known, containing, a detuning determinant, made in the form of a serially connected key, a frequency divider whose counting input is the reference signal input, and a D-flip-flop, while the output of the frequency divider is connected to the D-flip-flop information input, and low pass filter l. However, in the well-known digital frequency detector, when the difference between the periods of pressing and pressing frequencies is comparable to the period of the reference frequency, the detection accuracy is not sufficient, i.e. The prevalence of detected THI sichal is large. This deficiency is caused by temporal errors in the operation of the frequency divider due to the non-phase of the signals of the reference and operating frequencies. The purpose of the invention is to improve the detection accuracy. To do this, a digital frequency detector containing a detuning determinant, made in the form of a serially connected key, a frequency divider whose counting input is the reference signal input, and a D-flip-flop, wherein the output of the frequency divider is connected to the D-flip-flop information input, and also a low-pass filter, introduced n additional determinants of detuning, pulse distributor, polling pulse shaper and majority element, while the inputs of the pulse distributor and polling pulse shaper are are the same and are the signal input of the detector, the outputs of the pulse distributor are connected to the first inputs of the keys of the corresponding defined distance. the second inputs of all the keys. , are combined and connected to the output of the polling pulse generator, the key output is connected to the clock input. D-flip-flop in each determinant detuning, and the majority element is connected between the outputs of the determinants of the disorder and the input of the low-pass filter. The drawing shows a structural electrical circuit of the proposed digital frequency detector.

The digital frequency detector contains a detuning identifier 1, a key 2, a frequency divider 3, a D-flip-flop 4, a low-pass filter 5, a pulse distributor 6, a polling pulse driver 7 and a majority element 8.

Digital frequency detector works as follows. A device signal arrives at the input signal, limited by the moments of zero crossing. At the outputs of the pulse distributor b, pulses are formed, the duration of which is equal to the period of the input signal, and the following frequency is equal to fp / n, where n is the conversion factor equal to the number of determinants of mismatch 1. Poll pulse generator 7 forms a short pulse coinciding with the leading edge of the input TH -signal. When the key 2 of the pulses of the pulse distributor 6 and the pulse of the polling pulse generator 7 coincides, the polling pulse passes the output of the key 2 and resets the frequency divider 3 to the initial state. The frequency divider 3 arrives at the input of frequency divider 3. The division factor of frequency divider 3 is selected.

such that --i. ,

 2 - n

where fon is the reference frequency, K is the division factor of frequency divider 3, fcp is the average frequency of the input frequency signal. In this case, the half-period of the output signal of the frequency divider 3 is equal to the period of the output signal of the pulse distributor 6, provided that it arrives at its frequency input. If the device receives a frequency less than, then by the time of the next polling pulse the frequency divider 3 will not change its state (i.e. the O signal will be output) and at the same time the divider is reset, the D-flip-flop 4 will be recorded the

If the devices come to the input: the frequency is greater than fcp, then by the time the next polling pulse arrives, frequency divider 3 will change its state (i.e. signal 1 at its output) and D-flip-flop 4 will record this state simultaneously with the reset divider 3. The output signals of the D-flip-flops 4 of all the mismatch determinants 1 are fed to the inputs of the majority element 8, which serves to separate the modulating signal. To decide on the presence of one of the two (press or press) frequencies at the device input, it is necessary to analyze the value of the outputs of all determinants of mismatch 1. In the majority element 8, the values of O and 1 are input to its input, and the value of the signal at the output of the majority element 8 define

The ratio of the input signals. If the majority of input signals are .1, then the output of element 8 is according to 1 and vice versa. The mismatch determinants 1 do not input signals to the majority element 8 simultaneously. The memory functions in the proposed device are performed by D-flip-flops 4. The signal at the output of D-flip-flop 4 is stored until it appears at the clock input of D-flip-flop 4 following the polling pulse when the signal value at the output of D-flip-flop 4 is either confirmed or changed on the opposite

A decrease in the temporal prevalence and, therefore, an increase in the detection accuracy, is achieved by increasing the detuning time by n times and using n detuning determinants 1, working with a shift in one period relative to each other. In the proposed detector, a comparison result can be obtained in each period of the input signal, while in a known device, several periods of the input frequency are needed to obtain the result of one comparison.

The technical and economic efficiency of the proposed digital frequency detector, as compared with the known one, is to improve the quality of the modulating signal recovery, i.e. increase the detection accuracy when the difference between the periods of pressing and pressing is comparable to the period of the reference frequency.

Claims (1)

1. Mashbits L.M. Digital signal processing in radiotelegraph communication. M., Holy, p. 48, fig. 2.21 (prototype)