SU907859A1 - Frequency-manipulated signal receiving device - Google Patents

Description

(54) DEVICE FOR ACCEPTING FREQUENCY-MANIPULATED SIGNALS

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The invention relates to a communication technique and can be used to receive signals with a combined frequency-phase shift keying.

A device for receiving frequency-manipulated signals is known, which contains an input matching unit whose output is connected to the inputs of two channels, each of which consists of a phase-locked frequency control unit, a phase detector, an adder, an integrator and a memory unit connected in series, the output of each channel is connected to the corresponding input of the OR element, the second inputs of the phase channel detectors are connected to the output of the input matching unit, and the second inputs of the channel adders are connected to the outputs of the phase etektorov opposite channels and block release of significant points of the signal 1.

However, the known device does not provide adequate noise immunity.

The purpose of the invention is to increase noise immunity.

To achieve this goal, a device for receiving frequency-manipulated signals containing an input matching unit, the output of which is connected to the inputs of two channels, each of which consists of series-connected phase-locked loops, phase

 detector, adder, integrator and memory block, the output of each channel is connected to the corresponding input of the OR element, the second inputs of the phase channel detectors are connected to the output of the input matching unit, and the second inputs of the channel adders are connected to the outputs of the phase detectors of the opposite channels signal moments, an additional block for the selection of significant signal moments is introduced, the first and second additional phase detectors, the additional adder, the averaging block and controlled oscillators The corresponding outputs of which are connected to the corresponding inputs of the integrators and channel memory units and the first inputs of the first and second additional phase detectors, the second inputs of which, respectively, are connected to the outputs of the corresponding adders of channels through the block for highlighting significant signal moments and the additional block for highlighting significant signal points. the first and second additional phase detectors are connected to the first and second inputs of the additional adder, the output of which is through the average A block is connected to the input of a controlled generator.

FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 - timing diagrams for the operation of the device.

The device contains an input matching unit 1, the element OR 2, two channels 3 and 4, each of which contains a block 5 (6) phase-locked loop iJacTOTbi, a phase detector 7 (8), an adder 9 (10), an integratator 11 (12) and a block 13 (14) of the memory, in addition, the device contains a block 15 for extracting significant signal moments, an additional block 16 for extracting significant signal moments, a first and second additional phase detectors 17 and 18, an additional adder 19, an averaging block 20 and a controlled oscillator 21 .

The device works as follows.

The input signal, modulated in phase and frequency, through block 1 enters the blocks 5 and 6 of the phase locked loop and the phase detectors 7 and 8. The original binary signal is shown in FIG. 2a, and the signal with frequency-phase manipulation in FIG. 2 b. The phase comparison in block 5 is performed at the doubled upper characteristic frequency, and at block 6 - at the doubled lower frequency frequency. Operation at double frequencies eliminates the effect of phase shift keying. The reference oscillations of the characteristic frequencies (Fig. 2c and d) are transmitted to the corresponding phase detectors 7 and 8, where the phase detection of the received signal is performed. The output voltages of the phase detectors 7 and 8 are shown in FIG. 2 d and e respectively. The output of the adder 9 is the sum of the output voltages of the phase detectors 7 and 8 (Fig. 2 g), and at the output of the adder 10 their difference (Fig. 2 3).

Blocks 15 and 16 of the selection of significant moments form short pulses at the moment of transition of output voltages of adders 9 and 10 through zero (Fig. 2 and. And K), respectively. The maximum frequency of following significant moments in each channel is half the signal clock frequency, and their mutual offset is Jt. Therefore, the output signals of blocks 15 and 16 are received in the phase-locked loop at separate phase detectors 17 and 18, to the other inputs of which the output signals of the controlled oscillator 21 are received with a frequency equal to half the clock frequency and shifted in phase by 51

(Fig. 2 l and m). The summation of the output signals of the phase detectors 17 and 18 in the adder 19 provides a reduction in clock synchronization time. After averaging in the averaging unit 20, the phase error signal arrives at the controlled oscillator 21, changing the phase of its output signals in the direction of decreasing the phase error.

The output voltages of the adders 9 and 10 are integrated in the integrators 11 and 12. According to the clock synchronization signals taken from the corresponding output of the controlled oscillator 21, the sign of the output voltage of the integrator 11 (12) is stored in the binary memory block 13 (14). Then integrator 11 (12) is performed. The output voltage diagrams of the integrators 11 and 12 are shown in FIG. 2 and o, and the output voltages of the binary blocks 13 and 14 of the memory are shown in FIG. 2 n and p respectively. By entering the inputs of the element OR 2, the binary output signals of the blocks 13 and 14 form a binary signal at its output in accordance with this logical operation (Fig. 2c). This signal is the output of the device. As can be seen from the comparison chart of FIG. 2 s and 2a, it coincides with the original binary signal, but is delayed by two cycles.

The technical efficiency of the proposed device consists in the possibility of receiving signals with an arbitrary frequency modulation index and in improving the noise immunity with respect to the receivers of the frequency-manipulated signals.

Claims (1)

Invention Formula A device for receiving frequency-manipulated signals, containing an input matching unit, the output of which is connected to the inputs of two channels, each of which consists of a series, connected phase-locked loop, phase detector, adder, integrator and memory, the output of each The channel is connected to the corresponding input of the OR element, the second inputs of the channel phase detectors are connected to the output of the input matching block, and the second inputs of the channel adders are connected to the outputs of the phase detectors of the opposite channels, and the block for highlighting significant signal moments, characterized in that In order to improve noise immunity, an additional block for extracting significant signal moments is introduced, the first and second additional phase detectors, an additional adder, averaging block and controlled generator op sootvetstvuyuiHie outputs are connected to corresponding inputs of integrators and blocks the memory channels and the first inputs of the first and second additional phase detectors, the second inputs of which, respectively, through the block of significant signal moments extraction and the additional block of significant signal moments, are connected to the outputs of the corresponding channel adders, and the outputs of the first and second additional phase detectors are connected respectively to the first and the second inputs of the additional adder, the output of which is connected to the input of the controlled generator via the averaging unit. Sources of information taken into account in the examination 1. US Patent No. 3743775, cl. 178/88, 1973 (prototype). R one