SU809152A1 - Device for bcd-to-binary conversion - Google Patents

Description

(54) DEVICE FOR TRANSFORMING BINARY-TO-DENIAL NUMBER TO BINARY

the initial binary-decimal number by the number 1010 and in the transfer of the result obtained from the input to the output of the auxiliary n-bit shift register. In this case, clock cycles are spent on inputting a binary-decimal number into the device.

The closest technical solution to the present invention is a device for converting binary-decimal numbers into binary ones, containing a distributor, whose information input is connected to the first control bus of the device, the setup input - with the device reset bus and zero trigger input, the single input of which is connected to the output of the first element And, and the single output to the first input of the second element And through the first element NOT to the first input of the third element And, the output of which is connected to the first input of the first e OR, whose output is connected to the output bus of the device, and the second input to the output of the adder and input of the delay element, the output of which is connected to the first input of the adder, the second input of which is connected to the output of the second AND element, while the distributor outputs from first to the fourth is connected to the inputs of the second OR element, the output of which is connected to the first input of the fourth element AND, the bit outputs of the distributor from the fifth to the eighth are connected to the inputs of the third OR element, the output of which is connected to the first the input of the fifth element And, the bit outputs of the distributor from ninth to twelfth are connected to the inputs of the fourth element OR, the output of which is connected to the first input of the sixth element And, the bit outputs of the distributor from the thirteenth to the fifteenth are connected to the inputs of the fifth element OR, the output which is connected to the first input of the seventh element And, the sixteenth discharge output of the distributor is connected to the first input of the first element And, the second input of which is connected to the input information bus of the device and to the second input The fourth, fifth, sixth and seventh elements I, and also the eighth element I, the first input of which is connected to the second control bus of the device and through the second element NOT to the first input of the ninth element I 3.

The disadvantages of the known device are low speed, since converting binary-decimal numbers to binary requires at least 5 steps. This is because n cycles are required to form an n-bit result, and each cycle consists of a shift (multiplication by two) of a binary-decimal number and a correction step. Corrective chips are defined as those trades for which condition 4-2 holds. where M is a binary number (O or 1), and p is the number of binary bits of the binary-decimal tetrad. In the case when this condition is satisfied, the corrective step consists in sending the corrective OOP code to the summator, where the contents of these tetrads are combined with the correction code. This compensates for the error resulting from the subsequent binary digits. Here, as in the above cases, n clock cycles are spent on entering a binary-decimal number into the device.

The purpose of the invention is to increase the speed of the device for converting binary-decimal numbers into binary ones.

This goal is achieved due to the fact that in the device for converting binary-decimal numbers into binary ones, contains a distributor, whose information input is connected to the first control bus of the device, the installation input is the device reset bus and the zero input of the trigger, the single input of which is connected to the output The first element is AND, and the unit output is to the first input of the second element AND, and through the first element is NOT to the first input of the third element AND, the output of which is connected to the first input of the first element OR, the output otorrhea connected to the output device bus and the second input - to the output of the adder and the input of delay element whose output is connected to a first input of an adder, whose second input

0 is connected to the output of the second element AND, while the first and fourth distributor bit outputs are connected to the inputs of the second OR element, the output of which is connected to the first input of the fourth AND element, the binary outputs of the distributor

5 from the fifth to the eighth are connected to the inputs of the third element OR, the output of which is connected to the first input of the fifth element AND, the bit outputs of the distributor from ninth to twelfth are connected to the inputs of the fourth element OR, the output of which is connected to the first input of the sixth element And, the bit outputs of the distributors from the thirteenth to the fifteenth are connected to the inputs of the fifth OR element, the output of which is connected to the first input of the seventh element And, the sixteenth discharge output of the distributor is connected to the first input of the first ele And the second input of which is connected to the input information bus of the device and to the second inputs of the fourth, fifth, sixth and seventh elements of AND, as well as the eighth element of AND, the first input of which is connected to the second control bus of the device and through the second element NOT to the first the input of the ninth AND element, the multiplication unit, the additional OR element, the additional adders and the additional delay elements are introduced, while the output of the fourth AND element is connected to the first input through the nine titact additional delay element m of the first additional adder, the output of which is connected to the second inputs of the eighth and ninth elements And, the output of the fifth element And through the first six-stroke additional element, that the delay is connected to the first input of the second additional adder, the output of which is connected to the first input of the third additional adder and through the first push-pull additional delay element with the second input of the third additional adder, the output of which is connected to the second input of the first additional adder, the output pole And through the three-stroke additional delay element is connected to the first input of the fourth additional adder, whose input is connected to the first input of the fifth additional adder and through the second two-stroke additional delay element to the second input of the fifth additional adder, the output of which is connected to the second input of the second additional adder, the output of the seventh element And is connected to the first input of the sixth additional adder and through the third push-pull additional element delay ki with the second input of the sixth additional adder, the output of which is connected to the second input of the fourth additional adder, the output of the ninth element And through the second six-stroke additional delay element connected to the first input of the additional element OR, the second input of which is connected to the output of the eighth element I at In this case, the output of the additional element OR is connected to the second inputs of the second and third elements I. In FIG. 1 is a functional block diagram of a device for converting binary-decimal numbers to binary ones; in fig. 2 and 3 - time diagrams. The device contains a distributor 1, the information input of which is connected to the first control bus 2, the installation input - to the reset bus 3 and the zero input of the trigger 4, whose single input is connected to the output of the first element 5; and a single output to the first input of the second element AND 6 and through the first element NOT 7 to the first input of the third element AND 8, the output of which is connected to the first input of the first element OR 9, the output of which is connected to the output bus 10, and the second input to the output the adder 11 and the input of the delay element 12, the output of which is connected to the first input of the adder 11, the second input of which is connected to the output of the second element AND 6, the bit outputs of the distributor 1 from the first to the fourth are connected to the inputs of the second element OR 13, the output of which is connected to the first at one of the fourth element And 14, the bit outputs of the distributor 1 from the fifth to the eighth are connected to the inputs of the third element OR 15, the output of which is connected to the first input of the fifth element And 16, the bit outputs of the distributor 1 from the ninth to the twelfth are connected to the inputs of the fourth element OR 17, the output of which is connected to the first input of the sixth element AND 18, the discharge outputs of the distributor 1 from the thirteenth to the fifteenth are connected to the inputs of the fifth element OR 19, the output of which is connected to the first input of the seventh element AND 20, sixth The tenth bit output of the distributor 1 is connected to the first input of the first element I 5, the second input of which is connected to the input data bus 21 and to the second inputs of the fourth, fifth, sixth and seventh elements 14, 16, 18 and 20, 22 - the eighth the element I, the first input of which is connected to the second control bus 23 and through the second element NOT 24 to the first input of the ninth element AND 25, the output of the fourth element AND 14 through the nine additional additional delay element 26 is connected to the first input of the first additional adder 27, output whom connected to the second inputs of the eighth and ninth elements And 22 and 25, the output of the fifth element And 16 through the first six-stroke additional delay element 28 is connected to the first input of the second additional adder 29, the output of which is connected to the first input of the third additional adder 30 and through the first push-pull additional delay element 31 with the second input of the third additional adder 30, the output of which is connected to the second input of the first additional adder 27 output of the sixth element I 18 through a three-stroke d Additional delay element 32 is connected to the first input of the fourth additional adder 33, the output of which is connected to the first input of the fifth additional adder 34 and through the second two-stroke additional delay element 35 to the second input of the fifth additional adder 34 whose output is connected to the second input of the second additional adder 29, the output of the seventh element And is connected to the first input of the sixth additional adder 36 and through the third push-pull additional delay element 37 to the second input w additional adder 33, the output of the ninth element AND 25 through the second six-stroke additional delay element 38 is connected to the first input of the additional element OR 39, the second input of which through the multiplication unit 40 is connected to the output of the eighth element And 22, the output of the additional element OR 39 is connected And the second inputs of the second and third elements And 6 and 8, 41 - adders, 42 - one-step delay elements, 43 - push-pull delay elements, 44 - four-stroke delay element. FIG. Figures 2 and 3 show the timing diagrams of the operation of the device for converting binary-decimal numbers to binary, where 45 is the code of the binary-decimal number supplied to the input information bus 21; 46, 47, 48, 49 — logical levels at the first, second, third, and n 16th gaps of the distributor 1, respectively; 50-logical levels at the output of the element OR 13, 51-logical levels at the output of the element OR 19, 52 - logical levels at the output of the element AND 20, 53 - logical levels at the output of the delay element 37, 54 - logical levels at the output of the adder 36, 55 - logical levels at the output of the element 32 delay, 56 - logical levels at the output of the adder 33, 57 - logical levels at the output of the element 35 delay, 58 - logical levels at the output of the adder 34, 59 - logical levels at the output of the element 28 delay, 60: - logical levels at the output of the adder 29, 61 - logical levels on the output of the delay element 31, 62 - logical levels at the output of the adder 30, 63 - logical levels at the output of the delay element 26, 64 - logical levels at the output of the adder 27, 65 - result code, 66 - logical levels on the control bus 23, 67 - logical levels at the output of the element AND 5, 68 — logical levels at the output of the element OR 39. The operation of the device for converting binary-decimal numbers to binary for the case of sixteen-bit numbers, in which the sign is contained in the last digit, is implemented as follows. In the initial state, by means of a single logic level supplied via the reset bus 3, the trigger 4 and the distributor 1 are set to the zero state. In the first cycle, a pulse is applied to the control bus 2, which is distributed in 16 clock cycles as single logical levels over the discharge outputs of the distributor 1 (see Fig. 2 and 3 plots 46-49). Starting from the first clock to the input information bus 21, the binary number code (see Fig. 2 and 3 plot 45) is supplied starting from the lower order bits. The unit logic level from the output of the element OR 13 (see Fig. 2 and 3 plot 50) unlocks the elements I 14 from the first to the fourth cycles, with the result that during the indicated cycles the first tetrad of the initial binary-decimal number is fed to the input of the delay element 26 which delays the indicated tetrad by nine cycles (see Figs. 2 and 3, plot 63). Similarly, the second tetrad of the initial binary-decimal number from the fifth to the eighth cycle is fed to the input of the delay element 28, which delays this tetrad by a fraction of the clock (see plot 59). Similarly, from the ninth to the twelfth clock cycles, a third tetrad of the original binary-tenth number is fed to the input of the delay element 32, which is removed from the output of the specified delay element delayed by 3 cycles (see plot 55). The unit logic level from the output of the element OR 19 (see plot 51) from the thirteenth to the fifteenth clock cycles unlocks the AND 20 element (see plot of 52), with the result that the last (fourth) incomplete tetrad is removed from the output of the element 20 and 20 source binary-decimal number. On the delay element 37, the fourth tetrad is delayed by two cycles (see plot 53). As a consequence, the output of the adder 36 results in the multiplication of the fourth tetrad by 1010 (see plot 54), which is added to the third tetrada supplied from the delay element 32 at the summator 33 (see plot 56). The result obtained with the help of delay element 35 (see plot 57) and adder 34 (see plot 58) is multiplied by 1010 and added to the second tetrad fed from output of delay block 28 on adder 29 (see plot 60). This latter result, using delay element 31 (see plot 61) and adder 30 (see plot 62), is also multiplied by 1010 and added to the first tetrads from output of delay block 26 on adder 27 (see plot 64). JB in the case of converting binary-decimal codes of integers, the binary code removed from the output of the adder 27 is the result of the conversion, which, due to the presence on the control bus 23 (see Fig. 2 plot 66) of zero logic level through the AND 25 element and the element 38 delays are fed to the input of the element OR 38. At the sixteenth clock cycle from the output of element 5, a logical level is recorded corresponding to the sign of the binary-decimal number being converted (see plot 67), which is fixed in trigger 4. If the initial binary-decimal number is negative , Ie trigger 4 is in the unit state. The AND 6 element is unlocked and the conversion result from the output of the OR 39 element is fed to the input of the adder 11. This latter, together with the delay element 12, translates the conversion result into an additional code that through the electronic OR 9 output bus 10 (see plot 65). In case the initial binary-decimal number is positive, trigger 4 is in the zero state, as a result of which the result of the conversion from the output of the element OR 39 through the elements AND 8 and OR 9 falls on the output strip 10 (see plot 65). In FIG. 2 considers the case of converting a binary-decimal code of an integer O.llllOOlOOlOOlOi into a binary code 0.001111011110101, which is issued from the sixteenth to the thirty-first clock cycle. Thus, the proposed device performs the conversion of binary-decimal codes of integers into binary ones in less than 2 cycles, i.e. is 2.5 times faster than the known devices for converting binary-decimal numbers to binary ones.

In the case of converting binary-decimal codes of fractional numbers into binary ones, a single logical level is applied to the control pad 23 (see Fig. 3, plot 66). As a result, the output of the adder 27 through the element And 22 is connected to the input of the multiplication unit 40. Since the initial fractional binary-decimal number is taken as an integer, block 40 multiplies the conversion result taken from adder 27 by 1/2 where m is the size of the decimal number being converted. Thus, in this case, m 4 and block 40 multiplies the result of the conversion by the number 1/10000. In order to obtain conversion accuracy for the maximum error of the order of the sixteenth bit of the desired binary code of the converted binary-decimal number, block 40, according to FIG. 1, multiplies by the number 0.00000000000001101000110111. The result obtained from the output of multiplication unit 40 is fed to the input of the element OR 39 (see plot 68 in FIG. 3). Further, the device functions similarly to that considered, and the result is removed from the output slit 10 (see Fig. 3 plot 65) from the 21st to the 36th cycle.

FIG. 3, the case of converting a binary-decimal code of a fractional number 1.101001101000010 into a binary code 1.011101110011111 is considered. Thus, this device performs the conversion of binary-decimal codes of fractional numbers into binary ones in 2n + 4 cycles, i.e. is approximately 2.2 times faster than conventional devices for converting binary-decimal numbers to binary ones.

Thus, the present invention achieves a speed increase of converting binary-decimal codes of integers to binary 2.5 times and binary fractional codes of binary numbers 2.2 times compared to known devices.

Invention Formula

A device for converting binary-decimal numbers into binary ones, containing a distributor, whose information input is connected to the first control unit of the device, the installation input - with a device resetting device and a zero trigger input, the single input of which is connected to the output of the first And element, and the single output - to the first input of the second element I and through the first element NOT to the first input of the third element I, the output of which is connected to the first input of the first element OR, the output of which is connected to the device output bar, the second input to the output of the adder and the input of the delay element, the output of which is connected to the first input of the adder, the second input of which is connected to the output of the second AND element, while the bit outputs of the distributor from the first to the fourth are connected to the inputs of the second OR element, the output of which is connected to the first input of the fourth element AND, the bit outputs of the distributor from the fifth to the eighth connection of the yen with the inputs of the third element OR, the output of which is connected to the first input of the second element AND, the bit outputs of the distributor from nine tons second through twelfth connected to the inputs of a fourth OR gate, whose output is connected to the first

5 to the input of the sixth element And, the bit outputs of the distributor from the thirteenth to the fifteenth are connected to the inputs of the fifth OR element, the output of which is connected to the first input of the seventh element And, the sixteenth bit output of the distributor is connected to the first input of the first element And, the second input of which is connected to the input information bus of the device and to the second inputs of the fourth, fifth, sixth and seventh elements And, as well as the eighth element And, the first input of which is connected to the second control bus of the device and through the second the element is NOT with the first input of the ninth element AND, characterized in that, in order to improve speed, a multiplication unit is inserted into it,

0 an additional OR element, additional adders and additional delay elements, while the output of the fourth AND element is through nine additional extra delay elements connected to the first input of the first additional adder, the output of which is connected to the second inputs of the eighth and ninth elements AND, the output of the fifth element AND through the first six-stroke additional delay element is connected to the first input of the second additional adder, the output of which is connected to the first input of the third additional totalizer Pa and through the first push-pull additional delay element with the second input of the third additional adder, the output of which is connected to the second input of the first additional adder, the output of the sixth element And through the three-stroke additional, delay element connected to the first input of the fourth additional adder, the output of which is connected to the first input addition adder and through the second push-pull additional delay element - to the second input of the fifth addition of the accumulator adder whose output is Connected with the second input of the second additional adder, the output of the seventh element And connected to the first input of the sixth additional adder and through the third push-pull additional delay element with the second input of the sixth additional adder, the output of which is connected to the second input of the fourth additional adder, the output of the ninth element And through the second a six-stroke additional delay element is connected to the first input of an additional OR element, the second input of which is connected to Exit eighth AND gate, the output of an additional OR gate connected to the second inputs of the second and third elements, and /

Sources of information taken into account in the examination

1.Kartsev M.A. Arithmetic of digital machines. M., “Science, 1969, p. 543, fig. 5-7.

2. USSR author's certificate number 269598, cl. G 06 F 5/02, 28.03.69.

3. USSR author's certificate

No. 404077, cl. G 06 F 5/02, 07.10.71 (prototype).

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Claims (1)

Claim A device for converting binary decimal numbers to binary, containing a distributor, the information input of which is connected to the first control bus of the device, the installation input is to the reset bus of the device and the zero input of the trigger, a single input of which is connected to the output of the first element And, and a single output to the first input of the second AND element and through the first element NOT to the first input of the third AND element, the output of which is connected to the first input of the first OR element, the output of which is connected to the output bus of the device, and the second input is to the output of the adder and the input of the delay element, the output of which is connected to the first input of the adder, the second input of which is connected to the output of the second AND element, while the discharge outputs of the distributor from the first to the fourth are connected to the inputs of the second OR element, the output of which is connected to the first input of the fourth AND element, the bit outputs of the distributor from the fifth to the eighth are connected to the inputs of the third OR element, the output of which is connected to the first input of the fifth AND element, the bit outputs of the distributor from the ninth twelfth connected to the inputs of the fourth OR element, the output of which is connected to the first input of the sixth AND element, the bit outputs of the distributor from the thirteenth to the fifteenth are connected to the inputs of the fifth OR element, the output of which is connected to the first input of the seventh element AND, the sixteenth bit output of the distributor is connected to the first the input of the first element And, the second input of which is connected to the input information bus of the device and to the second inputs of the fourth, fifth, sixth and seventh elements of And, as well as the eighth ele ment And, the first input of which is connected to the second control bus of the device and through the second element NOT to the first input of the ninth element And, characterized in that, in order to improve performance, a multiplication block, an additional OR element, additional adders and additional delay elements are introduced into it wherein the output of the fourth element And through a nine-stroke additional delay element is connected to the first input of the first additional adder, the output of which is connected to the second inputs of the eighth and ninth elements And , the output of the fifth element And through the first six-stroke additional delay element is connected to the first input of the second additional adder, the output of which is connected to the first input of the third additional adder and through the first push-pull additional delay element with the second input of the third additional adder, the output of which is connected κρ to the second input of the first additional the adder, the output of the sixth element And through a three-stroke additional delay element is connected to the first input of the fourth additional adder whose output is connected to the first input of the fifth additional adder and through the second push-pull additional delay element to the second input of the fifth additional adder whose output is connected to the second input of the second additional adder, the output of the seventh element And is connected to the first input of the sixth additional adder and through the third push-pull additional delay element with the second input of the sixth additional 10 adder, the output of which is connected to the second input of the fourth additional body adder, the output of the ninth AND element through the second six-stroke additional delay element is connected to the first input of the additional OR element, the second input of which through the multiplication unit is connected to the output of the eighth AND element, while the output of the additional OR element is connected to the second inputs of the second and third AND elements . '