SU1437857A1 - Device for dividing binary numbers in auxiliary code - Google Patents

Abstract

The invention relates to the field of computing and can be used in arithmetic devices. The aim of the invention is to reduce hardware costs. The goal is achieved due to the new organization of links in the device for dividing binary numbers in an additional code containing registers 1 and 2 of the dividend, respectively, of the junior and senior formats, register 3 of the divisor, adder-subtractor 4, circuit 5 of the comparison. 1 il.

Description

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The invention relates to digital computing and can be used in arithmetic, where. preparation of the divisible and divisor operands is carried out in binary and single formats, respectively.

The aim of the invention is to reduce hardware costs,

The drawing shows a diagram of a device for dividing binary numbers in an additional code,

The device contains a register of a divisible junior format, a register 2 of a divisible senior format, a register 3 divider, adder-subtractor A, a comparison circuit 5, an input 6 of the divisible device, an input 7 of a device divider, an output 8 of a particular device, a clock input 9 of the device, an input 10 device sync, input I1 of the initial device setup.

The device for dividing binary numbers in the additional code works in the following way.

Before commencing the computation, the register 1 of the dividend junior format, the register 2 of the dividend major format and the register 3 of the divider are transferred to the parallel recording mode from the inputs 6.7 of the dividend and the divider. The dividend is a double-format operand that contains the highest part of the same bit size. The divider is a positive operand of a single format, equal in the number of bits to the format of the highest part of the dividend. The absolute value of the dividend is less than the absolute value of the divisor. The divider is normalized.

From the output of the register 2 divisible high format, the high part of the dividend in parallel enters the first input of the adder-subtractor 4, the second input of which simultaneously receives the divider from the output of the register 3 divider. From the outputs of the sign bits of the register 3, the dividers and the register 2 of the divisible older format, the informals arrive at the first and second inputs, respectively, of the comparison circuit 5, at the outputs Equal To Not Equal which generate signals to the control 5e inputs of the adder-subtractor 4. At the exit Equal comparison circuit 5 is formed by the sign bit private and is fed to the input of the lower bit of register 1 of the dividend

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junior format. At the output of the adder-subtractor 4, a first residue is formed, which in parallel arrives at the second information input of the register 2 of the divisible higher format with a shift by one bit in the direction of the older one. Then, all registers are transferred to a mode that implements a computational cycle, namely: register 1 of a divisible format — to sequential shift of information towards the higher order, register 2 of a divisible higher format is switched to receive residuals from its second information input and input to the low-order bit of information received from the first low-format register; the divider-3 register is switched to the storage mode. According to the following sync syntax, the first remainder is written B register 2 of the divisible senior format with a shift of one bit to the side of the senior one. From the register i of the dividend L of the next format into the {- (the best bit of the register of the second dividend format is recorded in the next digit of the dividend number, and in the freed) the best bit of the register I of the dividend junior format is inserted into the private sign. The comparison circuit 5 receives the sign of the next residue, as a result of which the next digit of the quotient and the operation code of adder-subtractor 4 are formed, the output of which is followed by the following DU10Shl1Y residue. According to the next synchrotact, the obtained remainder is written into register 2 of the divisible senior format, at the least significant bit of which the next digit of the divisible digit is moved, and the second bit of the private digit of the 5 comparison is shifted into the minor bit of register 1 of the divisible junior format. These operations are repeated throughout the entire computational cycle. The duration of the computational cycle is determined by the resolution of register 1 of the dividend junior format. After all bits of the lower part of the dividend are sequentially rewritten into register 2 of the dividend older format, and register 1 of the dividend dead format is filled with the private one, which arrives at output 8 of the device, the calculation process ends, register 1 of the dividend mpadg format, divide register 2. the older format and the 3 register divider are switched to parallel recording mode from inputs 6 and 7 of the device.

Claims (1)

Invention Formula A device for dividing binary numbers in an additional code, containing a register of a divisible junior format, a register of a divisible senior format, a divider register, a calculator adder and a comparison circuit, the divider input of the device connected to the divider register information input, the synchronization input of which is connected to the synchronization inputs the registers of the divisible junior and senior formats and the synchronization input of the device, the initial installation input of which is connected to the resolution enable inputs of the register divider and the register It has a junior format, with the first input of the receive resolution of a register of a divisible senior format, the inputs of the higher and lower bits of the input of a divisible device are connected respectively to the inputs of the bits of the first information input. A register of a divisible senior format and with the inputs of the information input bits of the register the sign bits of the register de the register and the divisible high format are connected respectively to the first and second inputs of the comparison circuit, the outputs Equal To and Not equal to which are connected respectively to the resolution inputs of the subtraction and addition of the adder-subtractor, the output of which is connected with the shift by one bit in the direction of the high bits to the second the information input of the register of the dividend high format, the second input of the reception resolution of which is connected to the clock input of the device, the outputs of the register of the high divide format and the register of the divisor of the connector correspond It is valid with the first and second information inputs of the totalizer-subtractor, characterized in that, in order to reduce hardware costs, the output Equals cxeNbi comparison is connected to the low-resolution input of the divisible low-format register, the output of the lower and the high-low output of which are connected respectively to the output private device and with the input of the least significant bit of the register of the dividend high format, the clock input of the device is connected to the input of the allowable shift of the register of the dividend low format.