SU691891A1 - Frequency-pulse differentiator - Google Patents

Description

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The invention relates to the field of automation and computational techniques and can be used in information and measurement and control systems for the formation of a 41M pulse signal in the form of a digital derivative code.

A 1-J frequency-differentiating device is known, which contains a cube-raising unit, a periobot difference difference unit, an AND pattern and a result counter.

The disadvantage of such a device is the low precision of differentiation of the signal.

It is also known a differentiating device 2 comprising a control unit, a reference frequency generator, controlled frequency dividers, an uncontrolled frequency divider, a period counter, a group of 9Lb (1ent I, a result counter and a period increment block.

A disadvantage of this device is reduced speed.

The closest to this inventor is the pulse-differentiating pulse ybtpOftCTBo 3; containing a reference frequency generator connected by an output to the input of a frequency divider and to the counting input of the first counter connected by bit inputs to the outputs of snoMeHiPOB And the first group connected first: and inputs to the output of the first counter and counting input of the second counter connected by bit inputs to the element outputs And the groups connected by the first inputs to the output of the second counter, the counting input of the third counter, connected by bits. input and with the outputs of the elements of the third group and the counting input of the fourth counter connected by bit inputs to the outputs of the elements of the fourth group connected by the first inputs to the output of the fourth counter, the output of the third counter The second inputs of which 3 are connected to the second inputs of the elements of the first and second groups and to the bit outputs of the fifth counter connected by a counting input to the output of the TS1TA hour divider, and the bit outputs of the sixth counter are connected to the first inputs of elements of the fifth group connected by outputs to the bit inputs of the reversible counter of the result, the bit outputs of which are connected to the first inputs of the elements of the sixth group, and the main inputs of the first, second, third, fourth and fifth counters the second inputs of the elements i the fifth and the neck, the groups and the input of the zero frequency divider, the reversible result counter and the sixth counter are connected to the corresponding outputs of the control unit connected by the input to the input bus of the device, the disadvantage of this device is a with constructive complexity implementation lowering reliability and not both pechivayuscha vfavnivanie proportionality coefficients constituting the code in the counter result. The aim of the invention is to simplify the device. This is achieved by the fact that a decoder, memory register, an additional group of elements AND, an additional frequency divider, two triggers and three elements AND connected with the first inputs to the output of the first trigger connected by the first input to the output of the decoder, are entered into the device inputs to the bit outputs of the fifth counter and to the first inputs of the elements AND of an additional group, the outputs of which are connected through the memory register to the second inputs of the elements AND of the fourth group connected by the first inputs to the counting the second input is three heres connected by an output to the second input of the first element I, the output of which is connected to the summing input of a reversible counter for the result connected by a subtracting input to the output of the second element I connected to the third input of which is connected via an additional the frequency divider to the second input of the third element is And is comno; the output is from the counting input of the sixth counter, with the second inputs of the elements of the additional group, the second input of the first trigger and inputs about Zero memory register and additional OJ4 frequency divider gtodypocheggy to the corresponding outputs of the control unit. The drawing shows a block diagram of the proposed device, which contains a reference frequency generator I, input bus 2, first 3, second 4 and third 5 counters, reversible counter 6 of the result, frequency divider, first 8, second 9 and third 10 groups of elements And . Fourth 11, fifth 12 and sixth 13 counters, memory register 14, additional frequency divider 15, decoder 16, fourth 17, fifth 18 and sixth 19 groups of And elements, additional group of 20 And elements, first 21 and second 22 triggers, the first 23, the second 24 and the third 25 elements And, the control unit 26, 27 35- &bgr; inputs of the control unit. The output of the generator 1. is connected to the counting input of the counter 3. The output of the counter 3 is connected to the counting input of the counter 4 and connected to the first inputs of elements AND of the first group 8, the outputs of which are connected to the serial inputs of the counter 3. The output of the counter 4 is connected to the counting inputs of counters 5 and 11 , the input of the frequency divider 15 and the first inputs of the elements AND the second group 9, the outputs of which are connected to the serial inputs of counter 4. The output of the counter 11 is connected to the first inputs of the elements AND of the fourth group 17 connected by outputs to the bit inputs of the counter 11 and connected to the counting input of the trigger 22. The first inputs of the elements AND of group 17 are connected via memory register 14 to the outputs of the elements AND of the additional group 20, the first inputs of which are connected to the bit specific outputs of the counter 12 and the inputs of the decoder 16, the output of which is connected to the first input trigger 21. The output of the trigger 21 is connected to the first inputs of the And 23 24, 25 elements. The second input of the And 24 element connected to the output from the subtractive input of the reversible counter of result 6 is connected to the output of the counter 5 and the first inputs of the And elements of the third group 10. B The left inputs of elements And groups 8, 9, 1O are connected to the serial outputs of counter 12. The output of frequency divider 15 is connected to the second input of And 23, which is connected to the output from - to the counting input of counter 13, whose bit outputs are connected to the first inputs of elements And The fifth group 18, connected by outputs to the serial inputs of a reversible counter 6, connected by a summing input to the output of the element I 25, the second input of which is connected to the output of the trigger 22, and connected by bit outputs to the first inputs of the elements And the sixth group s 19. The outputs of the elements And group 19 are connected js the output bus device. The outputs of the control unit 26f connected by the input to the input bus AND device are connected as follows: output 27 to the second input of the trigger 21, output 28 to the second inputs of elements AND of group 19, output 29 to the zeroing input of the reversible counter 6, output 30 to the second inputs of elements AND of group 18, output 31 to the input of zeroing counter 13, output 32 to input of zeroing of memory register 14, output 33 to the second inputs of elements AND of group 20, output 34 to the mounting input of counter 11, exit 35 - to installation 1 inputs of counters 3, 4, 5, 12 and inputs of zeroing frequency dividers 7 and 15. The device operates as follows. ; - ..- ;. ; After each pulse of the input frequency arrives in the control unit 26, signals are generated that sequentially on output 27 set trigger 21 to the position covering AND 23, 24, 25, output 28 open group of elements AND 19 and the result code from counter 6 is transmitted to input devices. Then the counter 6 is outputted by the output 29 signal ji into it through a group of elements -I16, which is output from the output 30, entered the code from counter 13, after which the counter 13 is zeroed by the output 31 of the control unit. Then the rip Bbixo signal 32 and 32 memory register 14 and into it through a group of elements And 20, opened with a signal from output 33, the code from counter 12 is entered. After that, in the counter 11 signalbm on output 34 of the control unit, the return code of the unit ( 2-1, where n is the number of bits of the counter). Output signal 35 zeroes dividers 7, 15, a unit code is set in counter 12, and in counters 3, 4, 5 a reverse unit code is set. After that, high-frequency pulses {from output 1 of generator 1, which passed through frequency divider 7 with a division factor K, are sent to the woode of counter 12, where they are summed up in the time intervals between input signals

Claims (3)

691891 pulses equal to the current periods of the T-input frequency 1,. At the end of each period of the input frequency, a code is formed in the counter 12, which is proportional to the terminating period tg-T; This code, before setting the counter 12 to its initial position, overwrites the AND 20 into the previously cleared memory register 14, where it is stored until the end of the next period The first frequency pulse {p causes overflow of counters 3, 4, 5, the output pulses of which through the corresponding groups of elements 8, 9, 10 rewrite the current code of counter 12 into these counters 3, 4, 5. During subsequent overflows of counters 3, 4 , 5 this process is repeated. At the output of counter 3, the frequency f is generated. K CH T 1 -. inversely proportional to time t; past from the beginning of the current period. At the output of counter 4, the frequency J Vii is formed, inversely proportional to the square of the time t; . At the output of counter 5, the frequency f is inversely proportional to the cube of time. The frequency pulses In from the output of counter 4 through the frequency divider 15 with the division factor K, v proportional to the minimum period T j of the input frequency, arrive through the element 23 and the input of the counter 13, where these pulses are summed over the time for which the element 23 is opened. The pulses from the output of counter 4 are also fed to the input of counter 11, which, together with memory register 14 and group of elements And 17, forms a control frequency divider with a division factor Equal to the code in register 14 and proportional to the terminating period of the input frequency. Frequency {. at the output of counter 11 is equal to the pulses of frequency i, using trigger 22, the pa and the output frequency i of this trigger are transmitted through the element 25 to the summing input of the reversible counter of result 6, to the subtracting input of which the pulses arrive at the frequency trj from the output of the counter 5. Elements 23-25 open-s for a time interval equal to the difference (T, - -) between the current and minimum period of the input frequency. This interval is formed by means of a trigger 21, which is set to the position at which the elements 23 23 are opened. , in the moment The time code in counter 1.2 reaches the value: MT. -. t, pip K mm) and returns to its original position by signal 27 of the control unit at the end of the current period and the arrival of the next impulse of the input frequency. The flip-flop 21 is turned on when the counter 21 value of the NT code is reached, decryptor 16. / During the time of the previous period, TV, the counter 12 generates a code proportional to this period, which is rewritten into register 14. T, - T 1 in the counter 13 the code N is formed; U / .... , . , B, :. ,: .4 Wfmdx- J; , maKv-mnv / mio -о which is proportional to the Product; .. the maximum frequency imnu of the input impedance. difference between the maximum and instantaneous current value of the input frequency corresponding to the previous period. After the end of the preceding period, this NI code is rewritten through a group of elements AND 18 into a reversible counter 6, in which during the interval T -Tg) equal to the difference between the subsequent Tji and the minimum period of the input frequency, the code will be subtracted from N, the frequency pulses f and summation of frequency pulses. At the end of the subsequent period, the output code Njbix (f, -i,) imtm n ° 1 will be generated in the reversible result counter, which is proportional to the time derivative of the input pulse frequency. signal. When the sign of the derivative changes, the code in counter 6 decreases to zero and changes its sign. In this case, the trigger of the counter 6 sign (not shown in the drawing) is triggered, which changes the counting direction of the pulses in the counter to the opposite and gives a minus sign to the device output. When this happens, the frequency pulses 1 begin to sum, and the frequencies it are subtracted. Simultaneously with the formation of the code in the result counter 6, in the counter 12 a code K is formed proportional to the current nepHoliy Tt in the counter 13 code / proportional to the product of the maximum frequency and the difference between the maximum and the corresponding current. period tj. Thus, after the end of period 7, the device is ready to form a new code value in the counter of result 6, which will occur in the subsequent period. The proposed device, due to the combination of a series of operations, does not use, unlike the prototype, an instantaneous frequency meter, a measurement unit of the periodic period and a unit for forming a minimum period in the control unit; This leads to a simplification of the constructive implementation of the pulse frequency differentiating device. In particular, the proposed device uses 10 pulse counters instead of 17 counters in the prototype. The invention is a pulse-frequency differentiating device comprising a reference frequency generator connected by an output to an input of a frequency divider and to a counting input of a first counter connected by discharge inputs to an output of AND elements of the first group connected by first inputs to an output of a first counter and a counting input of a second counter, connected by bit inputs with outputs of elements AND of the second group, connected by the first inputs to the output of the second counter, the counting input of the third counter, connected by bit inputs with the outputs of elements of the third group and the counting input of the fourth counter connected by the bit inputs of the elements of the fourth group connected by the first inputs to the output of the fourth counter, the output of the third counter connected to the first inputs of the elements of the third group, the second inputs of which are connected to the second the inputs of the elements of the first and second groups and to the bit inputs of the counter counter connected to the output of the frequency divider by a counting input, the bit outputs of the sixth counter being connected to the first inputs of the element Ntov And a group of gangs, connected by inputs to the rand inputs of the reversible counter of the result, the bit outputs of which are connected to the nepBbiM in the previous epemento and the shears. of the group, and the resilience is taken by the yerog, the second, the third (b), and the second counting | vtryo inputs g ontov fifth AND "g and sixth groups bevdyy obnu fines -delitvy astygy (YYy (16: / pedynbTiaTa counter and ygostbg ChoTchyya compound with rho uG1№tstyutoy (ishBfe | control unit; I№tWYyu №nyoi o B to input device, from ji and h yuyo with tech, oh, with til) simplify the device, in it, enter detour, {zygystry yamytyy, dopi1; "; n on a group of elemetr And, additional frequency divider, Two Trigger and three elements AND, under the Definition nejpBbiMk Inputs to the output of the first trigger connected by the first input to the Output of the controller connected to the VHB To the first inputs of the additional group I, the outputs of which are connected through the i register of the memory to the second inputs of the elements of the fourth group connected by the first inputs with the counting input of the second trigger connected by the output to the second input of the first element And, the output of which is connected to the summing input of the reversible counter of the result connected by the subtractive input to the output of the second element And connected to the output of the third counter, the counting input of which is connected h (v1zee additional divisor part5toto BTOjpoMy to beat up the third element AND, connect with each other from the additional group, the second input is nejiBoro and trashtera. Vyodt bb upyy memory and dopy | ti11glyy) d & pitep: subcategories to cooTBe | citByiotmiiMi vyddy blokynpaBjieisHe:, ... --- f.-1-: i andfor taken at heading (9), in a pass (d), in a pass (pass rate 16), put a pass rate of 10 yr. No. 399S60, CL G 06F 7/38, 1971. 2. For the number 2395060/24, cl, in About E Z / RB, 19716, according to which the decision on the Shdachyu copyright certificate, 3. Forms M 2119484/24, cl, G 0667/18, 1975, according to which a decision was made on the copyright certificate.