SU619918A1 - Multichannel device for interfacing users with digital computer - Google Patents

Description

combo and channels, with the second inputs of the second elements of the channels, with the installation input of the shift register and with the first input of the input element I, (the second input of which is connected to the input of the device, with the serial inputs of the working channel registers and with the input of the control unit, the outputs of the first element I the channel, the channel element and the second channel element AND are connected respectively to the first, second control inputs and the clock input of the working channel register; the serial output of the working channel register is connected to the second input third AND m channel outputs of the AND third channels through an OR gate connected to the output device, and The discharge shift register outputs are connected to the inputs of the decoder.

The block diagram of the device is shown in the drawing.

A multichannel device for interfacing subscribers with a digital computer contains an input element AND 1, a shift register 2, a decoder 3, an OR element 4, a control unit 5, channels 6-8, each of which contains a working register 9, first, second and the third elements AND 1012, which is NOT 13. The device also has an output 14 and an input 15. The positions 16–23 denote the sequential, clock and setup inputs of the shift register, the first, second control, clock, sequential input and output of the working channel register, respectively. , outputs and control unit input, 24-28 - outputs b eye 5 controlling.

The device works as follows.

Each parcel of a digital computer consists of a two-hour-address-and informational one and comes in the form of a serial codegram in a sequential code, arriving at input 15 and further to the inputs of the control unit 5, element 1 and registers 9. Unit 5 outputs from output 24 , ensuring the passage of sequential code through the element. And 1 at the entrance. shift register 2. Simultaneously, pulses are received from output 25, which receive a posting code in shift register 2, at the end of the address part of the message, control unit 5 stops outputting signals from output 24 to output 25. At the same time, in accordance with the received register Shift 2 with the address code appears on one of the outputs of the decoder 3, which prepares the elements AND 10, 11, 1.2 of one of the channels 68 associated with the register 9 of the corresponding channel. The address of register 9 is specified in shift register 2 to pass a sequential response code, write signals, and clock signals.

At the same time on the v. 19 register. 9 of the triggered channel, a signal appears, deactivating the register 9 of this channel from the co-receiver receiver. At the beginning of the information part of the parcel from exit 27

the control unit 5 outputs a write signal and the information from the source subscriber is recorded in parallel code in the register 9 of the selected channel. Further, on arrival of the serial code of the output 28 of the control unit 5, the sync signals are issued, which ensures the reception of the next code of the keyboard, the active part of the package to the specified register 9. Since the response code is written in 14), simultaneously with the reception of each bit of information from the register 9 of the selected channel, issuance through the elements AND 12 and OR 4 bits of the reply parcel. A sequential response code from the subscriber source informedia arrives at the output 14 of the device. At the end of the reception of information in the register 9c of the output 26 of the control unit 5, a signal is issued, according to which

shift register 2 is zeroed, the C11 signal is removed from the output of the decoder 3, and track 3 of the parallel code enters the corresponding GB; the most recent receiver subscriber. At the same time, the transmission of a sequential response code is terminated.

The Ugflenk B block stops issuing uprashshk cich signals from its outputs.

The proposed device involves

increase the speed, as 1, it provided a combination of receiving and transmitting information.

Claims (2)

1. USSR author's certificate N9 504199, c. 06 G 3/04, 1974. 2. USSR Author's Certificate No. 437О64, cl. G, 06 F C / PA, 1972.