SU982000A1 - N-channel adding device - Google Patents

Description

The invention relates to a computer and computing technique and can be used in the construction of frequency signal processing devices.

A device for summing the frequencies of pulsed signals is known, comprising a pulse frequency generator, a trigger and AND, OR,

NOT

 The disadvantage of this device is a small frequency range.

The closest to the invention is an N-channel summation device. Frequencies containing N lock blocks, each of which includes an RS flip-flop, the unit setup input is the first input of the lock block and the information input of the forward output device. connected to the first input of the AND element, the second input of which is the second input of the anchor block, and the output - the output of the anchor block, an N-phase short pulse generator, an OR element and an output frequency divider, where the outputs of the N-phase short pulse generator are Dineny, respectively, with the second input1 "blocks of binding, the output element OR

connected to the counting input of the output frequency divider, the output of which is the output of the device G2.

The disadvantage of this device is its small functionality, which allows only proportional summation of input frequencies.

The purpose of the invention is the expansion

10 functionality of the device by allocating the disproportionate summation of frequencies AND summation without reducing the frequency of the resulting signal.

ts

 The goal is achieved by the fact that in each block of the binding of an N-channel summation device containing N blocks of binding, each of which includes an RS flip-flop, an input

The installation unit 20 of which is the first input of the anchor block and the information input of the device, the direct output is connected to the first input of the AND element, the second input of which

25 is the second input of the anchor block, and the output is the output of the anchor block, an N-phase short pulse generator, an OR element and an output frequency divider, with the outputs of the N-phase 30 short pulse generator connected to the second inputs of the tether blocks, the output of the OR element is connected to the counting input of the output frequency divider, the output of which is the output of the device | .., e ,, prices controlled divider register, the outputs of which are connected respectively to the installation inputs of the controlled frequency divider, the register write enable input is the third input, and the installation inputs are the installation inputs of the anchor block, the output of the controlled frequency divider is connected to the setting input to zero is the RS trigger, and the counting input of the controlled frequency divider is connected to the output of the AND element, in addition, N + 1 AND elements are entered into the device, the mode register, and the operation and the division ratio register of the output signal, when The setting inputs of the mode register are the mode inputs of the device, the input of the shift pulses of the mode register is connected to the combined first inputs N + 1 of the AND elements and is the first control input of the device, the record resolution enable input is the second control The device’s input, the outputs of the mode register are connected respectively to the second inputs N + 1 elements AND, the outputs N of elements AND are connected respectively to the third inputs N of the binding blocks, the output (N + 1) of the And element connected with the enable entry of the register of the division of the output signal. The outputs of which are connected to the installation inputs of the output frequency divider, and the installation inputs are inputs of the coefficient setting, the division is the output signal of the device, the outputs of the lock blocks are connected respectively to the inputs of the OR element, the output of which is the second output of the device. The drawing shows a structural diagram of an N-channel summation device. The device contains inputs 1-1 .... 1-N operation mode settings, first and second control inputs 2,3, setting inputs 4-1 ... 4-N + 1, information inputs 5-1 ... 5-N, generator of 6 short pulses, register 7 working modes, elements AND 8-1 ... 8-N + 1, tie-in blocks 9-1 .. 9-N, which include RS-three heras 10-1-1 ... 10- N-1, elements And 11-1-2 ... 11-N-2, controlled dividers 12-1-3 ... 12-N-3 frequencies, registers 13-1-4 ... 13- N-4, element OR 14, register 15 of the output signal division factor, output frequency divider 16, first and second 17, 18. device outputs, the information inputs 5-1, ... 5-N of the device, respectively, being connected with the inputs of the installation of the NN-triggers 10-1-1 ... 10-N-1 of the anchor blocks, the forward outputs of which are respectively connected to the first inputs of the And 11-1-2 ... 11-N-2 elements, the second inputs of the elements 11-1-2 ... 11-N-2, respectively, are connected to the outputs of the N-phase generator b of short pulses; the outputs of the controlled dividers 12-1-3 ... 12-N-3 frequencies, respectively, are connected to inputs set-. ki to zero RS-flip-flops 10-1-1 ... 10-N-1, the counting inputs of the controlled dividers 12-1-3-12-N-3 frequency, respectively, are connected to the outputs of the elements And 11-1-2-11 -N-2 and with the inputs of the element OR 10, the installation inputs of the controlled dividers 12-1-3-12-N-3 frequencies, respectively, are connected to the outputs of the registers 13-1-4-13-N-4, the write enable inputs of which are respectively connected to the outputs of the elements And BT-lBN, and the installation inputs are respectively connected to the installation inputs 4-1-4-N of the device, the first inputs of the elements And 8-1-8-N + 1 are combined and connected to the first control input 2 the device and the shift pulse input of the register 7 of the operation mode, and the second inputs are respectively connected to the outputs of the operation mode register 7, the recording enable input of which is connected to the second control input 3 of the device, and the setup inputs to the inputs 1-1 ... 1- N specifies the mode of operation, the output of the I8-H + 1 element is connected to the write enable input of the register 11 of the output signal dividing ratio, the setup inputs of which are respectively connected to the 4-N + 1 setup inputs, and the outputs - to the setup inputs of the output splitter 12, the output of which is connected to the first output 13 of the device, and the counting input is connected to the output of the element OR 10 and to the second output 14 of the device. The device works as follows. At the inputs 1-1-1-N of the setting of the operation mode, a code 100..0 is applied, which with the arrival of a pulse to the second control input 3 is written to the operation mode register 7, which ensures the passage of recording pulses from the first control input 2 through the AND element 8-1 to the input of the register entry 13-1-4 resolution of the first anchor block 9-1. Then, an operation mode code is set at the inputs 1-1-1-N of the setting of the operating mode, after which a write pulse is applied to the first control input 2 of the device.

which permits the impulse to write the operating mode code on the first channel through the AND 8-1 element, writes the operation mode code to the register 13-1-4 and shifts the information in the operating mode register 7 by one; unit to the right, preparing the device to record the mode code work on the second channel.

Similarly, the codes are recorded in the subsequent registers up to the N-ro channel. After that, in register 7 of the operation mode, a code 00 ... 01 is set, which ensures the passage of a write pulse to the write enable input of the register 11 of the output division factor. With the filing of the last recording pulse, the device is ready for summation or corresponding signal transmission with. inputs 5-1-5-N to outputs 13 and 14.

To the inputs 5-1-5-N of the device, either sequences of short pulses with different repetition frequencies or number-pulse codes are applied. N-phase generator b produces N sequences of pulses that do not coincide in phase. The frequency of the clock pulses must be greater than the maximum frequency of the pulses applied to the inputs 5-1-5-N. From the outputs of registers 13-1-4-13-N-4 and register 15 to the installation inputs of controlled dividers 12-1-3-12-N-3 frequencies and output frequency dividers 16, the codes of operation modes, previously recorded in the corresponding registers, are supplied . This provides the possibility of changing the division factors of the controlled dividers 12-1-3-12-N-3 frequencies and the output divider 16 frequencies from

 1 to KvrtOXK

MiH

With the arrival of each pulse at the inputs 5-1-5-N, the RS-flip-flops 10-1-1-10-N-1 are set to one, which allows the passage of a pulse from the output of the N-phase generator 6 to the output of the AND 11- elements 1-2-11-N-2, and, when the division factor of the dividers 12-1-3-12-N-3 is equal to one, the first impulse from the output of the And 11-1-2-11-N-2 elements is set RS-flip-flops to zero, -WHR prepares the device to receive subsequent-pulses from inputs 5-1 ... 5-N. Thus, at the outputs of the AND 11-1-2-HN-2 elements, pulse sequences with frequencies equal to the frequencies of the corresponding input signals that do not coincide in time are allocated to the element OR 14, at output 18 of which an uneven pulse sequence is selected. with medium

a frequency equal to the sum of the frequencies of the input signals, or the sum of the parcels, the number of impulse codes fed to the inputs 5-1 ... 5-N of the device. Due to the fact that the pulses at the output 18 of the device are rigidly connected in time to the pulses coming from the generator output 6 of the N-phase pulses of the device, the sequence of pulses at the output of the device iS

0 can be decoded in. therefore, this device can be used to transmit N frequency signals or number-pulse codes one at a time

5 communication channel.

By setting the appropriate division factor of the output frequency divider 16, which is used as a normalizer for the unequalness of the sequence of pulses fed to its input, the sequence of pulses at the output of the OR 14 element can be normalized, i.e. irregularity of pulses can be eliminated. At the same time, at the output 13 of the device, a uniform sequence of pulses is allocated with a frequency equal to the sum of the input frequencies, decreasing in Kg

0 times.

i + fa. +. . . + fN

(one)

v1x

s

. , ... f - input frequencies

f

where f

5 signals;

K - coefficient of the Research Institute of the output frequency divider.

In order to obtain the unreduced sum of the input frequencies at the output 13 of the device, it is possible to write to the registers 13-1-4-13-W-4 codes corresponding to setting such dividers divisors 12-1-4-12-N-4,

5 at each input pulse output element And 11-1-2-11-N-2

times more pulses

allocated to

6 owls, i.e.

(2)

 TO.

M.

M.

ftx

0

where M is the number of pulses at the output

output elements And 11-1-4-11-N-4;

- number of pulses per comp.

The corresponding input is device5. properties.

In this case, the output of the element OR 10 is a sequence of pulses, the number of which

Kvyh-x;

0

, M - the number of pulses

Where

at the output of the element OR 14 or at the output 18 of the device;

Claims (1)

SUMMARY OF THE INVENTION N-channel summing device containing N binding units, each of which includes an RS trigger, the unit input of which is the first input of the binding unit and the information input of the device, the direct output of the RS trigger is connected to the first input of the And element, the second input which is the second input of the block, and the output is the output of the binding block, N-phase short pulse generator, OR element and output frequency divider, the outputs of the N-phase short pulse generator being connected respectively respectively, with the second inputs of the binding blocks, the output of the OR element is connected to the counting input of the output frequency divider, the output of which is the output of the device, characterized in that, in order to expand the functionality by introducing disproportionate summation of frequencies and summing without lowering the frequency of the resulting signal, each binding unit has a controlled frequency divider and a register, the outputs of which are connected respectively to the installation inputs of the controlled frequency divider, the input is register writing decisions is the third input, and the installation inputs are the installation inputs of the binding unit, the output of the controlled frequency divider is connected to the installation input to zero RS trigger, and the counted input of the controlled divider, frequency is connected to the output of the And element, in addition, N + 1 is introduced into the device elements And, the operating mode register and the coefficient register. dividing the output signal, and the installation inputs of the operating mode register are inputs of the operating mode of the device, the input of the shift pulses of the operating mode register is connected to the combined first inputs of N + 1 elements And is the first control input of the device, the write enable input of the operating mode register is the second control input of the device , the outputs of the operating mode register are connected respectively to the second inputs of N + 1 AND elements, the outputs of the N elements AND are connected respectively to the third inputs of N anchor blocks, outputs d (N + l) -ro AND gate connected to the input write enable signal output division factor register ¹ outputs of which are respectively connected to the output of the frequency divider inputs mounting and adjusting inputs are vhodayi coefficient setting division output sig 'Nala device outputs blocks. the bindings are connected respectively to the inputs of the OR element, the output of which is the second output of the device.