SU470826A1 - Probabilistic device for dividing two numbers - Google Patents

Description

The functional diagram of the probabilistic device for dividing two numbers is shown in the drawing.

The probability device for dividing two numbers consists of division block 1, two inputs of which are connected respectively to the outputs of two elements "AND 2 and 3, element" NOT 4, the output of which is connected to the first inputs of elements "And 2 and 3, element" And 5 with a polling input 6, registers 7 and 8 with a shift bus 9, the bit outputs of which are connected to the inputs of the comparison circuits 10-12, respectively, the output of which is connected to the input element "NOT and to the second input element" And 5, the output of which is connected through the element delays 13 with a shift bus 9 register 8 and with the input of and a reverse binary counter 14, the unit outputs of bits are connected to the inputs of the element OR 15. The output of this element is connected to the first input of the element “AND 16, to the second input of which the interrogation bus 6 is connected, and with the input of the element“ NOT 17, the output of which connected to the zero input of the trigger 18, the control input 19 is connected to the unit input. The output of the trigger 18 is connected to the third input of the element “AND 16”, the output of which is connected via the delay element 20 to the subtraction input of the reversible counter 14 and directly to the bus offset and 21 of the reversible counter 22, the unit outputs of which bits, with the exception of additional ones, are connected to the inputs of comparison circuit 23. The output of the comparison circuit is connected to the first input of control unit 24, to the second input of which the output of division unit 1 is connected. Two outputs of control unit 24 are connected with two inputs of the reversible counter 22, respectively, and the outputs of the binary noise generator of the generator 25 random codes are connected to the inputs of the comparison circuits 10, 11 and 23, respectively.

The device works in the following way.

In register 7, the divisible code is set, and in register 8, the divisor code is set. Then, these two chips are compared in the comparison circuit 12. If the divider code is smaller than the dividend code, then the output of the comparison circuit 12 is the potential, the opening element is “And 5, and the clock pulse arriving at the input of the element“ And 5 via the interrogation bus 6 After passing through the delay element 13, it enters the shift bus 9 and shifts the contents of the register 8 towards the higher bit. In addition, this pulse is fed to the input of the reversible counter 14 and increases its content by one. Then again compares the codes of registers 7 and 8 on the comparison circuit 12 and, if there is a potential at its output, the register 8 is shifted again and the unit is added to the contents of the reversing counter 14 and so on until the divider code becomes more divisible code. This fact makes it known about the lack of potential at the output of the comparison circuit 12, which leads to the prohibition of the clock pulse through the element "And 5" and to the termination of the register 8 shifts. The potential, developed at the output of the element "HE 4, opens the elements" And 2 and 3 and allows passing to the inputs of the dividing unit 1 stochastic pulse sequences from the outputs of comparison circuits 10 and 11, which receive these sequences when comparing the binary code of registers 7 and 8 with independent sources of binary noise generator 25. The impulse and stochastic sequence from the output of divider 1 to the input node, consisting of control unit 24, a reversible binary counter 22 and comparator circuit 23, and after a certain number overshoot converted into down counter 22 into a binary code.

At the end of the calculation, the control pulse arrives through the bus 19 and transfers the trigger 18 to the state "1. If in the reversible counter 14 contains any

the code indicating the number of shifts done in register 8, then at the output of the element “OR 15 there will be a potential that, together with the potential at the single output of trigger 18, allows the passage of a clock pulse

from bus 6 through the element “AND 16 to the shear bus 21 of the reversible counter 22, as well as with a certain delay, provided by the delay element 20, to subtract a unit from the contents of the reversible counter 14. Shift

continues until the code in the counter 14 becomes zero. Thereafter, the potential at the output of the element "NOT 17 translates to the state" About the trigger 18. The contents of the counter 22 represent the binary code

the private, and in the additional higher bits, there is a whole part, and in the other bits, the mantissa of the private.

Thus, the device allows to obtain a result in the range of values (Q,),

where / g is the size of the registers of the dividend and divisor, provided that the dividend and divisor take values in the interval (0; 1), which completely covers the whole possible range of values accepted by the numbers represented as probabilities of impulses of stochastic pulse sequences .

Subject invention

A probability device for dividing two numbers containing a dividing unit, the output of which is connected to the first input of the control unit, the second input of which is connected to the output of the first comparison circuit, the first inputs of which are connected to the discharge outputs of the first reversible counter, respectively, and the second inputs with the first exits

random code generator, second outputs

which are connected to the first inputs of the second comparison circuit, respectively, and the third outputs to the first inputs of the third comparison circuit, the second inputs of the second and third comparison circuits are connected to the first outputs of the first and second registers, respectively, characterized in that, in order to expand the functionality of the device, it contains delay elements, elements "NOT the first and second elements" AND, the outputs of which are connected to the inputs of the division unit, the first inputs to the outputs of the second and third comparison circuit, respectively, Werth comparing circuit, the output of which through the first member "is NOT connected to the second inputs of the first and second elements" And, as inputs - to the second outputs of the first and second registers, respectively, and the third element "And, the second input of shift

register through the first delay element and the third element "And connected to the input of the first element" NOT, the second reversible counter, the summing input of which is connected

to the output of the first delay element, the OR element whose inputs are connected to the bit outputs of the second reversible counter, respectively, is a trigger whose first input through the second element is NOT connected to the output of the OR element, the fourth AND element, whose inputs are connected to the element outputs "OR and trigger and the second input of the third element" And, respectively, and the output through the second delay element - with the subtractive input of the second reversible counter and directly - with the shift input of the first reversible counter, the inputs to orogo connected to the outputs of the control unit respectively.