SU437231A1 - Pulse counting counter - Google Patents

Description

one

The invention relates to electronics, automation and computing.

In the known device | Be, which contains the source of the switch sequence, the character trigger, the synchronization unit, the phase difference converter, the counter-converter and the switch of discharges, it is necessary to have a generator of phase constants reversible, which complicates the circuit and reduces its reliability. In addition, the known device is characterized by the complexity of working with external devices and the need to have additional code converters for working with external devices, as well as the power of digital indicators with short pulses of 8-10 microseconds adversely affects the alignment of information signals with digital indicators and the durability of the indicators.

The proposed device, in order to simplify and expand its functionality, contains a code analysis scheme, a prohibition scheme, additional code analysis gates and a coincidence circuit, with the code analysis circuit inputs connected to the trigger outputs of the bit switch and the reference sequence source, and code analysis circuits are connected to a synchronization unit and a phase difference converter; the output of the inhibit circuit

connected to the installation input "minus one unit of the converter counter, and the inputs of this circuit are connected to the discharge switch and the output of the coincidence circuit, the inputs of which are connected to the output of the synchronization unit and the output of the sign trigger, the first inputs of the additional code analysis gates Duplex pulse counter, the valve outputs are connected to the bit switch and to the second inputs of the additional code analysis gate of each next bit, the second input is the input l additional code analysis

the low order bit is connected to the output of the reference sequence source.

Pa figs. I presents the block diagram of the proposed device; in fig. 2 - conversion of the phase-pulse code to direct and additional.

The following notation is taken: Part 1 of the up / down counter is known; input device 2 direct invoice; the input device 3 of the count; push-pull generator 4 clock pulses; source 5 reference sequence; delay circuit 6; phase pulse multistable element 7; scheme 8 matches; Expanded: itel 9 pulses; “OR 10; schemes 11, 12 coincidence; trigger 13 characters; known part 14

output devices; switch 15 bits; control unit 16; counter-converter 17; the converter 18 phase difference in the number of pulse code; block 19 synchronization; delay circuit 20; display device 21; code analysis circuit 22; circuits 23-24 matches; gate 25 analysis of additional code; schemes 26, 27 matches; scheme 28 of the ban.

The known part 1 of the counter consists of input devices for forward 2 and reverse counting 3, a push-pull generator of 4 clock pulses, a source 5 of the reference sequence, delay elements 6 and a corresponding number of bits, each of which contains a pulse-phase multi-stable element 7, coincidence circuit 8, a spreader 9 pulses and a three-input circuit "OR 10 combining; in addition, the counter contains schemes 11 and 12 of match and trigger 13 characters.

The known part 14 of the output device consists of a switch 15 bits, a control unit 16, a converter counter 17, a phase difference converter 18 into a number of a pulse code, a synchronization unit 19, a delay circuit 20, and a display device 21. In addition, the counter contains a code analysis circuit 22 with a matching circuit 23 and 24, an additional code analysis gate 25 with a match circuit 26 and 27 and a prohibition circuit 28.

The device works as follows.

After the pulse "Start of indication (or registration)" at the input of control unit 16, pulses appear at its control output. The first pulse will set the synchronization unit 19 to the initial state and switch the switch 15 bits. At a positive number, a pulse from the information output of the switch 15 bits will switch the synchronization unit 19 through the open circuit 23, which outputs a single pulse to the phase difference converter 18 to the number of the pulse code and to the input of the closed circuit 27. A pulse of the reference sequence is fed to the second input of the phase difference converter 18 through the second open coincidence circuit 23.

In this way, a time interval is formed that is proportional to the phase difference in the forward code, which is filled with auxiliary clock pulse. With a negative number, the first pulse of the reference sequence through the open circuit 24 matches the timing unit 19, which outputs a single pulse to the phase difference converter 18 in the numbered code and to the input of the open circuit 27 matches. A pulse from the information output of the switch 15 bits is fed to the second input of the converter circuit of the phase difference converter 18 through the second open circuit 24 of coincidence.

In this way, a time interval is formed that is proportional to the phase difference in the additional code, which is filled with the pulses of the auxiliary clock sequence.

FIG. 2, the conversion of the phase-pulse code to the direct and additional codes (up to “10) codes (digit“ 7) is explained. The following symbols are taken: pulses in the auxiliary clock sequence; reference sequence b; information signal e; time interval r proportional to the direct code; time interval d, proportional to the additional code; information signal e in the forward pulse code; information signal in an additional pulse code. When displaying the true values of negative numbers, the low-order information is always converted to an additional code up to "10. Conversion of the information of subsequent bits into an additional code up to "10 is carried out only in the case when all previous bits are in the zero state. If at least one of the previous bits is not in the zero state, then the conversion is performed in the additional code up to "9.

This is achieved by the fact that the counter-converter 17 is preliminarily set to the state "On adding up to 10 and to the state -1 (for a binary counter on four triggers to state 14) -

when supplementing to “9 with the help of the additional code analysis valve 25 The valve 25 operates as follows. At the inputs of all the coincidence circuits 26, information signals of the corresponding bits are received. The signals of the reference sequence are fed to the input of the low-order match circuit 26. The output of the low-order matching circuit 26 is connected to the input of the next-matching matching circuit 26 and the switch input of the bits 15. The outputs of the remaining matching circuits 26 are connected in the same way.

The switch 15 bits each polling pulse simultaneously switches the information output of the next bit of the element 7 and the output of the previous bit matching circuit 26.

If the previous bits of the phase-impulse-resistant element 7 are in

the zero state, then from the second output of the switch 15 bits, the signal in-phase with zero reference sequence prohibits in the inhibitor circuit 28 a single pulse coming from the synchronization unit 19 via the open circuit 27 coincidence. If at least one of the previous bits of element 7 is not in the zero state, then at the second output of the switch 15 bits there are no signals, and a single pulse with

The synchronization and interdiction unit 28 will open the synchronization unit 19 through the counter-converter 17 to the state minus one.

Subject invention

A reversible pulse counter on phase-pulse multi-stable elements, containing a reference sequence source, a character trigger, a synchronization unit, a phase difference converter, a counter-converter and a bit switch, characterized in that, in order to simplify the device and extend the functionality, it contains a code analysis circuit , a prohibition scheme, additional code analysis gates, and a coincidence circuit, and the inputs of the code analysis circuit are connected to the outputs of the sign trigger, bit switch and source the reference sequence, and the outputs of the code analysis circuit are connected to the synchronization unit and the phase difference converter, the output of the inhibit circuit is connected to the installation input minus the unit of the conversion meter, and the inputs of this circuit are connected to the bit switch and the output of the coincidence circuit, whose inputs are connected with the output of the synchronization unit and with the output of the sign trigger, the first inputs of the additional code analysis gates are connected to the information outputs of the corresponding bits of the reversible pulse counter, the outputs the gates are connected to the switch of bits and with the second inputs of the gates of the additional code analysis for each next bit, the second input of the gates of the additional code analysis is connected to the output of the reference sequence source.

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