SU374738A1 - DECIMAL ACCOUNT! ^ W ^ 'l ^' l-l'i ^, r ^ - ^ l ^^] '- (.'- ^. - Google Patents

Description

The invention relates to the field of automation and computing.

A decimal counter is known, containing triggers, made on memory elements with non-destructive readout, such as transfluxors, diode valves, and capacitors.

The purpose of the invention is to reduce the mosh, the number of trigger and read pulses, as well as the simplification of the counter device.

To do this, one output winding of the initial state of the transfluxor of each trigger of the three lower order bits and two output windings of the same transformer of the third level of the higher bit of each decade are connected to the post-serially connected diode and the ondancer, shunty, p1vnNu resistor. The connection points of capacitors and resistors with the output windings form the inputs, and the capacitors, resistors and diodes of the diodes form the outputs of the transfer circuits. The input of one transfer circuit of each trigger is connected to its counting input, the output is connected to the counting input of the next higher discharge trigger in each decade, the input of the second transfer chain of the high-priority trigger is connected to the counting input of the lower discharge trigger, output through diodes to separation cathodes diodes of unlocked in the initial state of the transfluxors of the second and third bit triggers. The windings of reading and setting the triggers in the initial state are connected in series and connected to the corresponding inputs.

counter.

The drawing shows a circuit diagram of one decade of the proposed device. .

The device contains inputs / -3, outputs

 and triggers performed on transfluxors 3i and diodes 141- / 4b and capacitors} 5i- / 54. Each trasfluxor has windings 16i-76.5 - respectively, installation, two switching, readout and

output. The transfluxor / 3i of each discharge also contains an output winding 16, and in the fourth discharge it also has an additional output winding / 67. The output winding of a transfluxor MB / 5) of each bit is connected to a series-connected diode n of a capacitor 15, shunted by a resistor / 7 |, and the output winding 16j is connected to a MS diode and a capacitor 754 shunted by a 7/2 resistor.

The alternating signal from the matching generator is fed continuously from the input 2 of the counter along the serially connected windings 16 of the reading of all transfluxors. With output winding unlocked

transfluxor 13 () each trigger

alternating voltage is supplied through diode 14 (14) to charge accumulative condensation, torus / 52 (15z).

The starting capacitor / 5i of each trigger is charged at its "zero state through diode 14 by the voltage removed from the output winding 16 of the transfluxor / .. The capacitor 15 is charged at the" zero state of high-priority trigger through diode 14 by voltage with an additional output windings 16j. Since the frequency of the reading pulses is chosen more than the frequency of the triggering, the power of the reading, its generator may be small.

In the counting mode, the trigger is switched by closing the charge circuits of the capacitors ISz and 15z through the switching windings 16 and 16y, the transluxors 13 and 13 and the external key connected to the counting input of the trigger and controlled by the source of trigger pulses. The windings 162 and 16 are connected to capacitors / 52 and / 5z, so that the discharge current of capacitor 15 sets the transfluxor to position "1 and the transfluxor to position" O, and the discharge current of capacitor / 5z sets transfluxors / 5, and 13z, respectively, in position "1 and" O.

The diodes are valves in the charge circuit, respectively, capacitors / 5i / 5z, and diodes 14 and 14 separate the discharge circuits of the capacitors 752 and / 5 $. When a trigger pulse arrives at the input 3, an unconditional switch of the first discharge of the decade occurs as a result of the discharge of the capacitor / 52 (/ 5z) of this trigger through the switching windings 16i and / 5z and the external key (input 3). The switching of the trigger of the second discharge of the decade takes place at the moment when the trigger pulse arrives at input 3 in the absence of a charge on the capacitor / 5 of the trigger of the first discharge of the decade. If this trigger is in "O, not in" 1, then the second discharge trigger does not switch, since its storage capacitor does not discharge in a decade, due to the counter-connected voltages of both capacitors. Switching the trigger of the third decade occurs when the first trigger of the first and second digits is found in “1”. The fourth bit trigger is switched in the same way as the first three. The starting capacitor 15 of the transfer circuit is charged at the "zero state of the fourth bit trigger" and does not affect the operation of the circuit until the decade of eight trigger pulses arrives at the input.

The eighth launch impulse sets the position “On the triggers of the three younger bits and the position“ 1 - the fourth discharge trigger of the decade. As a result, the capacitor 15

by the time of arrival of the ninth impulse will be discharged. The ninth pulse stops the triggers of the three lower digits of the decade, since it is possible to discharge their storage capacitors 152, through a discharged capacitor 15, diodes / 5 and / §2, and an external key- Tenth trigger pulse arrives at the counting the inputs of all four triggers and the output are 4 decades, since the capacitors / 5i of each trigger have no charge. As a result, all the triggers of the decade are set to " O and the transfer output receives a transfer pulse in the next decade.

Outputs 5-12 are used to output information to external circuits.

Resistors / 7i and P provide the discharge of the starting capacitors in the intervals between the starting pulses and when the corresponding transfluxor of the trigger is blocked.

Subject invention

A decanter counter containing triggers made on memory elements with non-destructive readout, such as transfluxors, diode valves and capacitors, characterized in that, in order to reduce the power of the trigger and read pulses, as well as to simplify the counter, one output winding unlocked in its original state transfluxor of each trigger of the three lower-order bits and two output windings of the same transfluxor of the highest-order trigger of each decade are connected to a series of connected diode capacitor shunted by a resistor, the connection points of resistors and capacitors with vyhodnmi windings form inputs, and the points of the compounds of capacitors, resistors, diodes and anodes - outputs transport chains; the input of one transfer chain of each trigger is connected to the counting input of this trigger, the output of each specified transfer chain is connected to the counting input of the next higher discharge trigger, the input of the second transfer chain of the high-priority trigger of each decade is connected to the counting input of the lower trigger trigger of this decade, output This transfer chain is connected via diodes to the cathodes of the separation diodes of the transfluxors of the triggers of the second and third bits of this decade unlocked in the initial state, and the read windings and Fitting bmotki trigger to its original state are connected in series and are connected to respective inputs of the counter.